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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 - 2006 Jakub Jermar |
2 | * Copyright (C) 2005 - 2006 Jakub Jermar |
3 | * Copyright (C) 2006 Jakub Vana |
3 | * Copyright (C) 2006 Jakub Vana |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | #ifndef __ia64_PAGE_H__ |
30 | #ifndef __ia64_PAGE_H__ |
31 | #define __ia64_PAGE_H__ |
31 | #define __ia64_PAGE_H__ |
32 | 32 | ||
33 | #include <arch/mm/frame.h> |
33 | #include <arch/mm/frame.h> |
34 | #include <genarch/mm/page_ht.h> |
34 | #include <genarch/mm/page_ht.h> |
35 | #include <arch/mm/asid.h> |
35 | #include <arch/mm/asid.h> |
36 | #include <arch/types.h> |
36 | #include <arch/types.h> |
37 | #include <typedefs.h> |
37 | #include <typedefs.h> |
38 | #include <debug.h> |
38 | #include <debug.h> |
39 | 39 | ||
40 | #define PAGE_SIZE FRAME_SIZE |
40 | #define PAGE_SIZE FRAME_SIZE |
41 | #define PAGE_WIDTH FRAME_WIDTH |
41 | #define PAGE_WIDTH FRAME_WIDTH |
42 | 42 | ||
43 | #define KA2PA(x) ((__address) (x)) |
43 | #define KA2PA(x) ((__address) (x)) |
44 | #define PA2KA(x) ((__address) (x)) |
44 | #define PA2KA(x) ((__address) (x)) |
45 | 45 | ||
46 | #define SET_PTL0_ADDRESS_ARCH(x) /**< To be removed as situation permits. */ |
46 | #define SET_PTL0_ADDRESS_ARCH(x) /**< To be removed as situation permits. */ |
47 | 47 | ||
48 | /** Implementation of page hash table interface. */ |
- | |
49 | #define HT_WIDTH_ARCH 20 /* 1M */ |
- | |
50 | #define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid)) |
- | |
51 | #define HT_COMPARE_ARCH(page, asid, t) vhpt_compare((page), (asid), (t)) |
- | |
52 | #define HT_SLOT_EMPTY_ARCH(t) ((t)->present.tag.tag_info.ti) |
- | |
53 | #define HT_INVALIDATE_SLOT_ARCH(t) (t)->present.tag.tag_info.ti = true |
- | |
54 | #define HT_GET_NEXT_ARCH(t) (t)->present.next |
- | |
55 | #define HT_SET_NEXT_ARCH(t, s) (t)->present.next = (s) |
- | |
56 | #define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags) |
- | |
57 | - | ||
58 | #define PPN_SHIFT 12 |
48 | #define PPN_SHIFT 12 |
59 | 49 | ||
60 | #define VRN_SHIFT 61 |
50 | #define VRN_SHIFT 61 |
61 | #define VRN_MASK (7LL << VRN_SHIFT) |
51 | #define VRN_MASK (7LL << VRN_SHIFT) |
62 | #define VRN_KERNEL 0 |
52 | #define VRN_KERNEL 0 |
63 | #define REGION_REGISTERS 8 |
53 | #define REGION_REGISTERS 8 |
64 | 54 | ||
65 | #define VHPT_WIDTH 20 /* 1M */ |
55 | #define VHPT_WIDTH 20 /* 1M */ |
66 | #define VHPT_SIZE (1<<VHPT_WIDTH) |
56 | #define VHPT_SIZE (1 << VHPT_WIDTH) |
67 | #define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */ |
57 | #define VHPT_BASE 0 /* Must be aligned to VHPT_SIZE */ |
68 | 58 | ||
69 | #define PTA_BASE_SHIFT 15 |
59 | #define PTA_BASE_SHIFT 15 |
70 | 60 | ||
71 | /** Memory Attributes. */ |
61 | /** Memory Attributes. */ |
72 | #define MA_WRITEBACK 0x0 |
62 | #define MA_WRITEBACK 0x0 |
73 | #define MA_UNCACHEABLE 0x4 |
63 | #define MA_UNCACHEABLE 0x4 |
74 | 64 | ||
75 | /** Privilege Levels. Only the most and the least privileged ones are ever used. */ |
65 | /** Privilege Levels. Only the most and the least privileged ones are ever used. */ |
76 | #define PL_KERNEL 0x0 |
66 | #define PL_KERNEL 0x0 |
77 | #define PL_USER 0x3 |
67 | #define PL_USER 0x3 |
78 | 68 | ||
79 | /* Access Rigths. Only certain combinations are used by the kernel. */ |
69 | /* Access Rigths. Only certain combinations are used by the kernel. */ |
80 | #define AR_READ 0x0 |
70 | #define AR_READ 0x0 |
81 | #define AR_EXECUTE 0x1 |
71 | #define AR_EXECUTE 0x1 |
82 | #define AR_WRITE 0x2 |
72 | #define AR_WRITE 0x2 |
83 | 73 | ||
84 | struct vhpt_tag_info { |
74 | struct vhpt_tag_info { |
85 | unsigned long long tag : 63; |
75 | unsigned long long tag : 63; |
86 | unsigned ti : 1; |
76 | unsigned ti : 1; |
87 | } __attribute__ ((packed)); |
77 | } __attribute__ ((packed)); |
88 | 78 | ||
89 | union vhpt_tag { |
79 | union vhpt_tag { |
90 | struct vhpt_tag_info tag_info; |
80 | struct vhpt_tag_info tag_info; |
91 | unsigned tag_word; |
81 | unsigned tag_word; |
92 | }; |
82 | }; |
93 | 83 | ||
94 | struct vhpt_entry_present { |
84 | struct vhpt_entry_present { |
95 | /* Word 0 */ |
85 | /* Word 0 */ |
96 | unsigned p : 1; |
86 | unsigned p : 1; |
97 | unsigned : 1; |
87 | unsigned : 1; |
98 | unsigned ma : 3; |
88 | unsigned ma : 3; |
99 | unsigned a : 1; |
89 | unsigned a : 1; |
100 | unsigned d : 1; |
90 | unsigned d : 1; |
101 | unsigned pl : 2; |
91 | unsigned pl : 2; |
102 | unsigned ar : 3; |
92 | unsigned ar : 3; |
103 | unsigned long long ppn : 38; |
93 | unsigned long long ppn : 38; |
104 | unsigned : 2; |
94 | unsigned : 2; |
105 | unsigned ed : 1; |
95 | unsigned ed : 1; |
106 | unsigned ig1 : 11; |
96 | unsigned ig1 : 11; |
107 | 97 | ||
108 | /* Word 1 */ |
98 | /* Word 1 */ |
109 | unsigned : 2; |
99 | unsigned : 2; |
110 | unsigned ps : 6; |
100 | unsigned ps : 6; |
111 | unsigned key : 24; |
101 | unsigned key : 24; |
112 | unsigned : 32; |
102 | unsigned : 32; |
113 | 103 | ||
114 | /* Word 2 */ |
104 | /* Word 2 */ |
115 | union vhpt_tag tag; |
105 | union vhpt_tag tag; |
116 | 106 | ||
117 | /* Word 3 */ |
107 | /* Word 3 */ |
118 | pte_t *next; /**< Collision chain next pointer. */ |
108 | __u64 ig3 : 64; |
119 | } __attribute__ ((packed)); |
109 | } __attribute__ ((packed)); |
120 | 110 | ||
121 | struct vhpt_entry_not_present { |
111 | struct vhpt_entry_not_present { |
122 | /* Word 0 */ |
112 | /* Word 0 */ |
123 | unsigned p : 1; |
113 | unsigned p : 1; |
124 | unsigned long long ig0 : 52; |
114 | unsigned long long ig0 : 52; |
125 | unsigned ig1 : 11; |
115 | unsigned ig1 : 11; |
126 | 116 | ||
127 | /* Word 1 */ |
117 | /* Word 1 */ |
128 | unsigned : 2; |
118 | unsigned : 2; |
129 | unsigned ps : 6; |
119 | unsigned ps : 6; |
130 | unsigned long long ig2 : 56; |
120 | unsigned long long ig2 : 56; |
131 | 121 | ||
132 | /* Word 2 */ |
122 | /* Word 2 */ |
133 | union vhpt_tag tag; |
123 | union vhpt_tag tag; |
134 | 124 | ||
135 | /* Word 3 */ |
125 | /* Word 3 */ |
136 | pte_t *next; /**< Collision chain next pointer. */ |
126 | __u64 ig3 : 64; |
137 | - | ||
138 | } __attribute__ ((packed)); |
127 | } __attribute__ ((packed)); |
139 | 128 | ||
140 | typedef union vhpt_entry { |
129 | typedef union vhpt_entry { |
141 | struct vhpt_entry_present present; |
130 | struct vhpt_entry_present present; |
142 | struct vhpt_entry_not_present not_present; |
131 | struct vhpt_entry_not_present not_present; |
143 | __u64 word[4]; |
132 | __u64 word[4]; |
144 | } vhpt_entry; |
133 | } vhpt_entry_t; |
145 | 134 | ||
146 | struct region_register_map { |
135 | struct region_register_map { |
147 | unsigned ve : 1; |
136 | unsigned ve : 1; |
148 | unsigned : 1; |
137 | unsigned : 1; |
149 | unsigned ps : 6; |
138 | unsigned ps : 6; |
150 | unsigned rid : 24; |
139 | unsigned rid : 24; |
151 | unsigned : 32; |
140 | unsigned : 32; |
152 | } __attribute__ ((packed)); |
141 | } __attribute__ ((packed)); |
153 | 142 | ||
154 | typedef union region_register { |
143 | typedef union region_register { |
155 | struct region_register_map map; |
144 | struct region_register_map map; |
156 | unsigned long long word; |
145 | unsigned long long word; |
157 | } region_register; |
146 | } region_register; |
158 | 147 | ||
159 | struct pta_register_map { |
148 | struct pta_register_map { |
160 | unsigned ve : 1; |
149 | unsigned ve : 1; |
161 | unsigned : 1; |
150 | unsigned : 1; |
162 | unsigned size : 6; |
151 | unsigned size : 6; |
163 | unsigned vf : 1; |
152 | unsigned vf : 1; |
164 | unsigned : 6; |
153 | unsigned : 6; |
165 | unsigned long long base : 49; |
154 | unsigned long long base : 49; |
166 | } __attribute__ ((packed)); |
155 | } __attribute__ ((packed)); |
167 | 156 | ||
168 | typedef union pta_register { |
157 | typedef union pta_register { |
169 | struct pta_register_map map; |
158 | struct pta_register_map map; |
170 | __u64 word; |
159 | __u64 word; |
171 | } pta_register; |
160 | } pta_register; |
172 | 161 | ||
173 | /** Return Translation Hashed Entry Address. |
162 | /** Return Translation Hashed Entry Address. |
174 | * |
163 | * |
175 | * VRN bits are used to read RID (ASID) from one |
164 | * VRN bits are used to read RID (ASID) from one |
176 | * of the eight region registers registers. |
165 | * of the eight region registers registers. |
177 | * |
166 | * |
178 | * @param va Virtual address including VRN bits. |
167 | * @param va Virtual address including VRN bits. |
179 | * |
168 | * |
180 | * @return Address of the head of VHPT collision chain. |
169 | * @return Address of the head of VHPT collision chain. |
181 | */ |
170 | */ |
182 | static inline __u64 thash(__u64 va) |
171 | static inline __u64 thash(__u64 va) |
183 | { |
172 | { |
184 | __u64 ret; |
173 | __u64 ret; |
185 | 174 | ||
186 | __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
175 | __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
187 | 176 | ||
188 | return ret; |
177 | return ret; |
189 | } |
178 | } |
190 | 179 | ||
191 | /** Return Translation Hashed Entry Tag. |
180 | /** Return Translation Hashed Entry Tag. |
192 | * |
181 | * |
193 | * VRN bits are used to read RID (ASID) from one |
182 | * VRN bits are used to read RID (ASID) from one |
194 | * of the eight region registers. |
183 | * of the eight region registers. |
195 | * |
184 | * |
196 | * @param va Virtual address including VRN bits. |
185 | * @param va Virtual address including VRN bits. |
197 | * |
186 | * |
198 | * @return The unique tag for VPN and RID in the collision chain returned by thash(). |
187 | * @return The unique tag for VPN and RID in the collision chain returned by thash(). |
199 | */ |
188 | */ |
200 | static inline __u64 ttag(__u64 va) |
189 | static inline __u64 ttag(__u64 va) |
201 | { |
190 | { |
202 | __u64 ret; |
191 | __u64 ret; |
203 | 192 | ||
204 | __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
193 | __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
205 | 194 | ||
206 | return ret; |
195 | return ret; |
207 | } |
196 | } |
208 | 197 | ||
209 | /** Read Region Register. |
198 | /** Read Region Register. |
210 | * |
199 | * |
211 | * @param i Region register index. |
200 | * @param i Region register index. |
212 | * |
201 | * |
213 | * @return Current contents of rr[i]. |
202 | * @return Current contents of rr[i]. |
214 | */ |
203 | */ |
215 | static inline __u64 rr_read(index_t i) |
204 | static inline __u64 rr_read(index_t i) |
216 | { |
205 | { |
217 | __u64 ret; |
206 | __u64 ret; |
218 | 207 | ||
219 | ASSERT(i < REGION_REGISTERS); |
208 | ASSERT(i < REGION_REGISTERS); |
220 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i)); |
209 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i)); |
221 | 210 | ||
222 | return ret; |
211 | return ret; |
223 | } |
212 | } |
224 | 213 | ||
225 | 214 | ||
226 | /** Write Region Register. |
215 | /** Write Region Register. |
227 | * |
216 | * |
228 | * @param i Region register index. |
217 | * @param i Region register index. |
229 | * @param v Value to be written to rr[i]. |
218 | * @param v Value to be written to rr[i]. |
230 | */ |
219 | */ |
231 | static inline void rr_write(index_t i, __u64 v) |
220 | static inline void rr_write(index_t i, __u64 v) |
232 | { |
221 | { |
233 | ASSERT(i < REGION_REGISTERS); |
222 | ASSERT(i < REGION_REGISTERS); |
234 | __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v)); |
223 | __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v)); |
235 | } |
224 | } |
236 | 225 | ||
237 | /** Read Page Table Register. |
226 | /** Read Page Table Register. |
238 | * |
227 | * |
239 | * @return Current value stored in PTA. |
228 | * @return Current value stored in PTA. |
240 | */ |
229 | */ |
241 | static inline __u64 pta_read(void) |
230 | static inline __u64 pta_read(void) |
242 | { |
231 | { |
243 | __u64 ret; |
232 | __u64 ret; |
244 | 233 | ||
245 | __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
234 | __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
246 | 235 | ||
247 | return ret; |
236 | return ret; |
248 | } |
237 | } |
249 | 238 | ||
250 | /** Write Page Table Register. |
239 | /** Write Page Table Register. |
251 | * |
240 | * |
252 | * @param v New value to be stored in PTA. |
241 | * @param v New value to be stored in PTA. |
253 | */ |
242 | */ |
254 | static inline void pta_write(__u64 v) |
243 | static inline void pta_write(__u64 v) |
255 | { |
244 | { |
256 | __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); |
245 | __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); |
257 | } |
246 | } |
258 | 247 | ||
259 | extern void page_arch_init(void); |
248 | extern void page_arch_init(void); |
- | 249 | ||
260 | extern pte_t *vhpt_hash(__address page, asid_t asid); |
250 | extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid); |
261 | extern bool vhpt_compare(__address page, asid_t asid, pte_t *t); |
251 | extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v); |
262 | extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags); |
252 | extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags); |
263 | 253 | ||
264 | #endif |
254 | #endif |
265 | 255 |