Rev 532 | Rev 746 | Go to most recent revision | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 532 | Rev 534 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __ia64_ASM_H__ |
29 | #ifndef __ia64_ASM_H__ |
30 | #define __ia64_ASM_H__ |
30 | #define __ia64_ASM_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <config.h> |
33 | #include <config.h> |
34 | #include <arch/register.h> |
34 | #include <arch/register.h> |
35 | 35 | ||
36 | /** Return base address of current stack |
36 | /** Return base address of current stack |
37 | * |
37 | * |
38 | * Return the base address of the current stack. |
38 | * Return the base address of the current stack. |
39 | * The stack is assumed to be STACK_SIZE long. |
39 | * The stack is assumed to be STACK_SIZE long. |
40 | * The stack must start on page boundary. |
40 | * The stack must start on page boundary. |
41 | */ |
41 | */ |
42 | static inline __address get_stack_base(void) |
42 | static inline __address get_stack_base(void) |
43 | { |
43 | { |
44 | __u64 v; |
44 | __u64 v; |
45 | 45 | ||
46 | __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
46 | __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
47 | 47 | ||
48 | return v; |
48 | return v; |
49 | } |
49 | } |
50 | 50 | ||
51 | /** Read IVA (Interruption Vector Address). |
51 | /** Read IVA (Interruption Vector Address). |
52 | * |
52 | * |
53 | * @return Return location of interruption vector table. |
53 | * @return Return location of interruption vector table. |
54 | */ |
54 | */ |
55 | static inline __u64 iva_read(void) |
55 | static inline __u64 iva_read(void) |
56 | { |
56 | { |
57 | __u64 v; |
57 | __u64 v; |
58 | 58 | ||
59 | __asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v)); |
59 | __asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v)); |
60 | 60 | ||
61 | return v; |
61 | return v; |
62 | } |
62 | } |
63 | 63 | ||
64 | /** Write IVA (Interruption Vector Address) register. |
64 | /** Write IVA (Interruption Vector Address) register. |
65 | * |
65 | * |
66 | * @param New location of interruption vector table. |
66 | * @param New location of interruption vector table. |
67 | */ |
67 | */ |
68 | static inline void iva_write(__u64 v) |
68 | static inline void iva_write(__u64 v) |
69 | { |
69 | { |
70 | __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v)); |
70 | __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v)); |
71 | } |
71 | } |
72 | 72 | ||
73 | 73 | ||
74 | /** Read IVR (External Interrupt Vector Register). |
74 | /** Read IVR (External Interrupt Vector Register). |
75 | * |
75 | * |
76 | * @return Highest priority, pending, unmasked external interrupt vector. |
76 | * @return Highest priority, pending, unmasked external interrupt vector. |
77 | */ |
77 | */ |
78 | static inline __u64 ivr_read(void) |
78 | static inline __u64 ivr_read(void) |
79 | { |
79 | { |
80 | __u64 v; |
80 | __u64 v; |
81 | 81 | ||
82 | __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v)); |
82 | __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v)); |
83 | 83 | ||
84 | return v; |
84 | return v; |
85 | } |
85 | } |
86 | 86 | ||
87 | /** Write ITC (Interval Timer Counter) register. |
87 | /** Write ITC (Interval Timer Counter) register. |
88 | * |
88 | * |
89 | * @param New counter value. |
89 | * @param New counter value. |
90 | */ |
90 | */ |
91 | static inline void itc_write(__u64 v) |
91 | static inline void itc_write(__u64 v) |
92 | { |
92 | { |
93 | __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); |
93 | __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); |
94 | } |
94 | } |
95 | 95 | ||
96 | /** Read ITC (Interval Timer Counter) register. |
96 | /** Read ITC (Interval Timer Counter) register. |
97 | * |
97 | * |
98 | * @return Current counter value. |
98 | * @return Current counter value. |
99 | */ |
99 | */ |
100 | static inline __u64 itc_read(void) |
100 | static inline __u64 itc_read(void) |
101 | { |
101 | { |
102 | __u64 v; |
102 | __u64 v; |
103 | 103 | ||
104 | __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v)); |
104 | __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v)); |
105 | 105 | ||
106 | return v; |
106 | return v; |
107 | } |
107 | } |
108 | 108 | ||
109 | /** Write ITM (Interval Timer Match) register. |
109 | /** Write ITM (Interval Timer Match) register. |
110 | * |
110 | * |
111 | * @param New match value. |
111 | * @param New match value. |
112 | */ |
112 | */ |
113 | static inline void itm_write(__u64 v) |
113 | static inline void itm_write(__u64 v) |
114 | { |
114 | { |
115 | __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); |
115 | __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); |
116 | } |
116 | } |
117 | 117 | ||
118 | /** Read ITV (Interval Timer Vector) register. |
118 | /** Read ITV (Interval Timer Vector) register. |
119 | * |
119 | * |
120 | * @return Current vector and mask bit. |
120 | * @return Current vector and mask bit. |
121 | */ |
121 | */ |
122 | static inline __u64 itv_read(void) |
122 | static inline __u64 itv_read(void) |
123 | { |
123 | { |
124 | __u64 v; |
124 | __u64 v; |
125 | 125 | ||
126 | __asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v)); |
126 | __asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v)); |
127 | 127 | ||
128 | return v; |
128 | return v; |
129 | } |
129 | } |
130 | 130 | ||
131 | /** Write ITV (Interval Timer Vector) register. |
131 | /** Write ITV (Interval Timer Vector) register. |
132 | * |
132 | * |
133 | * @param New vector and mask bit. |
133 | * @param New vector and mask bit. |
134 | */ |
134 | */ |
135 | static inline void itv_write(__u64 v) |
135 | static inline void itv_write(__u64 v) |
136 | { |
136 | { |
137 | __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); |
137 | __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); |
138 | } |
138 | } |
139 | 139 | ||
140 | /** Write EOI (End Of Interrupt) register. |
140 | /** Write EOI (End Of Interrupt) register. |
141 | * |
141 | * |
142 | * @param This value is ignored. |
142 | * @param This value is ignored. |
143 | */ |
143 | */ |
144 | static inline void eoi_write(__u64 v) |
144 | static inline void eoi_write(__u64 v) |
145 | { |
145 | { |
146 | __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
146 | __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
147 | } |
147 | } |
148 | 148 | ||
149 | /** Read TPR (Task Priority Register). |
149 | /** Read TPR (Task Priority Register). |
150 | * |
150 | * |
151 | * @return Current value of TPR. |
151 | * @return Current value of TPR. |
152 | */ |
152 | */ |
153 | static inline __u64 tpr_read(void) |
153 | static inline __u64 tpr_read(void) |
154 | { |
154 | { |
155 | __u64 v; |
155 | __u64 v; |
156 | 156 | ||
157 | __asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v)); |
157 | __asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v)); |
158 | 158 | ||
159 | return v; |
159 | return v; |
160 | } |
160 | } |
161 | 161 | ||
162 | /** Write TPR (Task Priority Register). |
162 | /** Write TPR (Task Priority Register). |
163 | * |
163 | * |
164 | * @param New value of TPR. |
164 | * @param New value of TPR. |
165 | */ |
165 | */ |
166 | static inline void tpr_write(__u64 v) |
166 | static inline void tpr_write(__u64 v) |
167 | { |
167 | { |
168 | __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
168 | __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
169 | } |
169 | } |
170 | 170 | ||
171 | /** Disable interrupts. |
171 | /** Disable interrupts. |
172 | * |
172 | * |
173 | * Disable interrupts and return previous |
173 | * Disable interrupts and return previous |
174 | * value of PSR. |
174 | * value of PSR. |
175 | * |
175 | * |
176 | * @return Old interrupt priority level. |
176 | * @return Old interrupt priority level. |
177 | */ |
177 | */ |
178 | static ipl_t interrupts_disable(void) |
178 | static ipl_t interrupts_disable(void) |
179 | { |
179 | { |
180 | __u64 v; |
180 | __u64 v; |
181 | 181 | ||
182 | __asm__ volatile ( |
182 | __asm__ volatile ( |
183 | "mov %0 = psr\n" |
183 | "mov %0 = psr\n" |
184 | "rsm %1\n" |
184 | "rsm %1\n" |
185 | : "=r" (v) |
185 | : "=r" (v) |
186 | : "i" (PSR_I_MASK) |
186 | : "i" (PSR_I_MASK) |
187 | ); |
187 | ); |
188 | 188 | ||
189 | return (ipl_t) v; |
189 | return (ipl_t) v; |
190 | } |
190 | } |
191 | 191 | ||
192 | /** Enable interrupts. |
192 | /** Enable interrupts. |
193 | * |
193 | * |
194 | * Enable interrupts and return previous |
194 | * Enable interrupts and return previous |
195 | * value of PSR. |
195 | * value of PSR. |
196 | * |
196 | * |
197 | * @return Old interrupt priority level. |
197 | * @return Old interrupt priority level. |
198 | */ |
198 | */ |
199 | static ipl_t interrupts_enable(void) |
199 | static ipl_t interrupts_enable(void) |
200 | { |
200 | { |
201 | __u64 v; |
201 | __u64 v; |
202 | 202 | ||
203 | __asm__ volatile ( |
203 | __asm__ volatile ( |
204 | "mov %0 = psr\n" |
204 | "mov %0 = psr\n" |
205 | "ssm %1\n" |
205 | "ssm %1\n" |
206 | ";;\n" |
206 | ";;\n" |
207 | "srlz.d\n" |
207 | "srlz.d\n" |
208 | : "=r" (v) |
208 | : "=r" (v) |
209 | : "i" (PSR_I_MASK) |
209 | : "i" (PSR_I_MASK) |
210 | ); |
210 | ); |
211 | 211 | ||
212 | return (ipl_t) v; |
212 | return (ipl_t) v; |
213 | } |
213 | } |
214 | 214 | ||
215 | /** Restore interrupt priority level. |
215 | /** Restore interrupt priority level. |
216 | * |
216 | * |
217 | * Restore PSR. |
217 | * Restore PSR. |
218 | * |
218 | * |
219 | * @param ipl Saved interrupt priority level. |
219 | * @param ipl Saved interrupt priority level. |
220 | */ |
220 | */ |
221 | static inline void interrupts_restore(ipl_t ipl) |
221 | static inline void interrupts_restore(ipl_t ipl) |
222 | { |
222 | { |
223 | if (ipl & PSR_I_MASK) |
223 | if (ipl & PSR_I_MASK) |
224 | (void) interrupts_enable(); |
224 | (void) interrupts_enable(); |
225 | else |
225 | else |
226 | (void) interrupts_disable(); |
226 | (void) interrupts_disable(); |
227 | } |
227 | } |
228 | 228 | ||
229 | /** Return interrupt priority level. |
229 | /** Return interrupt priority level. |
230 | * |
230 | * |
231 | * @return PSR. |
231 | * @return PSR. |
232 | */ |
232 | */ |
233 | static inline ipl_t interrupts_read(void) |
233 | static inline ipl_t interrupts_read(void) |
234 | { |
234 | { |
235 | __u64 v; |
235 | __u64 v; |
236 | 236 | ||
237 | __asm__ volatile ("mov %0 = psr\n" : "=r" (v)); |
237 | __asm__ volatile ("mov %0 = psr\n" : "=r" (v)); |
238 | 238 | ||
239 | return (ipl_t) v; |
239 | return (ipl_t) v; |
240 | } |
240 | } |
241 | 241 | ||
242 | extern void cpu_halt(void); |
242 | extern void cpu_halt(void); |
243 | extern void cpu_sleep(void); |
243 | extern void cpu_sleep(void); |
244 | extern void asm_delay_loop(__u32 t); |
244 | extern void asm_delay_loop(__u32 t); |
245 | 245 | ||
246 | #endif |
246 | #endif |
247 | 247 |