WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/smp/apic.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <mm/page.h>
#include <time/delay.h>
#include <interrupt.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef CONFIG_SMP
 
/*
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
 *  VMware Workstation 5.5 with 2 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
static int apic_poll_errors(void);
 
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {
    "Fixed",
    "Lowest Priority",
    "SMI",
    "Reserved",
    "NMI",
    "INIT",
    "STARTUP",
    "ExtInt"
};
 
static char *destmod_str[] = {
    "Physical",
    "Logical"
};
 
static char *trigmod_str[] = {
    "Edge",
    "Level"
};
 
static char *mask_str[] = {
    "Unmasked",
    "Masked"
};
 
static char *delivs_str[] = {
    "Idle",
    "Send Pending"
};
 
static char *tm_mode_str[] = {
    "One-shot",
    "Periodic"
};
 
static char *intpol_str[] = {
    "Polarity High",
    "Polarity Low"
};
#endif /* LAPIC_VERBOSE */
 
 
static void apic_spurious(int n, void *stack);
static void l_apic_timer_interrupt(int n, void *stack);
 
/** Initialize APIC on BSP. */
void apic_init(void)
{
    io_apic_id_t idreg;
    int i;
 
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt);
    for (i = 0; i < IRQ_COUNT; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1) {
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
        }
    }
   
    /*
     * Ensure that io_apic has unique ID.
     */
    idreg.value = io_apic_read(IOAPICID);
    if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
        for (i = 0; i < APIC_ID_COUNT; i++) {
            if (!((1<<i) & apic_id_mask)) {
                idreg.apic_id = i;
                io_apic_write(IOAPICID, idreg.value);
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
 
    l_apic_debug();
}
 
/** APIC spurious interrupt handler.
 *
 * @param n Interrupt vector.
 * @param stack Interrupted stack.
 */
void apic_spurious(int n, void *stack)
{
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
 
/** Poll for APIC errors.
 *
 * Examine Error Status Register and report all errors found.
 *
 * @return 0 on error, 1 on success.
 */
int apic_poll_errors(void)
{
    esr_t esr;
   
    esr.value = l_apic[ESR];
   
    if (esr.send_checksum_error)
        printf("Send Checksum Error\n");
    if (esr.receive_checksum_error)
        printf("Receive Checksum Error\n");
    if (esr.send_accept_error)
        printf("Send Accept Error\n");
    if (esr.receive_accept_error)
        printf("Receive Accept Error\n");
    if (esr.send_illegal_vector)
        printf("Send Illegal Vector\n");
    if (esr.received_illegal_vector)
        printf("Received Illegal Vector\n");
    if (esr.illegal_register_address)
        printf("Illegal Register Address\n");
 
    return !esr.err_bitmap;
}
 
/** Send all CPUs excluding CPU IPI vector.
 *
 * @param vector Interrupt vector to be sent.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_broadcast_custom_ipi(__u8 vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;
    icr.destmod = DESTMOD_LOGIC;
    icr.level = LEVEL_ASSERT;
    icr.shorthand = SHORTHAND_ALL_EXCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = vector;
 
    l_apic[ICRlo] = icr.lo;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING)
        printf("IPI is pending.\n");
 
    return apic_poll_errors();
}
 
/** Universal Start-up Algorithm for bringing up the AP processors.
 *
 * @param apicid APIC ID of the processor to be brought up.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_send_init_ipi(__u8 apicid)
{
    icr_t icr;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    icr.lo = l_apic[ICRlo];
    icr.hi = l_apic[ICRhi];
   
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_ASSERT;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.shorthand = SHORTHAND_NONE;
    icr.vector = 0;
    icr.dest = apicid;
   
    l_apic[ICRhi] = icr.hi;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors()) return 0;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING)
        printf("IPI is pending.\n");
 
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_NONE;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = 0;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;
            l_apic[ICRlo] = icr.lo;
            delay(200);
        }
    }
   
    return apic_poll_errors();
}
 
/** Initialize Local APIC. */
void l_apic_init(void)
{
    lvt_error_t error;
    lvt_lint_t lint;
    svr_t svr;
    icr_t icr;
    tdcr_t tdcr;
    lvt_tm_t tm;
    __u32 t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;
 
    /* Initialize LVT LINT0 register. */
    lint.value = l_apic[LVT_LINT0];
    lint.masked = true;
    l_apic[LVT_LINT0] = lint.value;
 
    /* Initialize LVT LINT1 register. */
    lint.value = l_apic[LVT_LINT1];
    lint.masked = true;
    l_apic[LVT_LINT1] = lint.value;
   
    /* Spurious-Interrupt Vector Register initialization. */
    svr.value = l_apic[SVR];
    svr.vector = VECTOR_APIC_SPUR;
    svr.lapic_enabled = true;
    l_apic[SVR] = svr.value;
 
    l_apic[TPR] &= TPRClear;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    /* Interrupt Command Register initialization. */
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_ALL_INCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    l_apic[ICRlo] = icr.lo;
   
    /* Timer Divide Configuration Register initialization. */
    tdcr.value = l_apic[TDCR];
    tdcr.div_value = DIVIDE_1;
    l_apic[TDCR] = tdcr.value;
 
    /* Program local timer. */
    tm.value = l_apic[LVT_Tm];
    tm.vector = VECTOR_CLK;
    tm.mode = TIMER_PERIODIC;
    tm.masked = false;
    l_apic[LVT_Tm] = tm.value;
 
    /* Measure and configure the timer to generate timer interrupt each ms. */
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
}
 
/** Local APIC End of Interrupt. */
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
/** Dump content of Local APIC registers. */
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    lvt_tm_t tm;
    lvt_lint_t lint;
    lvt_error_t error; 
   
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    tm.value = l_apic[LVT_Tm];
    printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
    lint.value = l_apic[LVT_LINT0];
    printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
    lint.value = l_apic[LVT_LINT1];
    printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);   
    error.value = l_apic[LVT_Err];
    printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
#endif
}
 
/** Local APIC Timer Interrupt.
 *
 * @param n Interrupt vector number.
 * @param stack Interrupted stack.
 */
void l_apic_timer_interrupt(int n, void *stack)
{
    l_apic_eoi();
    clock();
}
 
/** Get Local APIC ID.
 *
 * @return Local APIC ID.
 */
__u8 l_apic_id(void)
{
    l_apic_id_t idreg;
   
    idreg.value = l_apic[L_APIC_ID];
    return idreg.apic_id;
}
 
/** Read from IO APIC register.
 *
 * @param address IO APIC register address.
 *
 * @return Content of the addressed IO APIC register.
 */
__u32 io_apic_read(__u8 address)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    return io_apic[IOWIN];
}
 
/** Write to IO APIC register.
 *
 * @param address IO APIC register address.
 * @param Content to be written to the addressed IO APIC register.
 */
void io_apic_write(__u8 address, __u32 x)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    io_apic[IOWIN] = x;
}
 
/** Change some attributes of one item in I/O Redirection Table.
 *
 * @param pin IO APIC pin number.
 * @param dest Interrupt destination address.
 * @param v Interrupt vector to trigger.
 * @param flags Flags.
 */
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = DELMOD_FIXED;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
   
    reg.lo = io_apic_read(IOREDTBL + pin*2);
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
   
    reg.dest =  dest;
    reg.destmod = DESTMOD_LOGIC;
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + pin*2, reg.lo);
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
}
 
/** Mask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
 */
void io_apic_disable_irqs(__u16 irqmask)
{
    io_redirection_reg_t reg;
    int i, pin;
   
    for (i=0;i<16;i++) {
        if (irqmask & (1<<i)) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
/** Unmask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
 */
void io_apic_enable_irqs(__u16 irqmask)
{
    int i, pin;
    io_redirection_reg_t reg;  
   
    for (i=0;i<16;i++) {
        if (irqmask & (1<<i)) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
#endif /* CONFIG_SMP */
 

Rev 534	Rev 576
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/types.h>	29	#include <arch/types.h>
30	#include <arch/smp/apic.h>	30	#include <arch/smp/apic.h>
31	#include <arch/smp/ap.h>	31	#include <arch/smp/ap.h>
32	#include <arch/smp/mps.h>	32	#include <arch/smp/mps.h>
33	#include <mm/page.h>	33	#include <mm/page.h>
34	#include <time/delay.h>	34	#include <time/delay.h>
-		35	#include <interrupt.h>
35	#include <arch/interrupt.h>	36	#include <arch/interrupt.h>
36	#include <print.h>	37	#include <print.h>
37	#include <arch/asm.h>	38	#include <arch/asm.h>
38	#include <arch.h>	39	#include <arch.h>
39		40
40	#ifdef CONFIG_SMP	41	#ifdef CONFIG_SMP
41		42
42	/*	43	/*
43	* Advanced Programmable Interrupt Controller for SMP systems.	44	* Advanced Programmable Interrupt Controller for SMP systems.
44	* Tested on:	45	* Tested on:
45	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs	46	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
46	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs	47	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
47	* VMware Workstation 5.5 with 2 CPUs	48	* VMware Workstation 5.5 with 2 CPUs
48	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	49	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
49	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	50	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
50	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	51	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
51	*/	52	*/
52		53
53	/*	54	/*
54	* These variables either stay configured as initilalized, or are changed by	55	* These variables either stay configured as initilalized, or are changed by
55	* the MP configuration code.	56	* the MP configuration code.
56	*	57	*
57	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	58	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
58	* optimize the code too much and accesses to l_apic and io_apic, that must	59	* optimize the code too much and accesses to l_apic and io_apic, that must
59	* always be 32-bit, would use byte oriented instructions.	60	* always be 32-bit, would use byte oriented instructions.
60	*/	61	*/
61	volatile __u32 l_apic = (__u32 ) 0xfee00000;	62	volatile __u32 l_apic = (__u32 ) 0xfee00000;
62	volatile __u32 io_apic = (__u32 ) 0xfec00000;	63	volatile __u32 io_apic = (__u32 ) 0xfec00000;
63		64
64	__u32 apic_id_mask = 0;	65	__u32 apic_id_mask = 0;
65		66
66	static int apic_poll_errors(void);	67	static int apic_poll_errors(void);
67		68
68	#ifdef LAPIC_VERBOSE	69	#ifdef LAPIC_VERBOSE
69	static char *delmod_str[] = {	70	static char *delmod_str[] = {
70	"Fixed",	71	"Fixed",
71	"Lowest Priority",	72	"Lowest Priority",
72	"SMI",	73	"SMI",
73	"Reserved",	74	"Reserved",
74	"NMI",	75	"NMI",
75	"INIT",	76	"INIT",
76	"STARTUP",	77	"STARTUP",
77	"ExtInt"	78	"ExtInt"
78	};	79	};
79		80
80	static char *destmod_str[] = {	81	static char *destmod_str[] = {
81	"Physical",	82	"Physical",
82	"Logical"	83	"Logical"
83	};	84	};
84		85
85	static char *trigmod_str[] = {	86	static char *trigmod_str[] = {
86	"Edge",	87	"Edge",
87	"Level"	88	"Level"
88	};	89	};
89		90
90	static char *mask_str[] = {	91	static char *mask_str[] = {
91	"Unmasked",	92	"Unmasked",
92	"Masked"	93	"Masked"
93	};	94	};
94		95
95	static char *delivs_str[] = {	96	static char *delivs_str[] = {
96	"Idle",	97	"Idle",
97	"Send Pending"	98	"Send Pending"
98	};	99	};
99		100
100	static char *tm_mode_str[] = {	101	static char *tm_mode_str[] = {
101	"One-shot",	102	"One-shot",
102	"Periodic"	103	"Periodic"
103	};	104	};
104		105
105	static char *intpol_str[] = {	106	static char *intpol_str[] = {
106	"Polarity High",	107	"Polarity High",
107	"Polarity Low"	108	"Polarity Low"
108	};	109	};
109	#endif /* LAPIC_VERBOSE */	110	#endif /* LAPIC_VERBOSE */
110		111
-		112
-		113	static void apic_spurious(int n, void *stack);
-		114	static void l_apic_timer_interrupt(int n, void *stack);
-		115
111	/** Initialize APIC on BSP. */	116	/** Initialize APIC on BSP. */
112	void apic_init(void)	117	void apic_init(void)
113	{	118	{
114	io_apic_id_t idreg;	119	io_apic_id_t idreg;
115	int i;	120	int i;
116		121
117	trap_register(VECTOR_APIC_SPUR, apic_spurious);	122	exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious);
118		123
119	enable_irqs_function = io_apic_enable_irqs;	124	enable_irqs_function = io_apic_enable_irqs;
120	disable_irqs_function = io_apic_disable_irqs;	125	disable_irqs_function = io_apic_disable_irqs;
121	eoi_function = l_apic_eoi;	126	eoi_function = l_apic_eoi;
122		127
123	/*	128	/*
124	* Configure interrupt routing.	129	* Configure interrupt routing.
125	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	130	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
126	* Other interrupts will be forwarded to the lowest priority CPU.	131	* Other interrupts will be forwarded to the lowest priority CPU.
127	*/	132	*/
128	io_apic_disable_irqs(0xffff);	133	io_apic_disable_irqs(0xffff);
129	trap_register(VECTOR_CLK, l_apic_timer_interrupt);	134	exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt);
130	for (i = 0; i < IRQ_COUNT; i++) {	135	for (i = 0; i < IRQ_COUNT; i++) {
131	int pin;	136	int pin;
132		137
133	if ((pin = smp_irq_to_pin(i)) != -1) {	138	if ((pin = smp_irq_to_pin(i)) != -1) {
134	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);	139	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
135	}	140	}
136	}	141	}
137		142
138	/*	143	/*
139	* Ensure that io_apic has unique ID.	144	* Ensure that io_apic has unique ID.
140	*/	145	*/
141	idreg.value = io_apic_read(IOAPICID);	146	idreg.value = io_apic_read(IOAPICID);
142	if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */	147	if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
143	for (i = 0; i < APIC_ID_COUNT; i++) {	148	for (i = 0; i < APIC_ID_COUNT; i++) {
144	if (!((1<<i) & apic_id_mask)) {	149	if (!((1<<i) & apic_id_mask)) {
145	idreg.apic_id = i;	150	idreg.apic_id = i;
146	io_apic_write(IOAPICID, idreg.value);	151	io_apic_write(IOAPICID, idreg.value);
147	break;	152	break;
148	}	153	}
149	}	154	}
150	}	155	}
151		156
152	/*	157	/*
153	* Configure the BSP's lapic.	158	* Configure the BSP's lapic.
154	*/	159	*/
155	l_apic_init();	160	l_apic_init();
156		161
157	l_apic_debug();	162	l_apic_debug();
158	}	163	}
159		164
160	/** APIC spurious interrupt handler.	165	/** APIC spurious interrupt handler.
161	*	166	*
162	* @param n Interrupt vector.	167	* @param n Interrupt vector.
163	* @param stack Interrupted stack.	168	* @param stack Interrupted stack.
164	*/	169	*/
165	void apic_spurious(__u8 n, __native stack[])	170	void apic_spurious(int n, void *stack)
166	{	171	{
167	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	172	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
168	}	173	}
169		174
170	/** Poll for APIC errors.	175	/** Poll for APIC errors.
171	*	176	*
172	* Examine Error Status Register and report all errors found.	177	* Examine Error Status Register and report all errors found.
173	*	178	*
174	* @return 0 on error, 1 on success.	179	* @return 0 on error, 1 on success.
175	*/	180	*/
176	int apic_poll_errors(void)	181	int apic_poll_errors(void)
177	{	182	{
178	esr_t esr;	183	esr_t esr;
179		184
180	esr.value = l_apic[ESR];	185	esr.value = l_apic[ESR];
181		186
182	if (esr.send_checksum_error)	187	if (esr.send_checksum_error)
183	printf("Send Checksum Error\n");	188	printf("Send Checksum Error\n");
184	if (esr.receive_checksum_error)	189	if (esr.receive_checksum_error)
185	printf("Receive Checksum Error\n");	190	printf("Receive Checksum Error\n");
186	if (esr.send_accept_error)	191	if (esr.send_accept_error)
187	printf("Send Accept Error\n");	192	printf("Send Accept Error\n");
188	if (esr.receive_accept_error)	193	if (esr.receive_accept_error)
189	printf("Receive Accept Error\n");	194	printf("Receive Accept Error\n");
190	if (esr.send_illegal_vector)	195	if (esr.send_illegal_vector)
191	printf("Send Illegal Vector\n");	196	printf("Send Illegal Vector\n");
192	if (esr.received_illegal_vector)	197	if (esr.received_illegal_vector)
193	printf("Received Illegal Vector\n");	198	printf("Received Illegal Vector\n");
194	if (esr.illegal_register_address)	199	if (esr.illegal_register_address)
195	printf("Illegal Register Address\n");	200	printf("Illegal Register Address\n");
196		201
197	return !esr.err_bitmap;	202	return !esr.err_bitmap;
198	}	203	}
199		204
200	/** Send all CPUs excluding CPU IPI vector.	205	/** Send all CPUs excluding CPU IPI vector.
201	*	206	*
202	* @param vector Interrupt vector to be sent.	207	* @param vector Interrupt vector to be sent.
203	*	208	*
204	* @return 0 on failure, 1 on success.	209	* @return 0 on failure, 1 on success.
205	*/	210	*/
206	int l_apic_broadcast_custom_ipi(__u8 vector)	211	int l_apic_broadcast_custom_ipi(__u8 vector)
207	{	212	{
208	icr_t icr;	213	icr_t icr;
209		214
210	icr.lo = l_apic[ICRlo];	215	icr.lo = l_apic[ICRlo];
211	icr.delmod = DELMOD_FIXED;	216	icr.delmod = DELMOD_FIXED;
212	icr.destmod = DESTMOD_LOGIC;	217	icr.destmod = DESTMOD_LOGIC;
213	icr.level = LEVEL_ASSERT;	218	icr.level = LEVEL_ASSERT;
214	icr.shorthand = SHORTHAND_ALL_EXCL;	219	icr.shorthand = SHORTHAND_ALL_EXCL;
215	icr.trigger_mode = TRIGMOD_LEVEL;	220	icr.trigger_mode = TRIGMOD_LEVEL;
216	icr.vector = vector;	221	icr.vector = vector;
217		222
218	l_apic[ICRlo] = icr.lo;	223	l_apic[ICRlo] = icr.lo;
219		224
220	icr.lo = l_apic[ICRlo];	225	icr.lo = l_apic[ICRlo];
221	if (icr.delivs == DELIVS_PENDING)	226	if (icr.delivs == DELIVS_PENDING)
222	printf("IPI is pending.\n");	227	printf("IPI is pending.\n");
223		228
224	return apic_poll_errors();	229	return apic_poll_errors();
225	}	230	}
226		231
227	/** Universal Start-up Algorithm for bringing up the AP processors.	232	/** Universal Start-up Algorithm for bringing up the AP processors.
228	*	233	*
229	* @param apicid APIC ID of the processor to be brought up.	234	* @param apicid APIC ID of the processor to be brought up.
230	*	235	*
231	* @return 0 on failure, 1 on success.	236	* @return 0 on failure, 1 on success.
232	*/	237	*/
233	int l_apic_send_init_ipi(__u8 apicid)	238	int l_apic_send_init_ipi(__u8 apicid)
234	{	239	{
235	icr_t icr;	240	icr_t icr;
236	int i;	241	int i;
237		242
238	/*	243	/*
239	* Read the ICR register in and zero all non-reserved fields.	244	* Read the ICR register in and zero all non-reserved fields.
240	*/	245	*/
241	icr.lo = l_apic[ICRlo];	246	icr.lo = l_apic[ICRlo];
242	icr.hi = l_apic[ICRhi];	247	icr.hi = l_apic[ICRhi];
243		248
244	icr.delmod = DELMOD_INIT;	249	icr.delmod = DELMOD_INIT;
245	icr.destmod = DESTMOD_PHYS;	250	icr.destmod = DESTMOD_PHYS;
246	icr.level = LEVEL_ASSERT;	251	icr.level = LEVEL_ASSERT;
247	icr.trigger_mode = TRIGMOD_LEVEL;	252	icr.trigger_mode = TRIGMOD_LEVEL;
248	icr.shorthand = SHORTHAND_NONE;	253	icr.shorthand = SHORTHAND_NONE;
249	icr.vector = 0;	254	icr.vector = 0;
250	icr.dest = apicid;	255	icr.dest = apicid;
251		256
252	l_apic[ICRhi] = icr.hi;	257	l_apic[ICRhi] = icr.hi;
253	l_apic[ICRlo] = icr.lo;	258	l_apic[ICRlo] = icr.lo;
254		259
255	/*	260	/*
256	* According to MP Specification, 20us should be enough to	261	* According to MP Specification, 20us should be enough to
257	* deliver the IPI.	262	* deliver the IPI.
258	*/	263	*/
259	delay(20);	264	delay(20);
260		265
261	if (!apic_poll_errors()) return 0;	266	if (!apic_poll_errors()) return 0;
262		267
263	icr.lo = l_apic[ICRlo];	268	icr.lo = l_apic[ICRlo];
264	if (icr.delivs == DELIVS_PENDING)	269	if (icr.delivs == DELIVS_PENDING)
265	printf("IPI is pending.\n");	270	printf("IPI is pending.\n");
266		271
267	icr.delmod = DELMOD_INIT;	272	icr.delmod = DELMOD_INIT;
268	icr.destmod = DESTMOD_PHYS;	273	icr.destmod = DESTMOD_PHYS;
269	icr.level = LEVEL_DEASSERT;	274	icr.level = LEVEL_DEASSERT;
270	icr.shorthand = SHORTHAND_NONE;	275	icr.shorthand = SHORTHAND_NONE;
271	icr.trigger_mode = TRIGMOD_LEVEL;	276	icr.trigger_mode = TRIGMOD_LEVEL;
272	icr.vector = 0;	277	icr.vector = 0;
273	l_apic[ICRlo] = icr.lo;	278	l_apic[ICRlo] = icr.lo;
274		279
275	/*	280	/*
276	* Wait 10ms as MP Specification specifies.	281	* Wait 10ms as MP Specification specifies.
277	*/	282	*/
278	delay(10000);	283	delay(10000);
279		284
280	if (!is_82489DX_apic(l_apic[LAVR])) {	285	if (!is_82489DX_apic(l_apic[LAVR])) {
281	/*	286	/*
282	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	287	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
283	*/	288	*/
284	for (i = 0; i<2; i++) {	289	for (i = 0; i<2; i++) {
285	icr.lo = l_apic[ICRlo];	290	icr.lo = l_apic[ICRlo];
286	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */	291	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
287	icr.delmod = DELMOD_STARTUP;	292	icr.delmod = DELMOD_STARTUP;
288	icr.destmod = DESTMOD_PHYS;	293	icr.destmod = DESTMOD_PHYS;
289	icr.level = LEVEL_ASSERT;	294	icr.level = LEVEL_ASSERT;
290	icr.shorthand = SHORTHAND_NONE;	295	icr.shorthand = SHORTHAND_NONE;
291	icr.trigger_mode = TRIGMOD_LEVEL;	296	icr.trigger_mode = TRIGMOD_LEVEL;
292	l_apic[ICRlo] = icr.lo;	297	l_apic[ICRlo] = icr.lo;
293	delay(200);	298	delay(200);
294	}	299	}
295	}	300	}
296		301
297	return apic_poll_errors();	302	return apic_poll_errors();
298	}	303	}
299		304
300	/** Initialize Local APIC. */	305	/** Initialize Local APIC. */
301	void l_apic_init(void)	306	void l_apic_init(void)
302	{	307	{
303	lvt_error_t error;	308	lvt_error_t error;
304	lvt_lint_t lint;	309	lvt_lint_t lint;
305	svr_t svr;	310	svr_t svr;
306	icr_t icr;	311	icr_t icr;
307	tdcr_t tdcr;	312	tdcr_t tdcr;
308	lvt_tm_t tm;	313	lvt_tm_t tm;
309	__u32 t1, t2;	314	__u32 t1, t2;
310		315
311	/* Initialize LVT Error register. */	316	/* Initialize LVT Error register. */
312	error.value = l_apic[LVT_Err];	317	error.value = l_apic[LVT_Err];
313	error.masked = true;	318	error.masked = true;
314	l_apic[LVT_Err] = error.value;	319	l_apic[LVT_Err] = error.value;
315		320
316	/* Initialize LVT LINT0 register. */	321	/* Initialize LVT LINT0 register. */
317	lint.value = l_apic[LVT_LINT0];	322	lint.value = l_apic[LVT_LINT0];
318	lint.masked = true;	323	lint.masked = true;
319	l_apic[LVT_LINT0] = lint.value;	324	l_apic[LVT_LINT0] = lint.value;
320		325
321	/* Initialize LVT LINT1 register. */	326	/* Initialize LVT LINT1 register. */
322	lint.value = l_apic[LVT_LINT1];	327	lint.value = l_apic[LVT_LINT1];
323	lint.masked = true;	328	lint.masked = true;
324	l_apic[LVT_LINT1] = lint.value;	329	l_apic[LVT_LINT1] = lint.value;
325		330
326	/* Spurious-Interrupt Vector Register initialization. */	331	/* Spurious-Interrupt Vector Register initialization. */
327	svr.value = l_apic[SVR];	332	svr.value = l_apic[SVR];
328	svr.vector = VECTOR_APIC_SPUR;	333	svr.vector = VECTOR_APIC_SPUR;
329	svr.lapic_enabled = true;	334	svr.lapic_enabled = true;
330	l_apic[SVR] = svr.value;	335	l_apic[SVR] = svr.value;
331		336
332	l_apic[TPR] &= TPRClear;	337	l_apic[TPR] &= TPRClear;
333		338
334	if (CPU->arch.family >= 6)	339	if (CPU->arch.family >= 6)
335	enable_l_apic_in_msr();	340	enable_l_apic_in_msr();
336		341
337	/* Interrupt Command Register initialization. */	342	/* Interrupt Command Register initialization. */
338	icr.lo = l_apic[ICRlo];	343	icr.lo = l_apic[ICRlo];
339	icr.delmod = DELMOD_INIT;	344	icr.delmod = DELMOD_INIT;
340	icr.destmod = DESTMOD_PHYS;	345	icr.destmod = DESTMOD_PHYS;
341	icr.level = LEVEL_DEASSERT;	346	icr.level = LEVEL_DEASSERT;
342	icr.shorthand = SHORTHAND_ALL_INCL;	347	icr.shorthand = SHORTHAND_ALL_INCL;
343	icr.trigger_mode = TRIGMOD_LEVEL;	348	icr.trigger_mode = TRIGMOD_LEVEL;
344	l_apic[ICRlo] = icr.lo;	349	l_apic[ICRlo] = icr.lo;
345		350
346	/* Timer Divide Configuration Register initialization. */	351	/* Timer Divide Configuration Register initialization. */
347	tdcr.value = l_apic[TDCR];	352	tdcr.value = l_apic[TDCR];
348	tdcr.div_value = DIVIDE_1;	353	tdcr.div_value = DIVIDE_1;
349	l_apic[TDCR] = tdcr.value;	354	l_apic[TDCR] = tdcr.value;
350		355
351	/* Program local timer. */	356	/* Program local timer. */
352	tm.value = l_apic[LVT_Tm];	357	tm.value = l_apic[LVT_Tm];
353	tm.vector = VECTOR_CLK;	358	tm.vector = VECTOR_CLK;
354	tm.mode = TIMER_PERIODIC;	359	tm.mode = TIMER_PERIODIC;
355	tm.masked = false;	360	tm.masked = false;
356	l_apic[LVT_Tm] = tm.value;	361	l_apic[LVT_Tm] = tm.value;
357		362
358	/* Measure and configure the timer to generate timer interrupt each ms. */	363	/* Measure and configure the timer to generate timer interrupt each ms. */
359	t1 = l_apic[CCRT];	364	t1 = l_apic[CCRT];
360	l_apic[ICRT] = 0xffffffff;	365	l_apic[ICRT] = 0xffffffff;
361		366
362	while (l_apic[CCRT] == t1)	367	while (l_apic[CCRT] == t1)
363	;	368	;
364		369
365	t1 = l_apic[CCRT];	370	t1 = l_apic[CCRT];
366	delay(1000);	371	delay(1000);
367	t2 = l_apic[CCRT];	372	t2 = l_apic[CCRT];
368		373
369	l_apic[ICRT] = t1-t2;	374	l_apic[ICRT] = t1-t2;
370	}	375	}
371		376
372	/** Local APIC End of Interrupt. */	377	/** Local APIC End of Interrupt. */
373	void l_apic_eoi(void)	378	void l_apic_eoi(void)
374	{	379	{
375	l_apic[EOI] = 0;	380	l_apic[EOI] = 0;
376	}	381	}
377		382
378	/** Dump content of Local APIC registers. */	383	/** Dump content of Local APIC registers. */
379	void l_apic_debug(void)	384	void l_apic_debug(void)
380	{	385	{
381	#ifdef LAPIC_VERBOSE	386	#ifdef LAPIC_VERBOSE
382	lvt_tm_t tm;	387	lvt_tm_t tm;
383	lvt_lint_t lint;	388	lvt_lint_t lint;
384	lvt_error_t error;	389	lvt_error_t error;
385		390
386	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	391	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
387		392
388	tm.value = l_apic[LVT_Tm];	393	tm.value = l_apic[LVT_Tm];
389	printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);	394	printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
390	lint.value = l_apic[LVT_LINT0];	395	lint.value = l_apic[LVT_LINT0];
391	printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	396	printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
392	lint.value = l_apic[LVT_LINT1];	397	lint.value = l_apic[LVT_LINT1];
393	printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	398	printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
394	error.value = l_apic[LVT_Err];	399	error.value = l_apic[LVT_Err];
395	printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);	400	printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
396	#endif	401	#endif
397	}	402	}
398		403
399	/** Local APIC Timer Interrupt.	404	/** Local APIC Timer Interrupt.
400	*	405	*
401	* @param n Interrupt vector number.	406	* @param n Interrupt vector number.
402	* @param stack Interrupted stack.	407	* @param stack Interrupted stack.
403	*/	408	*/
404	void l_apic_timer_interrupt(__u8 n, __native stack[])	409	void l_apic_timer_interrupt(int n, void *stack)
405	{	410	{
406	l_apic_eoi();	411	l_apic_eoi();
407	clock();	412	clock();
408	}	413	}
409		414
410	/** Get Local APIC ID.	415	/** Get Local APIC ID.
411	*	416	*
412	* @return Local APIC ID.	417	* @return Local APIC ID.
413	*/	418	*/
414	__u8 l_apic_id(void)	419	__u8 l_apic_id(void)
415	{	420	{
416	l_apic_id_t idreg;	421	l_apic_id_t idreg;
417		422
418	idreg.value = l_apic[L_APIC_ID];	423	idreg.value = l_apic[L_APIC_ID];
419	return idreg.apic_id;	424	return idreg.apic_id;
420	}	425	}
421		426
422	/** Read from IO APIC register.	427	/** Read from IO APIC register.
423	*	428	*
424	* @param address IO APIC register address.	429	* @param address IO APIC register address.
425	*	430	*
426	* @return Content of the addressed IO APIC register.	431	* @return Content of the addressed IO APIC register.
427	*/	432	*/
428	__u32 io_apic_read(__u8 address)	433	__u32 io_apic_read(__u8 address)
429	{	434	{
430	io_regsel_t regsel;	435	io_regsel_t regsel;
431		436
432	regsel.value = io_apic[IOREGSEL];	437	regsel.value = io_apic[IOREGSEL];
433	regsel.reg_addr = address;	438	regsel.reg_addr = address;
434	io_apic[IOREGSEL] = regsel.value;	439	io_apic[IOREGSEL] = regsel.value;
435	return io_apic[IOWIN];	440	return io_apic[IOWIN];
436	}	441	}
437		442
438	/** Write to IO APIC register.	443	/** Write to IO APIC register.
439	*	444	*
440	* @param address IO APIC register address.	445	* @param address IO APIC register address.
441	* @param Content to be written to the addressed IO APIC register.	446	* @param Content to be written to the addressed IO APIC register.
442	*/	447	*/
443	void io_apic_write(__u8 address, __u32 x)	448	void io_apic_write(__u8 address, __u32 x)
444	{	449	{
445	io_regsel_t regsel;	450	io_regsel_t regsel;
446		451
447	regsel.value = io_apic[IOREGSEL];	452	regsel.value = io_apic[IOREGSEL];
448	regsel.reg_addr = address;	453	regsel.reg_addr = address;
449	io_apic[IOREGSEL] = regsel.value;	454	io_apic[IOREGSEL] = regsel.value;
450	io_apic[IOWIN] = x;	455	io_apic[IOWIN] = x;
451	}	456	}
452		457
453	/** Change some attributes of one item in I/O Redirection Table.	458	/** Change some attributes of one item in I/O Redirection Table.
454	*	459	*
455	* @param pin IO APIC pin number.	460	* @param pin IO APIC pin number.
456	* @param dest Interrupt destination address.	461	* @param dest Interrupt destination address.
457	* @param v Interrupt vector to trigger.	462	* @param v Interrupt vector to trigger.
458	* @param flags Flags.	463	* @param flags Flags.
459	*/	464	*/
460	void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)	465	void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
461	{	466	{
462	io_redirection_reg_t reg;	467	io_redirection_reg_t reg;
463	int dlvr = DELMOD_FIXED;	468	int dlvr = DELMOD_FIXED;
464		469
465	if (flags & LOPRI)	470	if (flags & LOPRI)
466	dlvr = DELMOD_LOWPRI;	471	dlvr = DELMOD_LOWPRI;
467		472
468		473
469	reg.lo = io_apic_read(IOREDTBL + pin*2);	474	reg.lo = io_apic_read(IOREDTBL + pin*2);
470	reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);	475	reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
471		476
472	reg.dest = dest;	477	reg.dest = dest;
473	reg.destmod = DESTMOD_LOGIC;	478	reg.destmod = DESTMOD_LOGIC;
474	reg.trigger_mode = TRIGMOD_EDGE;	479	reg.trigger_mode = TRIGMOD_EDGE;
475	reg.intpol = POLARITY_HIGH;	480	reg.intpol = POLARITY_HIGH;
476	reg.delmod = dlvr;	481	reg.delmod = dlvr;
477	reg.intvec = v;	482	reg.intvec = v;
478		483
479	io_apic_write(IOREDTBL + pin*2, reg.lo);	484	io_apic_write(IOREDTBL + pin*2, reg.lo);
480	io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);	485	io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
481	}	486	}
482		487
483	/** Mask IRQs in IO APIC.	488	/** Mask IRQs in IO APIC.
484	*	489	*
485	* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).	490	* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
486	*/	491	*/
487	void io_apic_disable_irqs(__u16 irqmask)	492	void io_apic_disable_irqs(__u16 irqmask)
488	{	493	{
489	io_redirection_reg_t reg;	494	io_redirection_reg_t reg;
490	int i, pin;	495	int i, pin;
491		496
492	for (i=0;i<16;i++) {	497	for (i=0;i<16;i++) {
493	if (irqmask & (1<<i)) {	498	if (irqmask & (1<<i)) {
494	/*	499	/*
495	* Mask the signal input in IO APIC if there is a	500	* Mask the signal input in IO APIC if there is a

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(root)/kernel/trunk/arch/ia32/src/smp/apic.c – Rev 534 → 576