WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/smp/apic.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <mm/page.h>
#include <time/delay.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef CONFIG_SMP
 
/*
 
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.14 2-4 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
int apic_poll_errors(void);
 
void apic_init(void)
{
    __u32 tmp, id, i;
 
    trap_register(VECTOR_APIC_SPUR, apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    trap_register(VECTOR_CLK, l_apic_timer_interrupt);
    for (i=0; i<16; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1) {
            io_apic_change_ioredtbl(pin,0xff,IVT_IRQBASE+i,LOPRI);
        }
    }
   
 
    /*
     * Ensure that io_apic has unique ID.
     */
    tmp = io_apic_read(IOAPICID);
    id = (tmp >> 24) & 0xf;
    if ((1<<id) & apic_id_mask) {
        int i;
       
        for (i=0; i<15; i++) {
            if (!((1<<i) & apic_id_mask)) {
                io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
    l_apic_debug();
}
 
void apic_spurious(__u8 n, __native stack[])
{
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
 
int apic_poll_errors(void)
{
    __u32 esr;
   
    esr = l_apic[ESR] & ~ESRClear;
   
    if ((esr>>0) & 1)
        printf("Send CS Error\n");
    if ((esr>>1) & 1)
        printf("Receive CS Error\n");
    if ((esr>>2) & 1)
        printf("Send Accept Error\n");
    if ((esr>>3) & 1)
        printf("Receive Accept Error\n");
    if ((esr>>5) & 1)
        printf("Send Illegal Vector\n");
    if ((esr>>6) & 1)
        printf("Received Illegal Vector\n");
    if ((esr>>7) & 1)
        printf("Illegal Register Address\n");
 
    return !esr;
}
 
/*
 * Send all CPUs excluding CPU IPI vector.
 */
int l_apic_broadcast_custom_ipi(__u8 vector)
{
    __u32 lo;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    lo = l_apic[ICRlo] & ICRloClear;
 
    lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
   
    l_apic[ICRlo] = lo;
 
    lo = l_apic[ICRlo] & ICRloClear;
    if (lo & SEND_PENDING)
        printf("IPI is pending.\n");
 
    return apic_poll_errors();
}
 
/*
 * Universal Start-up Algorithm for bringing up the AP processors.
 */
int l_apic_send_init_ipi(__u8 apicid)
{
    __u32 lo, hi;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    lo = l_apic[ICRlo] & ICRloClear;
    hi = l_apic[ICRhi] & ICRhiClear;
   
    lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
    hi |= apicid << 24;
   
    l_apic[ICRhi] = hi;
    l_apic[ICRlo] = lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors()) return 0;
 
    lo = l_apic[ICRlo] & ICRloClear;
    if (lo & SEND_PENDING)
        printf("IPI is pending.\n");
 
    l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            lo = l_apic[ICRlo] & ICRloClear;
            lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
            l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
            delay(200);
        }
    }
   
   
    return apic_poll_errors();
}
 
void l_apic_init(void)
{
    __u32 tmp, t1, t2;
 
    l_apic[LVT_Err] |= (1<<16);
    l_apic[LVT_LINT0] |= (1<<16);
    l_apic[LVT_LINT1] |= (1<<16);
 
    tmp = l_apic[SVR] & SVRClear;
    l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
 
    l_apic[TPR] &= TPRClear;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    tmp = l_apic[ICRlo] & ICRloClear;
    l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
   
    /*
     * Program the timer for periodic mode and respective vector.
     */
 
    l_apic[TDCR] &= TDCRClear;
    l_apic[TDCR] |= 0xb;
    tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
    l_apic[LVT_Tm] = tmp & ~(1<<16);
 
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
   
}
 
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    int i, lint;
 
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    printf("LVT_Tm: ");
    if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
    if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
    if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
    printf("%B\n", l_apic[LVT_Tm] & 0xff);
   
    for (i=0; i<2; i++) {
        lint = i ? LVT_LINT1 : LVT_LINT0;
        printf("LVT_LINT%d: ", i);
        if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
        if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
        printf("%d", l_apic[lint] & (1<<14)); putchar(',');
        printf("%d", l_apic[lint] & (1<<13)); putchar(',');
        if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
   
        switch ((l_apic[lint]>>8)&7) {
            case 0: printf("fixed"); break;
            case 4: printf("NMI"); break;
            case 7: printf("ExtINT"); break;
        }
        putchar(',');
        printf("%B\n", l_apic[lint] & 0xff);   
    }
 
    printf("LVT_Err: ");
    if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
    if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
    printf("%B\n", l_apic[LVT_Err] & 0xff);
 
    /*
     * This register is supported only on P6 and higher.
     */
    if (CPU->arch.family > 5) {
        printf("LVT_PCINT: ");
        if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
        if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
        switch ((l_apic[LVT_PCINT] >> 8)&7) {
            case 0: printf("fixed"); break;
            case 4: printf("NMI"); break;
            case 7: printf("ExtINT"); break;
        }
        putchar(',');
        printf("%B\n", l_apic[LVT_PCINT] & 0xff);
    }
#endif
}
 
void l_apic_timer_interrupt(__u8 n, __native stack[])
{
    l_apic_eoi();
    clock();
}
 
__u8 l_apic_id(void)
{
    return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
}
 
__u32 io_apic_read(__u8 address)
{
    __u32 tmp;
   
    tmp = io_apic[IOREGSEL] & ~0xf;
    io_apic[IOREGSEL] = tmp | address;
    return io_apic[IOWIN];
}
 
void io_apic_write(__u8 address, __u32 x)
{
    __u32 tmp;
 
    tmp = io_apic[IOREGSEL] & ~0xf;
    io_apic[IOREGSEL] = tmp | address;
    io_apic[IOWIN] = x;
}
 
void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = 0;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
   
    reg.lo = io_apic_read(IOREDTBL + signal*2);
    reg.hi = io_apic_read(IOREDTBL + signal*2 + 1);
   
    reg.dest =  dest;
    reg.destmod = DESTMOD_LOGIC;
 
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + signal*2, reg.lo);
    io_apic_write(IOREDTBL + signal*2 + 1, reg.hi);
}
 
void io_apic_disable_irqs(__u16 irqmask)
{
    io_redirection_reg_t reg;
    int i, pin;
 
   
    for (i=0;i<16;i++) {
        if ((irqmask>>i) & 1) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
void io_apic_enable_irqs(__u16 irqmask)
{
    int i, pin;
    io_redirection_reg_t reg;  
   
    for (i=0;i<16;i++) {
        if ((irqmask>>i) & 1) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
 
}
 
#endif /* CONFIG_SMP */
 

Rev 501	Rev 512
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/types.h>	29	#include <arch/types.h>
30	#include <arch/smp/apic.h>	30	#include <arch/smp/apic.h>
31	#include <arch/smp/ap.h>	31	#include <arch/smp/ap.h>
32	#include <arch/smp/mps.h>	32	#include <arch/smp/mps.h>
33	#include <mm/page.h>	33	#include <mm/page.h>
34	#include <time/delay.h>	34	#include <time/delay.h>
35	#include <arch/interrupt.h>	35	#include <arch/interrupt.h>
36	#include <print.h>	36	#include <print.h>
37	#include <arch/asm.h>	37	#include <arch/asm.h>
38	#include <arch.h>	38	#include <arch.h>
39		39
40	#ifdef CONFIG_SMP	40	#ifdef CONFIG_SMP
41		41
42	/*	42	/*
43	* This is functional, far-from-general-enough interface to the APIC.	-
44	* Advanced Programmable Interrupt Controller for MP systems.	43	* Advanced Programmable Interrupt Controller for SMP systems.
45	* Tested on:	44	* Tested on:
46	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs	45	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
47	* Simics 2.0.28 - Simics 2.2.14 2-4 CPUs	46	* Simics 2.0.28 - Simics 2.2.14 2-4 CPUs
48	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	47	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
49	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	48	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
50	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	49	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
51	*/	50	*/
52		51
53	/*	52	/*
54	* These variables either stay configured as initilalized, or are changed by	53	* These variables either stay configured as initilalized, or are changed by
55	* the MP configuration code.	54	* the MP configuration code.
56	*	55	*
57	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	56	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
58	* optimize the code too much and accesses to l_apic and io_apic, that must	57	* optimize the code too much and accesses to l_apic and io_apic, that must
59	* always be 32-bit, would use byte oriented instructions.	58	* always be 32-bit, would use byte oriented instructions.
60	*/	59	*/
61	volatile __u32 l_apic = (__u32 ) 0xfee00000;	60	volatile __u32 l_apic = (__u32 ) 0xfee00000;
62	volatile __u32 io_apic = (__u32 ) 0xfec00000;	61	volatile __u32 io_apic = (__u32 ) 0xfec00000;
63		62
64	__u32 apic_id_mask = 0;	63	__u32 apic_id_mask = 0;
65		64
66	int apic_poll_errors(void);	65	int apic_poll_errors(void);
67		66
68	void apic_init(void)	67	void apic_init(void)
69	{	68	{
70	__u32 tmp, id, i;	69	__u32 tmp, id, i;
71		70
72	trap_register(VECTOR_APIC_SPUR, apic_spurious);	71	trap_register(VECTOR_APIC_SPUR, apic_spurious);
73		72
74	enable_irqs_function = io_apic_enable_irqs;	73	enable_irqs_function = io_apic_enable_irqs;
75	disable_irqs_function = io_apic_disable_irqs;	74	disable_irqs_function = io_apic_disable_irqs;
76	eoi_function = l_apic_eoi;	75	eoi_function = l_apic_eoi;
77		76
78	/*	77	/*
79	* Configure interrupt routing.	78	* Configure interrupt routing.
80	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	79	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
81	* Other interrupts will be forwarded to the lowest priority CPU.	80	* Other interrupts will be forwarded to the lowest priority CPU.
82	*/	81	*/
83	io_apic_disable_irqs(0xffff);	82	io_apic_disable_irqs(0xffff);
84	trap_register(VECTOR_CLK, l_apic_timer_interrupt);	83	trap_register(VECTOR_CLK, l_apic_timer_interrupt);
85	for (i=1; i<16; i++) {	84	for (i=0; i<16; i++) {
86	int pin;	85	int pin;
87		86
88	if ((pin = mps_irq_to_pin(i)) != -1)	87	if ((pin = smp_irq_to_pin(i)) != -1) {
89	io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);	88	io_apic_change_ioredtbl(pin,0xff,IVT_IRQBASE+i,LOPRI);
-		89	}
90	}	90	}
91		91
92		92
93	/*	93	/*
94	* Ensure that io_apic has unique ID.	94	* Ensure that io_apic has unique ID.
95	*/	95	*/
96	tmp = io_apic_read(IOAPICID);	96	tmp = io_apic_read(IOAPICID);
97	id = (tmp >> 24) & 0xf;	97	id = (tmp >> 24) & 0xf;
98	if ((1<<id) & apic_id_mask) {	98	if ((1<<id) & apic_id_mask) {
99	int i;	99	int i;
100		100
101	for (i=0; i<15; i++) {	101	for (i=0; i<15; i++) {
102	if (!((1<<i) & apic_id_mask)) {	102	if (!((1<<i) & apic_id_mask)) {
103	io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) \| (i<<24));	103	io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) \| (i<<24));
104	break;	104	break;
105	}	105	}
106	}	106	}
107	}	107	}
108		108
109	/*	109	/*
110	* Configure the BSP's lapic.	110	* Configure the BSP's lapic.
111	*/	111	*/
112	l_apic_init();	112	l_apic_init();
113	l_apic_debug();	113	l_apic_debug();
114	}	114	}
115		115
116	void apic_spurious(__u8 n, __native stack[])	116	void apic_spurious(__u8 n, __native stack[])
117	{	117	{
118	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	118	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
119	}	119	}
120		120
121	int apic_poll_errors(void)	121	int apic_poll_errors(void)
122	{	122	{
123	__u32 esr;	123	__u32 esr;
124		124
125	esr = l_apic[ESR] & ~ESRClear;	125	esr = l_apic[ESR] & ~ESRClear;
126		126
127	if ((esr>>0) & 1)	127	if ((esr>>0) & 1)
128	printf("Send CS Error\n");	128	printf("Send CS Error\n");
129	if ((esr>>1) & 1)	129	if ((esr>>1) & 1)
130	printf("Receive CS Error\n");	130	printf("Receive CS Error\n");
131	if ((esr>>2) & 1)	131	if ((esr>>2) & 1)
132	printf("Send Accept Error\n");	132	printf("Send Accept Error\n");
133	if ((esr>>3) & 1)	133	if ((esr>>3) & 1)
134	printf("Receive Accept Error\n");	134	printf("Receive Accept Error\n");
135	if ((esr>>5) & 1)	135	if ((esr>>5) & 1)
136	printf("Send Illegal Vector\n");	136	printf("Send Illegal Vector\n");
137	if ((esr>>6) & 1)	137	if ((esr>>6) & 1)
138	printf("Received Illegal Vector\n");	138	printf("Received Illegal Vector\n");
139	if ((esr>>7) & 1)	139	if ((esr>>7) & 1)
140	printf("Illegal Register Address\n");	140	printf("Illegal Register Address\n");
141		141
142	return !esr;	142	return !esr;
143	}	143	}
144		144
145	/*	145	/*
146	* Send all CPUs excluding CPU IPI vector.	146	* Send all CPUs excluding CPU IPI vector.
147	*/	147	*/
148	int l_apic_broadcast_custom_ipi(__u8 vector)	148	int l_apic_broadcast_custom_ipi(__u8 vector)
149	{	149	{
150	__u32 lo;	150	__u32 lo;
151		151
152	/*	152	/*
153	* Read the ICR register in and zero all non-reserved fields.	153	* Read the ICR register in and zero all non-reserved fields.
154	*/	154	*/
155	lo = l_apic[ICRlo] & ICRloClear;	155	lo = l_apic[ICRlo] & ICRloClear;
156		156
157	lo \|= DLVRMODE_FIXED \| DESTMODE_LOGIC \| LEVEL_ASSERT \| SHORTHAND_EXCL \| TRGRMODE_LEVEL \| vector;	157	lo \|= DLVRMODE_FIXED \| DESTMODE_LOGIC \| LEVEL_ASSERT \| SHORTHAND_EXCL \| TRGRMODE_LEVEL \| vector;
158		158
159	l_apic[ICRlo] = lo;	159	l_apic[ICRlo] = lo;
160		160
161	lo = l_apic[ICRlo] & ICRloClear;	161	lo = l_apic[ICRlo] & ICRloClear;
162	if (lo & SEND_PENDING)	162	if (lo & SEND_PENDING)
163	printf("IPI is pending.\n");	163	printf("IPI is pending.\n");
164		164
165	return apic_poll_errors();	165	return apic_poll_errors();
166	}	166	}
167		167
168	/*	168	/*
169	* Universal Start-up Algorithm for bringing up the AP processors.	169	* Universal Start-up Algorithm for bringing up the AP processors.
170	*/	170	*/
171	int l_apic_send_init_ipi(__u8 apicid)	171	int l_apic_send_init_ipi(__u8 apicid)
172	{	172	{
173	__u32 lo, hi;	173	__u32 lo, hi;
174	int i;	174	int i;
175		175
176	/*	176	/*
177	* Read the ICR register in and zero all non-reserved fields.	177	* Read the ICR register in and zero all non-reserved fields.
178	*/	178	*/
179	lo = l_apic[ICRlo] & ICRloClear;	179	lo = l_apic[ICRlo] & ICRloClear;
180	hi = l_apic[ICRhi] & ICRhiClear;	180	hi = l_apic[ICRhi] & ICRhiClear;
181		181
182	lo \|= DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	182	lo \|= DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
183	hi \|= apicid << 24;	183	hi \|= apicid << 24;
184		184
185	l_apic[ICRhi] = hi;	185	l_apic[ICRhi] = hi;
186	l_apic[ICRlo] = lo;	186	l_apic[ICRlo] = lo;
187		187
188	/*	188	/*
189	* According to MP Specification, 20us should be enough to	189	* According to MP Specification, 20us should be enough to
190	* deliver the IPI.	190	* deliver the IPI.
191	*/	191	*/
192	delay(20);	192	delay(20);
193		193
194	if (!apic_poll_errors()) return 0;	194	if (!apic_poll_errors()) return 0;
195		195
196	lo = l_apic[ICRlo] & ICRloClear;	196	lo = l_apic[ICRlo] & ICRloClear;
197	if (lo & SEND_PENDING)	197	if (lo & SEND_PENDING)
198	printf("IPI is pending.\n");	198	printf("IPI is pending.\n");
199		199
200	l_apic[ICRlo] = lo \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	200	l_apic[ICRlo] = lo \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
201		201
202	/*	202	/*
203	* Wait 10ms as MP Specification specifies.	203	* Wait 10ms as MP Specification specifies.
204	*/	204	*/
205	delay(10000);	205	delay(10000);
206		206
207	if (!is_82489DX_apic(l_apic[LAVR])) {	207	if (!is_82489DX_apic(l_apic[LAVR])) {
208	/*	208	/*
209	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	209	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
210	*/	210	*/
211	for (i = 0; i<2; i++) {	211	for (i = 0; i<2; i++) {
212	lo = l_apic[ICRlo] & ICRloClear;	212	lo = l_apic[ICRlo] & ICRloClear;
213	lo \|= ((__address) ap_boot) / 4096; /* calculate the reset vector */	213	lo \|= ((__address) ap_boot) / 4096; /* calculate the reset vector */
214	l_apic[ICRlo] = lo \| DLVRMODE_STUP \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	214	l_apic[ICRlo] = lo \| DLVRMODE_STUP \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
215	delay(200);	215	delay(200);
216	}	216	}
217	}	217	}
218		218
219		219
220	return apic_poll_errors();	220	return apic_poll_errors();
221	}	221	}
222		222
223	void l_apic_init(void)	223	void l_apic_init(void)
224	{	224	{
225	__u32 tmp, t1, t2;	225	__u32 tmp, t1, t2;
226		226
227	l_apic[LVT_Err] \|= (1<<16);	227	l_apic[LVT_Err] \|= (1<<16);
228	l_apic[LVT_LINT0] \|= (1<<16);	228	l_apic[LVT_LINT0] \|= (1<<16);
229	l_apic[LVT_LINT1] \|= (1<<16);	229	l_apic[LVT_LINT1] \|= (1<<16);
230		230
231	tmp = l_apic[SVR] & SVRClear;	231	tmp = l_apic[SVR] & SVRClear;
232	l_apic[SVR] = tmp \| (1<<8) \| (VECTOR_APIC_SPUR);	232	l_apic[SVR] = tmp \| (1<<8) \| (VECTOR_APIC_SPUR);
233		233
234	l_apic[TPR] &= TPRClear;	234	l_apic[TPR] &= TPRClear;
235		235
236	if (CPU->arch.family >= 6)	236	if (CPU->arch.family >= 6)
237	enable_l_apic_in_msr();	237	enable_l_apic_in_msr();
238		238
239	tmp = l_apic[ICRlo] & ICRloClear;	239	tmp = l_apic[ICRlo] & ICRloClear;
240	l_apic[ICRlo] = tmp \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_INCL \| TRGRMODE_LEVEL;	240	l_apic[ICRlo] = tmp \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_INCL \| TRGRMODE_LEVEL;
241		241
242	/*	242	/*
243	* Program the timer for periodic mode and respective vector.	243	* Program the timer for periodic mode and respective vector.
244	*/	244	*/
245		245
246	l_apic[TDCR] &= TDCRClear;	246	l_apic[TDCR] &= TDCRClear;
247	l_apic[TDCR] \|= 0xb;	247	l_apic[TDCR] \|= 0xb;
248	tmp = l_apic[LVT_Tm] \| (1<<17) \| (VECTOR_CLK);	248	tmp = l_apic[LVT_Tm] \| (1<<17) \| (VECTOR_CLK);
249	l_apic[LVT_Tm] = tmp & ~(1<<16);	249	l_apic[LVT_Tm] = tmp & ~(1<<16);
250		250
251	t1 = l_apic[CCRT];	251	t1 = l_apic[CCRT];
252	l_apic[ICRT] = 0xffffffff;	252	l_apic[ICRT] = 0xffffffff;
253		253
254	while (l_apic[CCRT] == t1)	254	while (l_apic[CCRT] == t1)
255	;	255	;
256		256
257	t1 = l_apic[CCRT];	257	t1 = l_apic[CCRT];
258	delay(1000);	258	delay(1000);
259	t2 = l_apic[CCRT];	259	t2 = l_apic[CCRT];
260		260
261	l_apic[ICRT] = t1-t2;	261	l_apic[ICRT] = t1-t2;
262		262
263	}	263	}
264		264
265	void l_apic_eoi(void)	265	void l_apic_eoi(void)
266	{	266	{
267	l_apic[EOI] = 0;	267	l_apic[EOI] = 0;
268	}	268	}
269		269
270	void l_apic_debug(void)	270	void l_apic_debug(void)
271	{	271	{
272	#ifdef LAPIC_VERBOSE	272	#ifdef LAPIC_VERBOSE
273	int i, lint;	273	int i, lint;
274		274
275	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	275	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
276		276
277	printf("LVT_Tm: ");	277	printf("LVT_Tm: ");
278	if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');	278	if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');
279	if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	279	if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
280	if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	280	if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
281	printf("%B\n", l_apic[LVT_Tm] & 0xff);	281	printf("%B\n", l_apic[LVT_Tm] & 0xff);
282		282
283	for (i=0; i<2; i++) {	283	for (i=0; i<2; i++) {
284	lint = i ? LVT_LINT1 : LVT_LINT0;	284	lint = i ? LVT_LINT1 : LVT_LINT0;
285	printf("LVT_LINT%d: ", i);	285	printf("LVT_LINT%d: ", i);
286	if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	286	if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
287	if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');	287	if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
288	printf("%d", l_apic[lint] & (1<<14)); putchar(',');	288	printf("%d", l_apic[lint] & (1<<14)); putchar(',');
289	printf("%d", l_apic[lint] & (1<<13)); putchar(',');	289	printf("%d", l_apic[lint] & (1<<13)); putchar(',');
290	if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	290	if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
291		291
292	switch ((l_apic[lint]>>8)&7) {	292	switch ((l_apic[lint]>>8)&7) {
293	case 0: printf("fixed"); break;	293	case 0: printf("fixed"); break;
294	case 4: printf("NMI"); break;	294	case 4: printf("NMI"); break;
295	case 7: printf("ExtINT"); break;	295	case 7: printf("ExtINT"); break;
296	}	296	}
297	putchar(',');	297	putchar(',');
298	printf("%B\n", l_apic[lint] & 0xff);	298	printf("%B\n", l_apic[lint] & 0xff);
299	}	299	}
300		300
301	printf("LVT_Err: ");	301	printf("LVT_Err: ");
302	if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	302	if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
303	if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	303	if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
304	printf("%B\n", l_apic[LVT_Err] & 0xff);	304	printf("%B\n", l_apic[LVT_Err] & 0xff);
305		305
306	/*	306	/*
307	* This register is supported only on P6 and higher.	307	* This register is supported only on P6 and higher.
308	*/	308	*/
309	if (CPU->arch.family > 5) {	309	if (CPU->arch.family > 5) {
310	printf("LVT_PCINT: ");	310	printf("LVT_PCINT: ");
311	if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	311	if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
312	if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	312	if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
313	switch ((l_apic[LVT_PCINT] >> 8)&7) {	313	switch ((l_apic[LVT_PCINT] >> 8)&7) {
314	case 0: printf("fixed"); break;	314	case 0: printf("fixed"); break;
315	case 4: printf("NMI"); break;	315	case 4: printf("NMI"); break;
316	case 7: printf("ExtINT"); break;	316	case 7: printf("ExtINT"); break;
317	}	317	}
318	putchar(',');	318	putchar(',');
319	printf("%B\n", l_apic[LVT_PCINT] & 0xff);	319	printf("%B\n", l_apic[LVT_PCINT] & 0xff);
320	}	320	}
321	#endif	321	#endif
322	}	322	}
323		323
324	void l_apic_timer_interrupt(__u8 n, __native stack[])	324	void l_apic_timer_interrupt(__u8 n, __native stack[])
325	{	325	{
326	l_apic_eoi();	326	l_apic_eoi();
327	clock();	327	clock();
328	}	328	}
329		329
330	__u8 l_apic_id(void)	330	__u8 l_apic_id(void)
331	{	331	{
332	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;	332	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
333	}	333	}
334		334
335	__u32 io_apic_read(__u8 address)	335	__u32 io_apic_read(__u8 address)
336	{	336	{
337	__u32 tmp;	337	__u32 tmp;
338		338
339	tmp = io_apic[IOREGSEL] & ~0xf;	339	tmp = io_apic[IOREGSEL] & ~0xf;
340	io_apic[IOREGSEL] = tmp \| address;	340	io_apic[IOREGSEL] = tmp \| address;
341	return io_apic[IOWIN];	341	return io_apic[IOWIN];
342	}	342	}
343		343
344	void io_apic_write(__u8 address, __u32 x)	344	void io_apic_write(__u8 address, __u32 x)
345	{	345	{
346	__u32 tmp;	346	__u32 tmp;
347		347
348	tmp = io_apic[IOREGSEL] & ~0xf;	348	tmp = io_apic[IOREGSEL] & ~0xf;
349	io_apic[IOREGSEL] = tmp \| address;	349	io_apic[IOREGSEL] = tmp \| address;
350	io_apic[IOWIN] = x;	350	io_apic[IOWIN] = x;
351	}	351	}
352		352
353	void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)	353	void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
354	{	354	{
355	__u32 reglo, reghi;	355	io_redirection_reg_t reg;
356	int dlvr = 0;	356	int dlvr = 0;
357		357
358	if (flags & LOPRI)	358	if (flags & LOPRI)
359	dlvr = 1;	359	dlvr = DELMOD_LOWPRI;
-		360
360		361
361	reglo = io_apic_read(IOREDTBL + signal*2);	362	reg.lo = io_apic_read(IOREDTBL + signal*2);
362	reghi = io_apic_read(IOREDTBL + signal*2 + 1);	363	reg.hi = io_apic_read(IOREDTBL + signal*2 + 1);
363		364
364	reghi &= ~0x0f000000;	365	reg.dest = dest;
365	reghi \|= (dest<<24);	366	reg.destmod = DESTMOD_LOGIC;
366		-
367	reglo &= (~0x1ffff) \| (1<<16); /* don't touch the mask */	367	reg.trigger_mode = TRIGMOD_EDGE;
368	reglo \|= (0<<15) \| (0<<13) \| (0<<11) \| (dlvr<<8) \| v;	368	reg.intpol = POLARITY_HIGH;
-		369	reg.delmod = dlvr;
-		370	reg.intvec = v;
369		371
370	io_apic_write(IOREDTBL + signal*2, reglo);	372	io_apic_write(IOREDTBL + signal*2, reg.lo);
371	io_apic_write(IOREDTBL + signal*2 + 1, reghi);	373	io_apic_write(IOREDTBL + signal*2 + 1, reg.hi);
372	}	374	}
373		375
374	void io_apic_disable_irqs(__u16 irqmask)	376	void io_apic_disable_irqs(__u16 irqmask)
375	{	377	{
-		378	io_redirection_reg_t reg;
376	int i,pin;	379	int i, pin;
377	__u32 reglo;	-
378		380
379	for (i=0;i<16;i++) {	381	for (i=0;i<16;i++) {
380	if ((irqmask>>i) & 1) {	382	if ((irqmask>>i) & 1) {
381	/*	383	/*
382	* Mask the signal input in IO APIC if there is a	384	* Mask the signal input in IO APIC if there is a
383	* mapping for the respective IRQ number.	385	* mapping for the respective IRQ number.
384	*/	386	*/
385	pin = mps_irq_to_pin(i);	387	pin = smp_irq_to_pin(i);
386	if (pin != -1) {	388	if (pin != -1) {
387	reglo = io_apic_read(IOREDTBL + pin*2);	389	reg.lo = io_apic_read(IOREDTBL + pin*2);
388	reglo \|= (1<<16);	390	reg.masked = true;
389	io_apic_write(IOREDTBL + pin*2,reglo);	391	io_apic_write(IOREDTBL + pin*2, reg.lo);
390	}	392	}
391		393
392	}	394	}
393	}	395	}
394	}	396	}
395		397
396	void io_apic_enable_irqs(__u16 irqmask)	398	void io_apic_enable_irqs(__u16 irqmask)
397	{	399	{
398	int i,pin;	400	int i, pin;
399	__u32 reglo;	401	io_redirection_reg_t reg;
400		402
401	for (i=0;i<16;i++) {	403	for (i=0;i<16;i++) {
402	if ((irqmask>>i) & 1) {	404	if ((irqmask>>i) & 1) {
403	/*	405	/*
404	* Unmask the signal input in IO APIC if there is a	406	* Unmask the signal input in IO APIC if there is a
405	* mapping for the respective IRQ number.	407	* mapping for the respective IRQ number.
406	*/	408	*/
407	pin = mps_irq_to_pin(i);	409	pin = smp_irq_to_pin(i);
408	if (pin != -1) {	410	if (pin != -1) {
409	reglo = io_apic_read(IOREDTBL + pin*2);	411	reg.lo = io_apic_read(IOREDTBL + pin*2);
410	reglo &= ~(1<<16);	412	reg.masked = false;
411	io_apic_write(IOREDTBL + pin*2,reglo);	413	io_apic_write(IOREDTBL + pin*2, reg.lo);
412	}	414	}
413		415
414	}	416	}
415	}	417	}
416		418
417	}	419	}
418		420
419	#endif /* CONFIG_SMP */	421	#endif /* CONFIG_SMP */
420		422

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(root)/kernel/trunk/arch/ia32/src/smp/apic.c – Rev 501 → 512