WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/smp/apic.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mp.h>
#include <mm/page.h>
#include <time/delay.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef __SMP__
 
/*
 * This is functional, far-from-general-enough interface to the APIC.
 * Advanced Programmable Interrupt Controller for MP systems.
 * Tested on:
 *  Bochs 2.0.2 with 2-8 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
int apic_poll_errors(void);
 
void apic_init(void)
{
    __u32 tmp, id, i;
 
    trap_register(VECTOR_APIC_SPUR, apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    trap_register(VECTOR_CLK, l_apic_timer_interrupt);
    for (i=1; i<16; i++) {
        int pin;
   
        if ((pin = mp_irq_to_pin(i)) != -1)
                io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
    }
   
 
    /*
     * Ensure that io_apic has unique ID.
     */
    tmp = io_apic_read(IOAPICID);
    id = (tmp >> 24) & 0xf;
    if ((1<<id) & apic_id_mask) {
        int i;
       
        for (i=0; i<15; i++) {
            if (!((1<<i) & apic_id_mask)) {
                io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
                break;
            }
        }
    }
 
 
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
    l_apic_debug();
}
 
void apic_spurious(__u8 n, __u32 stack[])
{
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
 
int apic_poll_errors(void)
{
    __u32 esr;
   
    esr = l_apic[ESR] & ~ESRClear;
   
    if ((esr>>0) & 1)
        printf("Send CS Error\n");
    if ((esr>>1) & 1)
        printf("Receive CS Error\n");
    if ((esr>>2) & 1)
        printf("Send Accept Error\n");
    if ((esr>>3) & 1)
        printf("Receive Accept Error\n");
    if ((esr>>5) & 1)
        printf("Send Illegal Vector\n");
    if ((esr>>6) & 1)
        printf("Received Illegal Vector\n");
    if ((esr>>7) & 1)
        printf("Illegal Register Address\n");
   
    return !esr;
}
 
/*
 * Send all CPUs excluding CPU IPI vector.
 */
int l_apic_broadcast_custom_ipi(__u8 vector)
{
    __u32 lo;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    lo = l_apic[ICRlo] & ICRloClear;
 
    lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
   
    l_apic[ICRlo] = lo;
 
    lo = l_apic[ICRlo] & ICRloClear;
    if (lo & SEND_PENDING)
        printf("IPI is pending.\n");
 
    return apic_poll_errors();
}
 
/*
 * Universal Start-up Algorithm for bringing up the AP processors.
 */
int l_apic_send_init_ipi(__u8 apicid)
{
    __u32 lo, hi;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    lo = l_apic[ICRlo] & ICRloClear;
    hi = l_apic[ICRhi] & ICRhiClear;
   
    lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
    hi |= apicid << 24;
   
    l_apic[ICRhi] = hi;
    l_apic[ICRlo] = lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors()) return 0;
 
    lo = l_apic[ICRlo] & ICRloClear;
    if (lo & SEND_PENDING)
        printf("IPI is pending.\n");
 
    l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
 
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
 
         */
        for (i = 0; i<2; i++) {
            lo = l_apic[ICRlo] & ICRloClear;
            lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
            l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST |  TRGRMODE_LEVEL;
            delay(200);
        }
    }
   
   
    return apic_poll_errors();
}
 
void l_apic_init(void)
{
    __u32 tmp, t1, t2;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
    l_apic[LVT_Err] |= (1<<16);
    l_apic[LVT_LINT0] |= (1<<16);
    l_apic[LVT_LINT1] |= (1<<16);
 
    tmp = l_apic[SVR] & SVRClear;
    l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
 
    l_apic[TPR] &= TPRClear;
 
//  if (CPU->arch.family >= 6)
//      enable_l_apic_in_msr();
   
    tmp = l_apic[ICRlo] & ICRloClear;
    l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
   
    /*
     * Program the timer for periodic mode and respective vector.
     */
 
    l_apic[TDCR] &= TDCRClear;
    l_apic[TDCR] |= 0xb;
    tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
    l_apic[LVT_Tm] = tmp & ~(1<<16);
 
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
}
 
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    int i, lint;
 
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    printf("LVT_Tm: ");
    if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
    if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
    if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
    printf("%B\n", l_apic[LVT_Tm] & 0xff);
   
    for (i=0; i<2; i++) {
        lint = i ? LVT_LINT1 : LVT_LINT0;
        printf("LVT_LINT%d: ", i);
        if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
        if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
        printf("%d", l_apic[lint] & (1<<14)); putchar(',');
        printf("%d", l_apic[lint] & (1<<13)); putchar(',');
        if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
   
        switch ((l_apic[lint]>>8)&7) {
            case 0: printf("fixed"); break;
            case 4: printf("NMI"); break;
            case 7: printf("ExtINT"); break;
        }
        putchar(',');
        printf("%B\n", l_apic[lint] & 0xff);   
    }
 
    printf("LVT_Err: ");
    if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
    if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
    printf("%B\n", l_apic[LVT_Err] & 0xff);
 
    /*
     * This register is supported only on P6 and higher.
     */
    if (CPU->arch.family > 5) {
        printf("LVT_PCINT: ");
        if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
        if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
        switch ((l_apic[LVT_PCINT] >> 8)&7) {
            case 0: printf("fixed"); break;
            case 4: printf("NMI"); break;
            case 7: printf("ExtINT"); break;
        }
        putchar(',');
        printf("%B\n", l_apic[LVT_PCINT] & 0xff);
    }
#endif
}
 
void l_apic_timer_interrupt(__u8 n, __u32 stack[])
{
    l_apic_eoi();
    clock();
}
 
inline __u8 l_apic_id(void)
{
    return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
}
 
__u32 io_apic_read(__u8 address)
{
    __u32 tmp;
   
    tmp = io_apic[IOREGSEL] & ~0xf;
    io_apic[IOREGSEL] = tmp | address;
    return io_apic[IOWIN];
}
 
void io_apic_write(__u8 address, __u32 x)
{
    __u32 tmp;
 
    tmp = io_apic[IOREGSEL] & ~0xf;
    io_apic[IOREGSEL] = tmp | address;
    io_apic[IOWIN] = x;
}
 
void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
{
    __u32 reglo, reghi;
    int dlvr = 0;
   
    if (flags & LOPRI)
        dlvr = 1;
   
    reglo = io_apic_read(IOREDTBL + signal*2);
    reghi = io_apic_read(IOREDTBL + signal*2 + 1);
   
    reghi &= ~0x0f000000;
    reghi |= (dest<<24);
 
    reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
    reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
 
    io_apic_write(IOREDTBL + signal*2, reglo);     
    io_apic_write(IOREDTBL + signal*2 + 1, reghi);
}
 
void io_apic_disable_irqs(__u16 irqmask)
{
    int i,pin;
    __u32 reglo;
   
    for (i=0;i<16;i++) {
        if ((irqmask>>i) & 1) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = mp_irq_to_pin(i);
            if (pin != -1) {
                reglo = io_apic_read(IOREDTBL + pin*2);
                reglo |= (1<<16);
                io_apic_write(IOREDTBL + pin*2,reglo);
            }
           
        }
    }
}
 
void io_apic_enable_irqs(__u16 irqmask)
{
    int i,pin;
    __u32 reglo;
   
    for (i=0;i<16;i++) {
        if ((irqmask>>i) & 1) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = mp_irq_to_pin(i);
            if (pin != -1) {
                reglo = io_apic_read(IOREDTBL + pin*2);
                reglo &= ~(1<<16);
                io_apic_write(IOREDTBL + pin*2,reglo);
            }
           
        }
    }
 
}
 
#endif /* __SMP__ */
 

Rev 21	Rev 27
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/types.h>	29	#include <arch/types.h>
30	#include <arch/smp/apic.h>	30	#include <arch/smp/apic.h>
31	#include <arch/smp/ap.h>	31	#include <arch/smp/ap.h>
32	#include <arch/smp/mp.h>	32	#include <arch/smp/mp.h>
33	#include <mm/page.h>	33	#include <mm/page.h>
34	#include <time/delay.h>	34	#include <time/delay.h>
35	#include <arch/interrupt.h>	35	#include <arch/interrupt.h>
36	#include <print.h>	36	#include <print.h>
37	#include <arch/asm.h>	37	#include <arch/asm.h>
38	#include <arch.h>	38	#include <arch.h>
39		39
40	#ifdef __SMP__	40	#ifdef __SMP__
41		41
42	/*	42	/*
43	* This is functional, far-from-general-enough interface to the APIC.	43	* This is functional, far-from-general-enough interface to the APIC.
44	* Advanced Programmable Interrupt Controller for MP systems.	44	* Advanced Programmable Interrupt Controller for MP systems.
45	* Tested on:	45	* Tested on:
46	* Bochs 2.0.2 with 2-8 CPUs	46	* Bochs 2.0.2 with 2-8 CPUs
47	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	47	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
48	*/	48	*/
49		49
50	/*	50	/*
51	* These variables either stay configured as initilalized, or are changed by	51	* These variables either stay configured as initilalized, or are changed by
52	* the MP configuration code.	52	* the MP configuration code.
53	*	53	*
54	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	54	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
55	* optimize the code too much and accesses to l_apic and io_apic, that must	55	* optimize the code too much and accesses to l_apic and io_apic, that must
56	* always be 32-bit, would use byte oriented instructions.	56	* always be 32-bit, would use byte oriented instructions.
57	*/	57	*/
58	volatile __u32 l_apic = (__u32 ) 0xfee00000;	58	volatile __u32 l_apic = (__u32 ) 0xfee00000;
59	volatile __u32 io_apic = (__u32 ) 0xfec00000;	59	volatile __u32 io_apic = (__u32 ) 0xfec00000;
60		60
61	__u32 apic_id_mask = 0;	61	__u32 apic_id_mask = 0;
62		62
63	int apic_poll_errors(void);	63	int apic_poll_errors(void);
64		64
65	void apic_init(void)	65	void apic_init(void)
66	{	66	{
67	__u32 tmp, id, i;	67	__u32 tmp, id, i;
68		68
69	trap_register(VECTOR_APIC_SPUR, apic_spurious);	69	trap_register(VECTOR_APIC_SPUR, apic_spurious);
70		70
71	enable_irqs_function = io_apic_enable_irqs;	71	enable_irqs_function = io_apic_enable_irqs;
72	disable_irqs_function = io_apic_disable_irqs;	72	disable_irqs_function = io_apic_disable_irqs;
73	eoi_function = l_apic_eoi;	73	eoi_function = l_apic_eoi;
74		74
75	/*	75	/*
76	* Configure interrupt routing.	76	* Configure interrupt routing.
77	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	77	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
78	* Other interrupts will be forwarded to the lowest priority CPU.	78	* Other interrupts will be forwarded to the lowest priority CPU.
79	*/	79	*/
80	io_apic_disable_irqs(0xffff);	80	io_apic_disable_irqs(0xffff);
81	trap_register(VECTOR_CLK, l_apic_timer_interrupt);	81	trap_register(VECTOR_CLK, l_apic_timer_interrupt);
82	for (i=1; i<16; i++) {	82	for (i=1; i<16; i++) {
83	int pin;	83	int pin;
84		84
85	if ((pin = mp_irq_to_pin(i)) != -1)	85	if ((pin = mp_irq_to_pin(i)) != -1)
86	io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);	86	io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
87	}	87	}
88		88
89		89
90	/*	90	/*
91	* Ensure that io_apic has unique ID.	91	* Ensure that io_apic has unique ID.
92	*/	92	*/
93	tmp = io_apic_read(IOAPICID);	93	tmp = io_apic_read(IOAPICID);
94	id = (tmp >> 24) & 0xf;	94	id = (tmp >> 24) & 0xf;
95	if ((1<<id) & apic_id_mask) {	95	if ((1<<id) & apic_id_mask) {
96	int i;	96	int i;
97		97
98	for (i=0; i<15; i++) {	98	for (i=0; i<15; i++) {
99	if (!((1<<i) & apic_id_mask)) {	99	if (!((1<<i) & apic_id_mask)) {
100	io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) \| (i<<24));	100	io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) \| (i<<24));
101	break;	101	break;
102	}	102	}
103	}	103	}
104	}	104	}
105		105
106		-
107		-
108	/*	106	/*
109	* Configure the BSP's lapic.	107	* Configure the BSP's lapic.
110	*/	108	*/
111	l_apic_init();	109	l_apic_init();
112	l_apic_debug();	110	l_apic_debug();
113	}	111	}
114		112
115	void apic_spurious(__u8 n, __u32 stack[])	113	void apic_spurious(__u8 n, __u32 stack[])
116	{	114	{
117	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	115	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
118	}	116	}
119		117
120	int apic_poll_errors(void)	118	int apic_poll_errors(void)
121	{	119	{
122	__u32 esr;	120	__u32 esr;
123		121
124	esr = l_apic[ESR] & ~ESRClear;	122	esr = l_apic[ESR] & ~ESRClear;
125		123
126	if ((esr>>0) & 1)	124	if ((esr>>0) & 1)
127	printf("Send CS Error\n");	125	printf("Send CS Error\n");
128	if ((esr>>1) & 1)	126	if ((esr>>1) & 1)
129	printf("Receive CS Error\n");	127	printf("Receive CS Error\n");
130	if ((esr>>2) & 1)	128	if ((esr>>2) & 1)
131	printf("Send Accept Error\n");	129	printf("Send Accept Error\n");
132	if ((esr>>3) & 1)	130	if ((esr>>3) & 1)
133	printf("Receive Accept Error\n");	131	printf("Receive Accept Error\n");
134	if ((esr>>5) & 1)	132	if ((esr>>5) & 1)
135	printf("Send Illegal Vector\n");	133	printf("Send Illegal Vector\n");
136	if ((esr>>6) & 1)	134	if ((esr>>6) & 1)
137	printf("Received Illegal Vector\n");	135	printf("Received Illegal Vector\n");
138	if ((esr>>7) & 1)	136	if ((esr>>7) & 1)
139	printf("Illegal Register Address\n");	137	printf("Illegal Register Address\n");
140		138
141	return !esr;	139	return !esr;
142	}	140	}
143		141
144	/*	142	/*
145	* Send all CPUs excluding CPU IPI vector.	143	* Send all CPUs excluding CPU IPI vector.
146	*/	144	*/
147	int l_apic_broadcast_custom_ipi(__u8 vector)	145	int l_apic_broadcast_custom_ipi(__u8 vector)
148	{	146	{
149	__u32 lo;	147	__u32 lo;
150		148
151	/*	149	/*
152	* Read the ICR register in and zero all non-reserved fields.	150	* Read the ICR register in and zero all non-reserved fields.
153	*/	151	*/
154	lo = l_apic[ICRlo] & ICRloClear;	152	lo = l_apic[ICRlo] & ICRloClear;
155		153
156	lo \|= DLVRMODE_FIXED \| DESTMODE_LOGIC \| LEVEL_ASSERT \| SHORTHAND_EXCL \| TRGRMODE_LEVEL \| vector;	154	lo \|= DLVRMODE_FIXED \| DESTMODE_LOGIC \| LEVEL_ASSERT \| SHORTHAND_EXCL \| TRGRMODE_LEVEL \| vector;
157		155
158	l_apic[ICRlo] = lo;	156	l_apic[ICRlo] = lo;
159		157
160	lo = l_apic[ICRlo] & ICRloClear;	158	lo = l_apic[ICRlo] & ICRloClear;
161	if (lo & SEND_PENDING)	159	if (lo & SEND_PENDING)
162	printf("IPI is pending.\n");	160	printf("IPI is pending.\n");
163		161
164	return apic_poll_errors();	162	return apic_poll_errors();
165	}	163	}
166		164
167	/*	165	/*
168	* Universal Start-up Algorithm for bringing up the AP processors.	166	* Universal Start-up Algorithm for bringing up the AP processors.
169	*/	167	*/
170	int l_apic_send_init_ipi(__u8 apicid)	168	int l_apic_send_init_ipi(__u8 apicid)
171	{	169	{
172	__u32 lo, hi;	170	__u32 lo, hi;
173	int i;	171	int i;
174		172
175	/*	173	/*
176	* Read the ICR register in and zero all non-reserved fields.	174	* Read the ICR register in and zero all non-reserved fields.
177	*/	175	*/
178	lo = l_apic[ICRlo] & ICRloClear;	176	lo = l_apic[ICRlo] & ICRloClear;
179	hi = l_apic[ICRhi] & ICRhiClear;	177	hi = l_apic[ICRhi] & ICRhiClear;
180		178
181	lo \|= DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	179	lo \|= DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
182	hi \|= apicid << 24;	180	hi \|= apicid << 24;
183		181
184	l_apic[ICRhi] = hi;	182	l_apic[ICRhi] = hi;
185	l_apic[ICRlo] = lo;	183	l_apic[ICRlo] = lo;
186		184
187	/*	185	/*
188	* According to MP Specification, 20us should be enough to	186	* According to MP Specification, 20us should be enough to
189	* deliver the IPI.	187	* deliver the IPI.
190	*/	188	*/
191	delay(20);	189	delay(20);
192		190
193	if (!apic_poll_errors()) return 0;	191	if (!apic_poll_errors()) return 0;
194		192
195	lo = l_apic[ICRlo] & ICRloClear;	193	lo = l_apic[ICRlo] & ICRloClear;
196	if (lo & SEND_PENDING)	194	if (lo & SEND_PENDING)
197	printf("IPI is pending.\n");	195	printf("IPI is pending.\n");
198		196
199	l_apic[ICRlo] = lo \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	197	l_apic[ICRlo] = lo \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
200		198
201	/*	199	/*
202	* Wait 10ms as MP Specification specifies.	200	* Wait 10ms as MP Specification specifies.
203	*/	201	*/
204	delay(10000);	202	delay(10000);
205		203
-		204	if (!is_82489DX_apic(l_apic[LAVR])) {
206	/*	205	/*
207	* MP specification says this should not be done for 82489DX-based	-
208	* l_apic's. However, everything is ok as long as STARTUP IPI is ignored	206	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
209	* by 8249DX.	-
210	*/	207	*/
211	for (i = 0; i < 2; i++) {	208	for (i = 0; i<2; i++) {
212	lo = l_apic[ICRlo] & ICRloClear;	209	lo = l_apic[ICRlo] & ICRloClear;
213	lo \|= ((__address) ap_boot) / 4096; /* calculate the reset vector */	210	lo \|= ((__address) ap_boot) / 4096; /* calculate the reset vector */
214	l_apic[ICRlo] = lo \| DLVRMODE_STUP \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	211	l_apic[ICRlo] = lo \| DLVRMODE_STUP \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
215	delay(200);	212	delay(200);
-		213	}
216	}	214	}
217		215
-		216
218	return apic_poll_errors();	217	return apic_poll_errors();
219	}	218	}
220		219
221	void l_apic_init(void)	220	void l_apic_init(void)
222	{	221	{
223	__u32 tmp, t1, t2;	222	__u32 tmp, t1, t2;
224	int cpu_id = config.cpu_active - 1;	-
225		-
226		-
227	/*	-
228	* Here we set local APIC ID's so that they match operating system's CPU ID's	-
229	* This operation is dangerous as it is model specific.	-
230	* TODO: some care should be taken.	-
231	* NOTE: CPU may not be used to define APIC ID	-
232	*/	-
233	if (l_apic_id() != cpu_id) {	-
234	l_apic[L_APIC_ID] &= L_APIC_IDClear;	-
235	l_apic[L_APIC_ID] \|= (l_apic[L_APIC_ID]&L_APIC_IDClear)\|((cpu_id)<<L_APIC_IDShift);	-
236	}	-
237		223
238	l_apic[LVT_Err] \|= (1<<16);	224	l_apic[LVT_Err] \|= (1<<16);
239	l_apic[LVT_LINT0] \|= (1<<16);	225	l_apic[LVT_LINT0] \|= (1<<16);
240	l_apic[LVT_LINT1] \|= (1<<16);	226	l_apic[LVT_LINT1] \|= (1<<16);
241		227
242	tmp = l_apic[SVR] & SVRClear;	228	tmp = l_apic[SVR] & SVRClear;
243	l_apic[SVR] = tmp \| (1<<8) \| (VECTOR_APIC_SPUR);	229	l_apic[SVR] = tmp \| (1<<8) \| (VECTOR_APIC_SPUR);
244		230
245	l_apic[TPR] &= TPRClear;	231	l_apic[TPR] &= TPRClear;
246		232
247	if (CPU->arch.family >= 6)	233	// if (CPU->arch.family >= 6)
248	enable_l_apic_in_msr();	234	// enable_l_apic_in_msr();
249		235
250	tmp = l_apic[ICRlo] & ICRloClear;	236	tmp = l_apic[ICRlo] & ICRloClear;
251	l_apic[ICRlo] = tmp \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_INCL \| TRGRMODE_LEVEL;	237	l_apic[ICRlo] = tmp \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_INCL \| TRGRMODE_LEVEL;
252		238
253	/*	239	/*
254	* Program the timer for periodic mode and respective vector.	240	* Program the timer for periodic mode and respective vector.
255	*/	241	*/
256		242
257	l_apic[TDCR] &= TDCRClear;	243	l_apic[TDCR] &= TDCRClear;
258	l_apic[TDCR] \|= 0xb;	244	l_apic[TDCR] \|= 0xb;
259	tmp = l_apic[LVT_Tm] \| (1<<17) \| (VECTOR_CLK);	245	tmp = l_apic[LVT_Tm] \| (1<<17) \| (VECTOR_CLK);
260	l_apic[LVT_Tm] = tmp & ~(1<<16);	246	l_apic[LVT_Tm] = tmp & ~(1<<16);
261		247
262	t1 = l_apic[CCRT];	248	t1 = l_apic[CCRT];
263	l_apic[ICRT] = 0xffffffff;	249	l_apic[ICRT] = 0xffffffff;
264		250
265	while (l_apic[CCRT] == t1)	251	while (l_apic[CCRT] == t1)
266	;	252	;
267		253
268	t1 = l_apic[CCRT];	254	t1 = l_apic[CCRT];
269	delay(1000);	255	delay(1000);
270	t2 = l_apic[CCRT];	256	t2 = l_apic[CCRT];
271		257
272	l_apic[ICRT] = t1-t2;	258	l_apic[ICRT] = t1-t2;
273	}	259	}
274		260
275	void l_apic_eoi(void)	261	void l_apic_eoi(void)
276	{	262	{
277	l_apic[EOI] = 0;	263	l_apic[EOI] = 0;
278	}	264	}
279		265
280	void l_apic_debug(void)	266	void l_apic_debug(void)
281	{	267	{
282	#ifdef LAPIC_VERBOSE	268	#ifdef LAPIC_VERBOSE
283	int i, lint;	269	int i, lint;
284		270
285	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	271	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
286		272
287	printf("LVT_Tm: ");	273	printf("LVT_Tm: ");
288	if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');	274	if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');
289	if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	275	if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
290	if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	276	if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
291	printf("%B\n", l_apic[LVT_Tm] & 0xff);	277	printf("%B\n", l_apic[LVT_Tm] & 0xff);
292		278
293	for (i=0; i<2; i++) {	279	for (i=0; i<2; i++) {
294	lint = i ? LVT_LINT1 : LVT_LINT0;	280	lint = i ? LVT_LINT1 : LVT_LINT0;
295	printf("LVT_LINT%d: ", i);	281	printf("LVT_LINT%d: ", i);
296	if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	282	if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
297	if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');	283	if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
298	printf("%d", l_apic[lint] & (1<<14)); putchar(',');	284	printf("%d", l_apic[lint] & (1<<14)); putchar(',');
299	printf("%d", l_apic[lint] & (1<<13)); putchar(',');	285	printf("%d", l_apic[lint] & (1<<13)); putchar(',');
300	if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	286	if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
301		287
302	switch ((l_apic[lint]>>8)&7) {	288	switch ((l_apic[lint]>>8)&7) {
303	case 0: printf("fixed"); break;	289	case 0: printf("fixed"); break;
304	case 4: printf("NMI"); break;	290	case 4: printf("NMI"); break;
305	case 7: printf("ExtINT"); break;	291	case 7: printf("ExtINT"); break;
306	}	292	}
307	putchar(',');	293	putchar(',');
308	printf("%B\n", l_apic[lint] & 0xff);	294	printf("%B\n", l_apic[lint] & 0xff);
309	}	295	}
310		296
311	printf("LVT_Err: ");	297	printf("LVT_Err: ");
312	if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	298	if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
313	if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	299	if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
314	printf("%B\n", l_apic[LVT_Err] & 0xff);	300	printf("%B\n", l_apic[LVT_Err] & 0xff);
315		301
316	/*	302	/*
317	* This register is supported only on P6 and higher.	303	* This register is supported only on P6 and higher.
318	*/	304	*/
319	if (CPU->arch.family > 5) {	305	if (CPU->arch.family > 5) {
320	printf("LVT_PCINT: ");	306	printf("LVT_PCINT: ");
321	if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	307	if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
322	if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	308	if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
323	switch ((l_apic[LVT_PCINT] >> 8)&7) {	309	switch ((l_apic[LVT_PCINT] >> 8)&7) {
324	case 0: printf("fixed"); break;	310	case 0: printf("fixed"); break;
325	case 4: printf("NMI"); break;	311	case 4: printf("NMI"); break;
326	case 7: printf("ExtINT"); break;	312	case 7: printf("ExtINT"); break;
327	}	313	}
328	putchar(',');	314	putchar(',');
329	printf("%B\n", l_apic[LVT_PCINT] & 0xff);	315	printf("%B\n", l_apic[LVT_PCINT] & 0xff);
330	}	316	}
331	#endif	317	#endif
332	}	318	}
333		319
334	void l_apic_timer_interrupt(__u8 n, __u32 stack[])	320	void l_apic_timer_interrupt(__u8 n, __u32 stack[])
335	{	321	{
336	l_apic_eoi();	322	l_apic_eoi();
337	clock();	323	clock();
338	}	324	}
339		325
340	inline __u8 l_apic_id(void)	326	inline __u8 l_apic_id(void)
341	{	327	{
342	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;	328	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
343	}	329	}
344		330
345	__u32 io_apic_read(__u8 address)	331	__u32 io_apic_read(__u8 address)
346	{	332	{
347	__u32 tmp;	333	__u32 tmp;
348		334
349	tmp = io_apic[IOREGSEL] & ~0xf;	335	tmp = io_apic[IOREGSEL] & ~0xf;
350	io_apic[IOREGSEL] = tmp \| address;	336	io_apic[IOREGSEL] = tmp \| address;
351	return io_apic[IOWIN];	337	return io_apic[IOWIN];
352	}	338	}
353		339
354	void io_apic_write(__u8 address, __u32 x)	340	void io_apic_write(__u8 address, __u32 x)
355	{	341	{
356	__u32 tmp;	342	__u32 tmp;
357		343
358	tmp = io_apic[IOREGSEL] & ~0xf;	344	tmp = io_apic[IOREGSEL] & ~0xf;
359	io_apic[IOREGSEL] = tmp \| address;	345	io_apic[IOREGSEL] = tmp \| address;
360	io_apic[IOWIN] = x;	346	io_apic[IOWIN] = x;
361	}	347	}
362		348
363	void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)	349	void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
364	{	350	{
365	__u32 reglo, reghi;	351	__u32 reglo, reghi;
366	int dlvr = 0;	352	int dlvr = 0;
367		353
368	if (flags & LOPRI)	354	if (flags & LOPRI)
369	dlvr = 1;	355	dlvr = 1;
370		356
371	reglo = io_apic_read(IOREDTBL + signal*2);	357	reglo = io_apic_read(IOREDTBL + signal*2);
372	reghi = io_apic_read(IOREDTBL + signal*2 + 1);	358	reghi = io_apic_read(IOREDTBL + signal*2 + 1);
373		359
374	reghi &= ~0x0f000000;	360	reghi &= ~0x0f000000;
375	reghi \|= (dest<<24);	361	reghi \|= (dest<<24);
376		362
377	reglo &= (~0x1ffff) \| (1<<16); /* don't touch the mask */	363	reglo &= (~0x1ffff) \| (1<<16); /* don't touch the mask */
378	reglo \|= (0<<15) \| (0<<13) \| (0<<11) \| (dlvr<<8) \| v;	364	reglo \|= (0<<15) \| (0<<13) \| (0<<11) \| (dlvr<<8) \| v;
379		365
380	io_apic_write(IOREDTBL + signal*2, reglo);	366	io_apic_write(IOREDTBL + signal*2, reglo);
381	io_apic_write(IOREDTBL + signal*2 + 1, reghi);	367	io_apic_write(IOREDTBL + signal*2 + 1, reghi);
382	}	368	}
383		369
384	void io_apic_disable_irqs(__u16 irqmask)	370	void io_apic_disable_irqs(__u16 irqmask)
385	{	371	{
386	int i,pin;	372	int i,pin;
387	__u32 reglo;	373	__u32 reglo;
388		374
389	for (i=0;i<16;i++) {	375	for (i=0;i<16;i++) {
390	if ((irqmask>>i) & 1) {	376	if ((irqmask>>i) & 1) {
391	/*	377	/*
392	* Mask the signal input in IO APIC if there is a	378	* Mask the signal input in IO APIC if there is a
393	* mapping for the respective IRQ number.	379	* mapping for the respective IRQ number.
394	*/	380	*/
395	pin = mp_irq_to_pin(i);	381	pin = mp_irq_to_pin(i);
396	if (pin != -1) {	382	if (pin != -1) {
397	reglo = io_apic_read(IOREDTBL + pin*2);	383	reglo = io_apic_read(IOREDTBL + pin*2);
398	reglo \|= (1<<16);	384	reglo \|= (1<<16);
399	io_apic_write(IOREDTBL + pin*2,reglo);	385	io_apic_write(IOREDTBL + pin*2,reglo);
400	}	386	}
401		387
402	}	388	}
403	}	389	}
404	}	390	}
405		391
406	void io_apic_enable_irqs(__u16 irqmask)	392	void io_apic_enable_irqs(__u16 irqmask)
407	{	393	{
408	int i,pin;	394	int i,pin;
409	__u32 reglo;	395	__u32 reglo;
410		396
411	for (i=0;i<16;i++) {	397	for (i=0;i<16;i++) {
412	if ((irqmask>>i) & 1) {	398	if ((irqmask>>i) & 1) {
413	/*	399	/*
414	* Unmask the signal input in IO APIC if there is a	400	* Unmask the signal input in IO APIC if there is a
415	* mapping for the respective IRQ number.	401	* mapping for the respective IRQ number.
416	*/	402	*/
417	pin = mp_irq_to_pin(i);	403	pin = mp_irq_to_pin(i);
418	if (pin != -1) {	404	if (pin != -1) {
419	reglo = io_apic_read(IOREDTBL + pin*2);	405	reglo = io_apic_read(IOREDTBL + pin*2);
420	reglo &= ~(1<<16);	406	reglo &= ~(1<<16);
421	io_apic_write(IOREDTBL + pin*2,reglo);	407	io_apic_write(IOREDTBL + pin*2,reglo);
422	}	408	}
423		409
424	}	410	}
425	}	411	}
426		412
427	}	413	}
428		414
429	#endif /* __SMP__ */	415	#endif /* __SMP__ */
430		416

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia32/src/smp/apic.c @ 1780 – Rev 21 → 27