WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/smp/apic.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <mm/page.h>
#include <time/delay.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef CONFIG_SMP
 
/*
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.19 2-8 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
int apic_poll_errors(void);
 
/** Initialize APIC on BSP. */
void apic_init(void)
{
    __u32 tmp, id, i;
 
    trap_register(VECTOR_APIC_SPUR, apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    trap_register(VECTOR_CLK, l_apic_timer_interrupt);
    for (i=0; i<16; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1) {
            io_apic_change_ioredtbl(pin, 0xff, IVT_IRQBASE+i, LOPRI);
        }
    }
   
 
    /*
     * Ensure that io_apic has unique ID.
     */
    tmp = io_apic_read(IOAPICID);
    id = (tmp >> 24) & 0xf;
    if ((1<<id) & apic_id_mask) {
        int i;
       
        for (i=0; i<15; i++) {
            if (!((1<<i) & apic_id_mask)) {
                io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
    l_apic_debug();
}
 
void apic_spurious(__u8 n, __native stack[])
{
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
 
int apic_poll_errors(void)
{
    __u32 esr;
   
    esr = l_apic[ESR] & ~ESRClear;
   
    if ((esr>>0) & 1)
        printf("Send CS Error\n");
    if ((esr>>1) & 1)
        printf("Receive CS Error\n");
    if ((esr>>2) & 1)
        printf("Send Accept Error\n");
    if ((esr>>3) & 1)
        printf("Receive Accept Error\n");
    if ((esr>>5) & 1)
        printf("Send Illegal Vector\n");
    if ((esr>>6) & 1)
        printf("Received Illegal Vector\n");
    if ((esr>>7) & 1)
        printf("Illegal Register Address\n");
 
    return !esr;
}
 
/*
 * Send all CPUs excluding CPU IPI vector.
 */
int l_apic_broadcast_custom_ipi(__u8 vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;
    icr.destmod = DESTMOD_LOGIC;
    icr.level = LEVEL_ASSERT;
    icr.shorthand = SHORTHAND_ALL_EXCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = vector;
 
 
 
    l_apic[ICRlo] = icr.lo;
 
    icr.lo = l_apic[ICRlo];
    if (icr.lo & SEND_PENDING)
        printf("IPI is pending.\n");
 
    return apic_poll_errors();
}
 
/*
 * Universal Start-up Algorithm for bringing up the AP processors.
 */
int l_apic_send_init_ipi(__u8 apicid)
{
    icr_t icr;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    icr.lo = l_apic[ICRlo];
    icr.hi = l_apic[ICRhi];
   
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_ASSERT;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.shorthand = SHORTHAND_NONE;
    icr.vector = 0;
    icr.dest = apicid;
   
    l_apic[ICRhi] = icr.hi;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors()) return 0;
 
    icr.lo = l_apic[ICRlo];
    if (icr.lo & SEND_PENDING)
        printf("IPI is pending.\n");
 
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_NONE;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = 0;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;
            l_apic[ICRlo] = icr.lo;
            delay(200);
        }
    }
   
   
    return apic_poll_errors();
}
 
void l_apic_init(void)
{
    lvt_error_t error;
    lvt_lint_t lint;
    svr_t svr;
    lvt_tm_t tm;
    icr_t icr;
    __u32 t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;
 
    /* Initialize LVT LINT0 register. */
    lint.value = l_apic[LVT_LINT0];
    lint.masked = true;
    l_apic[LVT_LINT0] = lint.value;
 
    /* Initialize LVT LINT1 register. */
    lint.value = l_apic[LVT_LINT1];
    lint.masked = true;
    l_apic[LVT_LINT1] = lint.value;
   
    /* Spurious-Interrupt Vector Register initialization. */
    svr.value = l_apic[SVR];
    svr.vector = VECTOR_APIC_SPUR;
    svr.lapic_enabled = true;
    l_apic[SVR] = svr.value;
 
    l_apic[TPR] &= TPRClear;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    /* Interrupt Command Register initialization. */
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_ALL_INCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    l_apic[ICRlo] = icr.lo;
   
    /*
     * Program the timer for periodic mode and respective vector.
     */
 
    l_apic[TDCR] &= TDCRClear;
    l_apic[TDCR] |= 0xb;
 
    tm.value = l_apic[LVT_Tm];
    tm.vector = VECTOR_CLK;
    tm.mode = TIMER_PERIODIC;
    tm.masked = false;
    l_apic[LVT_Tm] = tm.value;
 
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
   
}
 
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    int i, lint;
 
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    printf("LVT_Tm: ");
    if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
    if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
    if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
    printf("%B\n", l_apic[LVT_Tm] & 0xff);
   
    for (i=0; i<2; i++) {
        lint = i ? LVT_LINT1 : LVT_LINT0;
        printf("LVT_LINT%d: ", i);
        if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
        if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
        printf("%d", l_apic[lint] & (1<<14)); putchar(',');
        printf("%d", l_apic[lint] & (1<<13)); putchar(',');
        if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
   
        switch ((l_apic[lint]>>8)&7) {
            case 0: printf("fixed"); break;
            case 4: printf("NMI"); break;
            case 7: printf("ExtINT"); break;
        }
        putchar(',');
        printf("%B\n", l_apic[lint] & 0xff);   
    }
 
    printf("LVT_Err: ");
    if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
    if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
    printf("%B\n", l_apic[LVT_Err] & 0xff);
 
    /*
     * This register is supported only on P6 and higher.
     */
    if (CPU->arch.family > 5) {
        printf("LVT_PCINT: ");
        if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
        if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
        switch ((l_apic[LVT_PCINT] >> 8)&7) {
            case 0: printf("fixed"); break;
            case 4: printf("NMI"); break;
            case 7: printf("ExtINT"); break;
        }
        putchar(',');
        printf("%B\n", l_apic[LVT_PCINT] & 0xff);
    }
#endif
}
 
void l_apic_timer_interrupt(__u8 n, __native stack[])
{
    l_apic_eoi();
    clock();
}
 
__u8 l_apic_id(void)
{
    return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
}
 
__u32 io_apic_read(__u8 address)
{
    __u32 tmp;
   
    tmp = io_apic[IOREGSEL] & ~0xf;
    io_apic[IOREGSEL] = tmp | address;
    return io_apic[IOWIN];
}
 
void io_apic_write(__u8 address, __u32 x)
{
    __u32 tmp;
 
    tmp = io_apic[IOREGSEL] & ~0xf;
    io_apic[IOREGSEL] = tmp | address;
    io_apic[IOWIN] = x;
}
 
void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = 0;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
   
    reg.lo = io_apic_read(IOREDTBL + signal*2);
    reg.hi = io_apic_read(IOREDTBL + signal*2 + 1);
   
    reg.dest =  dest;
    reg.destmod = DESTMOD_LOGIC;
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + signal*2, reg.lo);
    io_apic_write(IOREDTBL + signal*2 + 1, reg.hi);
}
 
void io_apic_disable_irqs(__u16 irqmask)
{
    io_redirection_reg_t reg;
    int i, pin;
   
    for (i=0;i<16;i++) {
        if ((irqmask>>i) & 1) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
void io_apic_enable_irqs(__u16 irqmask)
{
    int i, pin;
    io_redirection_reg_t reg;  
   
    for (i=0;i<16;i++) {
        if ((irqmask>>i) & 1) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
 
}
 
#endif /* CONFIG_SMP */
 

Rev 512	Rev 513
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/types.h>	29	#include <arch/types.h>
30	#include <arch/smp/apic.h>	30	#include <arch/smp/apic.h>
31	#include <arch/smp/ap.h>	31	#include <arch/smp/ap.h>
32	#include <arch/smp/mps.h>	32	#include <arch/smp/mps.h>
33	#include <mm/page.h>	33	#include <mm/page.h>
34	#include <time/delay.h>	34	#include <time/delay.h>
35	#include <arch/interrupt.h>	35	#include <arch/interrupt.h>
36	#include <print.h>	36	#include <print.h>
37	#include <arch/asm.h>	37	#include <arch/asm.h>
38	#include <arch.h>	38	#include <arch.h>
39		39
40	#ifdef CONFIG_SMP	40	#ifdef CONFIG_SMP
41		41
42	/*	42	/*
43	* Advanced Programmable Interrupt Controller for SMP systems.	43	* Advanced Programmable Interrupt Controller for SMP systems.
44	* Tested on:	44	* Tested on:
45	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs	45	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
46	* Simics 2.0.28 - Simics 2.2.14 2-4 CPUs	46	* Simics 2.0.28 - Simics 2.2.19 2-8 CPUs
47	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	47	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
48	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	48	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
49	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	49	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
50	*/	50	*/
51		51
52	/*	52	/*
53	* These variables either stay configured as initilalized, or are changed by	53	* These variables either stay configured as initilalized, or are changed by
54	* the MP configuration code.	54	* the MP configuration code.
55	*	55	*
56	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	56	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
57	* optimize the code too much and accesses to l_apic and io_apic, that must	57	* optimize the code too much and accesses to l_apic and io_apic, that must
58	* always be 32-bit, would use byte oriented instructions.	58	* always be 32-bit, would use byte oriented instructions.
59	*/	59	*/
60	volatile __u32 l_apic = (__u32 ) 0xfee00000;	60	volatile __u32 l_apic = (__u32 ) 0xfee00000;
61	volatile __u32 io_apic = (__u32 ) 0xfec00000;	61	volatile __u32 io_apic = (__u32 ) 0xfec00000;
62		62
63	__u32 apic_id_mask = 0;	63	__u32 apic_id_mask = 0;
64		64
65	int apic_poll_errors(void);	65	int apic_poll_errors(void);
66		66
-		67	/** Initialize APIC on BSP. */
67	void apic_init(void)	68	void apic_init(void)
68	{	69	{
69	__u32 tmp, id, i;	70	__u32 tmp, id, i;
70		71
71	trap_register(VECTOR_APIC_SPUR, apic_spurious);	72	trap_register(VECTOR_APIC_SPUR, apic_spurious);
72		73
73	enable_irqs_function = io_apic_enable_irqs;	74	enable_irqs_function = io_apic_enable_irqs;
74	disable_irqs_function = io_apic_disable_irqs;	75	disable_irqs_function = io_apic_disable_irqs;
75	eoi_function = l_apic_eoi;	76	eoi_function = l_apic_eoi;
76		77
77	/*	78	/*
78	* Configure interrupt routing.	79	* Configure interrupt routing.
79	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	80	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
80	* Other interrupts will be forwarded to the lowest priority CPU.	81	* Other interrupts will be forwarded to the lowest priority CPU.
81	*/	82	*/
82	io_apic_disable_irqs(0xffff);	83	io_apic_disable_irqs(0xffff);
83	trap_register(VECTOR_CLK, l_apic_timer_interrupt);	84	trap_register(VECTOR_CLK, l_apic_timer_interrupt);
84	for (i=0; i<16; i++) {	85	for (i=0; i<16; i++) {
85	int pin;	86	int pin;
86		87
87	if ((pin = smp_irq_to_pin(i)) != -1) {	88	if ((pin = smp_irq_to_pin(i)) != -1) {
88	io_apic_change_ioredtbl(pin,0xff,IVT_IRQBASE+i,LOPRI);	89	io_apic_change_ioredtbl(pin, 0xff, IVT_IRQBASE+i, LOPRI);
89	}	90	}
90	}	91	}
91		92
92		93
93	/*	94	/*
94	* Ensure that io_apic has unique ID.	95	* Ensure that io_apic has unique ID.
95	*/	96	*/
96	tmp = io_apic_read(IOAPICID);	97	tmp = io_apic_read(IOAPICID);
97	id = (tmp >> 24) & 0xf;	98	id = (tmp >> 24) & 0xf;
98	if ((1<<id) & apic_id_mask) {	99	if ((1<<id) & apic_id_mask) {
99	int i;	100	int i;
100		101
101	for (i=0; i<15; i++) {	102	for (i=0; i<15; i++) {
102	if (!((1<<i) & apic_id_mask)) {	103	if (!((1<<i) & apic_id_mask)) {
103	io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) \| (i<<24));	104	io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) \| (i<<24));
104	break;	105	break;
105	}	106	}
106	}	107	}
107	}	108	}
108		109
109	/*	110	/*
110	* Configure the BSP's lapic.	111	* Configure the BSP's lapic.
111	*/	112	*/
112	l_apic_init();	113	l_apic_init();
113	l_apic_debug();	114	l_apic_debug();
114	}	115	}
115		116
116	void apic_spurious(__u8 n, __native stack[])	117	void apic_spurious(__u8 n, __native stack[])
117	{	118	{
118	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	119	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
119	}	120	}
120		121
121	int apic_poll_errors(void)	122	int apic_poll_errors(void)
122	{	123	{
123	__u32 esr;	124	__u32 esr;
124		125
125	esr = l_apic[ESR] & ~ESRClear;	126	esr = l_apic[ESR] & ~ESRClear;
126		127
127	if ((esr>>0) & 1)	128	if ((esr>>0) & 1)
128	printf("Send CS Error\n");	129	printf("Send CS Error\n");
129	if ((esr>>1) & 1)	130	if ((esr>>1) & 1)
130	printf("Receive CS Error\n");	131	printf("Receive CS Error\n");
131	if ((esr>>2) & 1)	132	if ((esr>>2) & 1)
132	printf("Send Accept Error\n");	133	printf("Send Accept Error\n");
133	if ((esr>>3) & 1)	134	if ((esr>>3) & 1)
134	printf("Receive Accept Error\n");	135	printf("Receive Accept Error\n");
135	if ((esr>>5) & 1)	136	if ((esr>>5) & 1)
136	printf("Send Illegal Vector\n");	137	printf("Send Illegal Vector\n");
137	if ((esr>>6) & 1)	138	if ((esr>>6) & 1)
138	printf("Received Illegal Vector\n");	139	printf("Received Illegal Vector\n");
139	if ((esr>>7) & 1)	140	if ((esr>>7) & 1)
140	printf("Illegal Register Address\n");	141	printf("Illegal Register Address\n");
141		142
142	return !esr;	143	return !esr;
143	}	144	}
144		145
145	/*	146	/*
146	* Send all CPUs excluding CPU IPI vector.	147	* Send all CPUs excluding CPU IPI vector.
147	*/	148	*/
148	int l_apic_broadcast_custom_ipi(__u8 vector)	149	int l_apic_broadcast_custom_ipi(__u8 vector)
149	{	150	{
150	__u32 lo;	151	icr_t icr;
151		152
152	/*	153	icr.lo = l_apic[ICRlo];
-		154	icr.delmod = DELMOD_FIXED;
153	* Read the ICR register in and zero all non-reserved fields.	155	icr.destmod = DESTMOD_LOGIC;
154	*/	156	icr.level = LEVEL_ASSERT;
-		157	icr.shorthand = SHORTHAND_ALL_EXCL;
155	lo = l_apic[ICRlo] & ICRloClear;	158	icr.trigger_mode = TRIGMOD_LEVEL;
-		159	icr.vector = vector;
156		160
157	lo \|= DLVRMODE_FIXED \| DESTMODE_LOGIC \| LEVEL_ASSERT \| SHORTHAND_EXCL \| TRGRMODE_LEVEL \| vector;	-
158		-
159	l_apic[ICRlo] = lo;	161	l_apic[ICRlo] = icr.lo;
160		162
161	lo = l_apic[ICRlo] & ICRloClear;	163	icr.lo = l_apic[ICRlo];
162	if (lo & SEND_PENDING)	164	if (icr.lo & SEND_PENDING)
163	printf("IPI is pending.\n");	165	printf("IPI is pending.\n");
164		166
165	return apic_poll_errors();	167	return apic_poll_errors();
166	}	168	}
167		169
168	/*	170	/*
169	* Universal Start-up Algorithm for bringing up the AP processors.	171	* Universal Start-up Algorithm for bringing up the AP processors.
170	*/	172	*/
171	int l_apic_send_init_ipi(__u8 apicid)	173	int l_apic_send_init_ipi(__u8 apicid)
172	{	174	{
173	__u32 lo, hi;	175	icr_t icr;
174	int i;	176	int i;
175		177
176	/*	178	/*
177	* Read the ICR register in and zero all non-reserved fields.	179	* Read the ICR register in and zero all non-reserved fields.
178	*/	180	*/
179	lo = l_apic[ICRlo] & ICRloClear;	181	icr.lo = l_apic[ICRlo];
180	hi = l_apic[ICRhi] & ICRhiClear;	182	icr.hi = l_apic[ICRhi];
181		183
-		184	icr.delmod = DELMOD_INIT;
-		185	icr.destmod = DESTMOD_PHYS;
-		186	icr.level = LEVEL_ASSERT;
182	lo \|= DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	187	icr.trigger_mode = TRIGMOD_LEVEL;
-		188	icr.shorthand = SHORTHAND_NONE;
-		189	icr.vector = 0;
183	hi \|= apicid << 24;	190	icr.dest = apicid;
184		191
185	l_apic[ICRhi] = hi;	192	l_apic[ICRhi] = icr.hi;
186	l_apic[ICRlo] = lo;	193	l_apic[ICRlo] = icr.lo;
187		194
188	/*	195	/*
189	* According to MP Specification, 20us should be enough to	196	* According to MP Specification, 20us should be enough to
190	* deliver the IPI.	197	* deliver the IPI.
191	*/	198	*/
192	delay(20);	199	delay(20);
193		200
194	if (!apic_poll_errors()) return 0;	201	if (!apic_poll_errors()) return 0;
195		202
196	lo = l_apic[ICRlo] & ICRloClear;	203	icr.lo = l_apic[ICRlo];
197	if (lo & SEND_PENDING)	204	if (icr.lo & SEND_PENDING)
198	printf("IPI is pending.\n");	205	printf("IPI is pending.\n");
199		206
-		207	icr.delmod = DELMOD_INIT;
-		208	icr.destmod = DESTMOD_PHYS;
-		209	icr.level = LEVEL_DEASSERT;
-		210	icr.shorthand = SHORTHAND_NONE;
200	l_apic[ICRlo] = lo \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	211	icr.trigger_mode = TRIGMOD_LEVEL;
-		212	icr.vector = 0;
-		213	l_apic[ICRlo] = icr.lo;
201		214
202	/*	215	/*
203	* Wait 10ms as MP Specification specifies.	216	* Wait 10ms as MP Specification specifies.
204	*/	217	*/
205	delay(10000);	218	delay(10000);
206		219
207	if (!is_82489DX_apic(l_apic[LAVR])) {	220	if (!is_82489DX_apic(l_apic[LAVR])) {
208	/*	221	/*
209	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	222	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
210	*/	223	*/
211	for (i = 0; i<2; i++) {	224	for (i = 0; i<2; i++) {
212	lo = l_apic[ICRlo] & ICRloClear;	225	icr.lo = l_apic[ICRlo];
213	lo \|= ((__address) ap_boot) / 4096; /* calculate the reset vector */	226	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
-		227	icr.delmod = DELMOD_STARTUP;
-		228	icr.destmod = DESTMOD_PHYS;
-		229	icr.level = LEVEL_ASSERT;
-		230	icr.shorthand = SHORTHAND_NONE;
214	l_apic[ICRlo] = lo \| DLVRMODE_STUP \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	231	icr.trigger_mode = TRIGMOD_LEVEL;
-		232	l_apic[ICRlo] = icr.lo;
215	delay(200);	233	delay(200);
216	}	234	}
217	}	235	}
218		236
219		237
220	return apic_poll_errors();	238	return apic_poll_errors();
221	}	239	}
222		240
223	void l_apic_init(void)	241	void l_apic_init(void)
224	{	242	{
-		243	lvt_error_t error;
-		244	lvt_lint_t lint;
-		245	svr_t svr;
-		246	lvt_tm_t tm;
-		247	icr_t icr;
225	__u32 tmp, t1, t2;	248	__u32 t1, t2;
226		249
-		250	/* Initialize LVT Error register. */
-		251	error.value = l_apic[LVT_Err];
-		252	error.masked = true;
227	l_apic[LVT_Err] \|= (1<<16);	253	l_apic[LVT_Err] = error.value;
-		254
-		255	/* Initialize LVT LINT0 register. */
-		256	lint.value = l_apic[LVT_LINT0];
-		257	lint.masked = true;
228	l_apic[LVT_LINT0] \|= (1<<16);	258	l_apic[LVT_LINT0] = lint.value;
-		259
-		260	/* Initialize LVT LINT1 register. */
-		261	lint.value = l_apic[LVT_LINT1];
-		262	lint.masked = true;
229	l_apic[LVT_LINT1] \|= (1<<16);	263	l_apic[LVT_LINT1] = lint.value;
230		264
-		265	/* Spurious-Interrupt Vector Register initialization. */
231	tmp = l_apic[SVR] & SVRClear;	266	svr.value = l_apic[SVR];
232	l_apic[SVR] = tmp \| (1<<8) \| (VECTOR_APIC_SPUR);	267	svr.vector = VECTOR_APIC_SPUR;
-		268	svr.lapic_enabled = true;
-		269	l_apic[SVR] = svr.value;
233		270
234	l_apic[TPR] &= TPRClear;	271	l_apic[TPR] &= TPRClear;
235		272
236	if (CPU->arch.family >= 6)	273	if (CPU->arch.family >= 6)
237	enable_l_apic_in_msr();	274	enable_l_apic_in_msr();
238		275
-		276	/* Interrupt Command Register initialization. */
239	tmp = l_apic[ICRlo] & ICRloClear;	277	icr.lo = l_apic[ICRlo];
-		278	icr.delmod = DELMOD_INIT;
-		279	icr.destmod = DESTMOD_PHYS;
-		280	icr.level = LEVEL_DEASSERT;
240	l_apic[ICRlo] = tmp \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_INCL \| TRGRMODE_LEVEL;	281	icr.shorthand = SHORTHAND_ALL_INCL;
-		282	icr.trigger_mode = TRIGMOD_LEVEL;
-		283	l_apic[ICRlo] = icr.lo;
241		284
242	/*	285	/*
243	* Program the timer for periodic mode and respective vector.	286	* Program the timer for periodic mode and respective vector.
244	*/	287	*/
245		288
246	l_apic[TDCR] &= TDCRClear;	289	l_apic[TDCR] &= TDCRClear;
247	l_apic[TDCR] \|= 0xb;	290	l_apic[TDCR] \|= 0xb;
-		291
248	tmp = l_apic[LVT_Tm] \| (1<<17) \| (VECTOR_CLK);	292	tm.value = l_apic[LVT_Tm];
-		293	tm.vector = VECTOR_CLK;
-		294	tm.mode = TIMER_PERIODIC;
-		295	tm.masked = false;
249	l_apic[LVT_Tm] = tmp & ~(1<<16);	296	l_apic[LVT_Tm] = tm.value;
250		297
251	t1 = l_apic[CCRT];	298	t1 = l_apic[CCRT];
252	l_apic[ICRT] = 0xffffffff;	299	l_apic[ICRT] = 0xffffffff;
253		300
254	while (l_apic[CCRT] == t1)	301	while (l_apic[CCRT] == t1)
255	;	302	;
256		303
257	t1 = l_apic[CCRT];	304	t1 = l_apic[CCRT];
258	delay(1000);	305	delay(1000);
259	t2 = l_apic[CCRT];	306	t2 = l_apic[CCRT];
260		307
261	l_apic[ICRT] = t1-t2;	308	l_apic[ICRT] = t1-t2;
262		309
263	}	310	}
264		311
265	void l_apic_eoi(void)	312	void l_apic_eoi(void)
266	{	313	{
267	l_apic[EOI] = 0;	314	l_apic[EOI] = 0;
268	}	315	}
269		316
270	void l_apic_debug(void)	317	void l_apic_debug(void)
271	{	318	{
272	#ifdef LAPIC_VERBOSE	319	#ifdef LAPIC_VERBOSE
273	int i, lint;	320	int i, lint;
274		321
275	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	322	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
276		323
277	printf("LVT_Tm: ");	324	printf("LVT_Tm: ");
278	if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');	325	if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');
279	if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	326	if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
280	if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	327	if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
281	printf("%B\n", l_apic[LVT_Tm] & 0xff);	328	printf("%B\n", l_apic[LVT_Tm] & 0xff);
282		329
283	for (i=0; i<2; i++) {	330	for (i=0; i<2; i++) {
284	lint = i ? LVT_LINT1 : LVT_LINT0;	331	lint = i ? LVT_LINT1 : LVT_LINT0;
285	printf("LVT_LINT%d: ", i);	332	printf("LVT_LINT%d: ", i);
286	if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	333	if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
287	if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');	334	if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
288	printf("%d", l_apic[lint] & (1<<14)); putchar(',');	335	printf("%d", l_apic[lint] & (1<<14)); putchar(',');
289	printf("%d", l_apic[lint] & (1<<13)); putchar(',');	336	printf("%d", l_apic[lint] & (1<<13)); putchar(',');
290	if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	337	if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
291		338
292	switch ((l_apic[lint]>>8)&7) {	339	switch ((l_apic[lint]>>8)&7) {
293	case 0: printf("fixed"); break;	340	case 0: printf("fixed"); break;
294	case 4: printf("NMI"); break;	341	case 4: printf("NMI"); break;
295	case 7: printf("ExtINT"); break;	342	case 7: printf("ExtINT"); break;
296	}	343	}
297	putchar(',');	344	putchar(',');
298	printf("%B\n", l_apic[lint] & 0xff);	345	printf("%B\n", l_apic[lint] & 0xff);
299	}	346	}
300		347
301	printf("LVT_Err: ");	348	printf("LVT_Err: ");
302	if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	349	if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
303	if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	350	if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
304	printf("%B\n", l_apic[LVT_Err] & 0xff);	351	printf("%B\n", l_apic[LVT_Err] & 0xff);
305		352
306	/*	353	/*
307	* This register is supported only on P6 and higher.	354	* This register is supported only on P6 and higher.
308	*/	355	*/
309	if (CPU->arch.family > 5) {	356	if (CPU->arch.family > 5) {
310	printf("LVT_PCINT: ");	357	printf("LVT_PCINT: ");
311	if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	358	if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
312	if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	359	if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
313	switch ((l_apic[LVT_PCINT] >> 8)&7) {	360	switch ((l_apic[LVT_PCINT] >> 8)&7) {
314	case 0: printf("fixed"); break;	361	case 0: printf("fixed"); break;
315	case 4: printf("NMI"); break;	362	case 4: printf("NMI"); break;
316	case 7: printf("ExtINT"); break;	363	case 7: printf("ExtINT"); break;
317	}	364	}
318	putchar(',');	365	putchar(',');
319	printf("%B\n", l_apic[LVT_PCINT] & 0xff);	366	printf("%B\n", l_apic[LVT_PCINT] & 0xff);
320	}	367	}
321	#endif	368	#endif
322	}	369	}
323		370
324	void l_apic_timer_interrupt(__u8 n, __native stack[])	371	void l_apic_timer_interrupt(__u8 n, __native stack[])
325	{	372	{
326	l_apic_eoi();	373	l_apic_eoi();
327	clock();	374	clock();
328	}	375	}
329		376
330	__u8 l_apic_id(void)	377	__u8 l_apic_id(void)
331	{	378	{
332	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;	379	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
333	}	380	}
334		381
335	__u32 io_apic_read(__u8 address)	382	__u32 io_apic_read(__u8 address)
336	{	383	{
337	__u32 tmp;	384	__u32 tmp;
338		385
339	tmp = io_apic[IOREGSEL] & ~0xf;	386	tmp = io_apic[IOREGSEL] & ~0xf;
340	io_apic[IOREGSEL] = tmp \| address;	387	io_apic[IOREGSEL] = tmp \| address;
341	return io_apic[IOWIN];	388	return io_apic[IOWIN];
342	}	389	}
343		390
344	void io_apic_write(__u8 address, __u32 x)	391	void io_apic_write(__u8 address, __u32 x)
345	{	392	{
346	__u32 tmp;	393	__u32 tmp;
347		394
348	tmp = io_apic[IOREGSEL] & ~0xf;	395	tmp = io_apic[IOREGSEL] & ~0xf;
349	io_apic[IOREGSEL] = tmp \| address;	396	io_apic[IOREGSEL] = tmp \| address;
350	io_apic[IOWIN] = x;	397	io_apic[IOWIN] = x;
351	}	398	}
352		399
353	void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)	400	void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
354	{	401	{
355	io_redirection_reg_t reg;	402	io_redirection_reg_t reg;
356	int dlvr = 0;	403	int dlvr = 0;
357		404
358	if (flags & LOPRI)	405	if (flags & LOPRI)
359	dlvr = DELMOD_LOWPRI;	406	dlvr = DELMOD_LOWPRI;
360		407
361		408
362	reg.lo = io_apic_read(IOREDTBL + signal*2);	409	reg.lo = io_apic_read(IOREDTBL + signal*2);
363	reg.hi = io_apic_read(IOREDTBL + signal*2 + 1);	410	reg.hi = io_apic_read(IOREDTBL + signal*2 + 1);
364		411
365	reg.dest = dest;	412	reg.dest = dest;
366	reg.destmod = DESTMOD_LOGIC;	413	reg.destmod = DESTMOD_LOGIC;
367	reg.trigger_mode = TRIGMOD_EDGE;	414	reg.trigger_mode = TRIGMOD_EDGE;
368	reg.intpol = POLARITY_HIGH;	415	reg.intpol = POLARITY_HIGH;
369	reg.delmod = dlvr;	416	reg.delmod = dlvr;
370	reg.intvec = v;	417	reg.intvec = v;
371		418
372	io_apic_write(IOREDTBL + signal*2, reg.lo);	419	io_apic_write(IOREDTBL + signal*2, reg.lo);
373	io_apic_write(IOREDTBL + signal*2 + 1, reg.hi);	420	io_apic_write(IOREDTBL + signal*2 + 1, reg.hi);
374	}	421	}
375		422
376	void io_apic_disable_irqs(__u16 irqmask)	423	void io_apic_disable_irqs(__u16 irqmask)
377	{	424	{
378	io_redirection_reg_t reg;	425	io_redirection_reg_t reg;
379	int i, pin;	426	int i, pin;
380		427
381	for (i=0;i<16;i++) {	428	for (i=0;i<16;i++) {
382	if ((irqmask>>i) & 1) {	429	if ((irqmask>>i) & 1) {
383	/*	430	/*
384	* Mask the signal input in IO APIC if there is a	431	* Mask the signal input in IO APIC if there is a
385	* mapping for the respective IRQ number.	432	* mapping for the respective IRQ number.
386	*/	433	*/
387	pin = smp_irq_to_pin(i);	434	pin = smp_irq_to_pin(i);
388	if (pin != -1) {	435	if (pin != -1) {
389	reg.lo = io_apic_read(IOREDTBL + pin*2);	436	reg.lo = io_apic_read(IOREDTBL + pin*2);
390	reg.masked = true;	437	reg.masked = true;
391	io_apic_write(IOREDTBL + pin*2, reg.lo);	438	io_apic_write(IOREDTBL + pin*2, reg.lo);
392	}	439	}
393		440
394	}	441	}
395	}	442	}
396	}	443	}
397		444
398	void io_apic_enable_irqs(__u16 irqmask)	445	void io_apic_enable_irqs(__u16 irqmask)
399	{	446	{
400	int i, pin;	447	int i, pin;
401	io_redirection_reg_t reg;	448	io_redirection_reg_t reg;
402		449
403	for (i=0;i<16;i++) {	450	for (i=0;i<16;i++) {
404	if ((irqmask>>i) & 1) {	451	if ((irqmask>>i) & 1) {
405	/*	452	/*
406	* Unmask the signal input in IO APIC if there is a	453	* Unmask the signal input in IO APIC if there is a
407	* mapping for the respective IRQ number.	454	* mapping for the respective IRQ number.
408	*/	455	*/
409	pin = smp_irq_to_pin(i);	456	pin = smp_irq_to_pin(i);
410	if (pin != -1) {	457	if (pin != -1) {
411	reg.lo = io_apic_read(IOREDTBL + pin*2);	458	reg.lo = io_apic_read(IOREDTBL + pin*2);
412	reg.masked = false;	459	reg.masked = false;
413	io_apic_write(IOREDTBL + pin*2, reg.lo);	460	io_apic_write(IOREDTBL + pin*2, reg.lo);
414	}	461	}
415		462
416	}	463	}
417	}	464	}
418		465
419	}	466	}
420		467
421	#endif /* CONFIG_SMP */	468	#endif /* CONFIG_SMP */
422		469

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia32/src/smp/apic.c @ 1768 – Rev 512 → 513