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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/types.h> |
29 | #include <arch/types.h> |
30 | #include <arch/smp/apic.h> |
30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
31 | #include <arch/smp/ap.h> |
32 | #include <arch/smp/mps.h> |
32 | #include <arch/smp/mps.h> |
33 | #include <mm/page.h> |
33 | #include <mm/page.h> |
34 | #include <time/delay.h> |
34 | #include <time/delay.h> |
35 | #include <arch/interrupt.h> |
35 | #include <arch/interrupt.h> |
36 | #include <print.h> |
36 | #include <print.h> |
37 | #include <arch/asm.h> |
37 | #include <arch/asm.h> |
38 | #include <arch.h> |
38 | #include <arch.h> |
39 | 39 | ||
40 | #ifdef CONFIG_SMP |
40 | #ifdef CONFIG_SMP |
41 | 41 | ||
42 | /* |
42 | /* |
43 | * Advanced Programmable Interrupt Controller for SMP systems. |
43 | * Advanced Programmable Interrupt Controller for SMP systems. |
44 | * Tested on: |
44 | * Tested on: |
45 | * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs |
45 | * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs |
46 | * Simics 2.0.28 - Simics 2.2.19 2-8 CPUs |
46 | * Simics 2.0.28 - Simics 2.2.19 2-8 CPUs |
47 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
47 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
48 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
48 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
49 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
49 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
50 | */ |
50 | */ |
51 | 51 | ||
52 | /* |
52 | /* |
53 | * These variables either stay configured as initilalized, or are changed by |
53 | * These variables either stay configured as initilalized, or are changed by |
54 | * the MP configuration code. |
54 | * the MP configuration code. |
55 | * |
55 | * |
56 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
56 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
57 | * optimize the code too much and accesses to l_apic and io_apic, that must |
57 | * optimize the code too much and accesses to l_apic and io_apic, that must |
58 | * always be 32-bit, would use byte oriented instructions. |
58 | * always be 32-bit, would use byte oriented instructions. |
59 | */ |
59 | */ |
60 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
60 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
61 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
61 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
62 | 62 | ||
63 | __u32 apic_id_mask = 0; |
63 | __u32 apic_id_mask = 0; |
64 | 64 | ||
65 | static int apic_poll_errors(void); |
65 | static int apic_poll_errors(void); |
66 | 66 | ||
- | 67 | #ifdef LAPIC_VERBOSE |
|
67 | static char *delmod_str[] = { |
68 | static char *delmod_str[] = { |
68 | "Fixed", |
69 | "Fixed", |
69 | "Lowest Priority", |
70 | "Lowest Priority", |
70 | "SMI", |
71 | "SMI", |
71 | "Reserved", |
72 | "Reserved", |
72 | "NMI", |
73 | "NMI", |
73 | "INIT", |
74 | "INIT", |
74 | "STARTUP", |
75 | "STARTUP", |
75 | "ExtInt" |
76 | "ExtInt" |
76 | }; |
77 | }; |
77 | 78 | ||
78 | static char *destmod_str[] = { |
79 | static char *destmod_str[] = { |
79 | "Physical", |
80 | "Physical", |
80 | "Logical" |
81 | "Logical" |
81 | }; |
82 | }; |
82 | 83 | ||
83 | static char *trigmod_str[] = { |
84 | static char *trigmod_str[] = { |
84 | "Edge", |
85 | "Edge", |
85 | "Level" |
86 | "Level" |
86 | }; |
87 | }; |
87 | 88 | ||
88 | static char *mask_str[] = { |
89 | static char *mask_str[] = { |
89 | "Unmasked", |
90 | "Unmasked", |
90 | "Masked" |
91 | "Masked" |
91 | }; |
92 | }; |
92 | 93 | ||
93 | static char *delivs_str[] = { |
94 | static char *delivs_str[] = { |
94 | "Idle", |
95 | "Idle", |
95 | "Send Pending" |
96 | "Send Pending" |
96 | }; |
97 | }; |
97 | 98 | ||
98 | static char *tm_mode_str[] = { |
99 | static char *tm_mode_str[] = { |
99 | "One-shot", |
100 | "One-shot", |
100 | "Periodic" |
101 | "Periodic" |
101 | }; |
102 | }; |
102 | 103 | ||
103 | static char *intpol_str[] = { |
104 | static char *intpol_str[] = { |
104 | "Polarity High", |
105 | "Polarity High", |
105 | "Polarity Low" |
106 | "Polarity Low" |
106 | }; |
107 | }; |
- | 108 | #endif /* LAPIC_VERBOSE */ |
|
107 | 109 | ||
108 | /** Initialize APIC on BSP. */ |
110 | /** Initialize APIC on BSP. */ |
109 | void apic_init(void) |
111 | void apic_init(void) |
110 | { |
112 | { |
111 | __u32 tmp, id, i; |
113 | io_apic_id_t idreg; |
- | 114 | int i; |
|
112 | 115 | ||
113 | trap_register(VECTOR_APIC_SPUR, apic_spurious); |
116 | trap_register(VECTOR_APIC_SPUR, apic_spurious); |
114 | 117 | ||
115 | enable_irqs_function = io_apic_enable_irqs; |
118 | enable_irqs_function = io_apic_enable_irqs; |
116 | disable_irqs_function = io_apic_disable_irqs; |
119 | disable_irqs_function = io_apic_disable_irqs; |
117 | eoi_function = l_apic_eoi; |
120 | eoi_function = l_apic_eoi; |
118 | 121 | ||
119 | /* |
122 | /* |
120 | * Configure interrupt routing. |
123 | * Configure interrupt routing. |
121 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
124 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
122 | * Other interrupts will be forwarded to the lowest priority CPU. |
125 | * Other interrupts will be forwarded to the lowest priority CPU. |
123 | */ |
126 | */ |
124 | io_apic_disable_irqs(0xffff); |
127 | io_apic_disable_irqs(0xffff); |
125 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
128 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
126 | for (i=0; i<16; i++) { |
129 | for (i = 0; i < IRQ_COUNT; i++) { |
127 | int pin; |
130 | int pin; |
128 | 131 | ||
129 | if ((pin = smp_irq_to_pin(i)) != -1) { |
132 | if ((pin = smp_irq_to_pin(i)) != -1) { |
130 | io_apic_change_ioredtbl(pin, 0xff, IVT_IRQBASE+i, LOPRI); |
133 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
131 | } |
134 | } |
132 | } |
135 | } |
133 | 136 | ||
134 | - | ||
135 | /* |
137 | /* |
136 | * Ensure that io_apic has unique ID. |
138 | * Ensure that io_apic has unique ID. |
137 | */ |
139 | */ |
138 | tmp = io_apic_read(IOAPICID); |
140 | idreg.value = io_apic_read(IOAPICID); |
139 | id = (tmp >> 24) & 0xf; |
- | |
140 | if ((1<<id) & apic_id_mask) { |
141 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
141 | int i; |
- | |
142 | - | ||
143 | for (i=0; i<15; i++) { |
142 | for (i = 0; i < APIC_ID_COUNT; i++) { |
144 | if (!((1<<i) & apic_id_mask)) { |
143 | if (!((1<<i) & apic_id_mask)) { |
- | 144 | idreg.apic_id = i; |
|
145 | io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24)); |
145 | io_apic_write(IOAPICID, idreg.value); |
146 | break; |
146 | break; |
147 | } |
147 | } |
148 | } |
148 | } |
149 | } |
149 | } |
150 | 150 | ||
151 | /* |
151 | /* |
152 | * Configure the BSP's lapic. |
152 | * Configure the BSP's lapic. |
153 | */ |
153 | */ |
154 | l_apic_init(); |
154 | l_apic_init(); |
- | 155 | ||
155 | l_apic_debug(); |
156 | l_apic_debug(); |
156 | } |
157 | } |
157 | 158 | ||
158 | /** APIC spurious interrupt handler. |
159 | /** APIC spurious interrupt handler. |
159 | * |
160 | * |
160 | * @param n Interrupt vector. |
161 | * @param n Interrupt vector. |
161 | * @param stack Interrupted stack. |
162 | * @param stack Interrupted stack. |
162 | */ |
163 | */ |
163 | void apic_spurious(__u8 n, __native stack[]) |
164 | void apic_spurious(__u8 n, __native stack[]) |
164 | { |
165 | { |
165 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
166 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
166 | } |
167 | } |
167 | 168 | ||
168 | /** Poll for APIC errors. |
169 | /** Poll for APIC errors. |
169 | * |
170 | * |
170 | * Examine Error Status Register and report all errors found. |
171 | * Examine Error Status Register and report all errors found. |
171 | * |
172 | * |
172 | * @return 0 on error, 1 on success. |
173 | * @return 0 on error, 1 on success. |
173 | */ |
174 | */ |
174 | int apic_poll_errors(void) |
175 | int apic_poll_errors(void) |
175 | { |
176 | { |
176 | esr_t esr; |
177 | esr_t esr; |
177 | 178 | ||
178 | esr.value = l_apic[ESR]; |
179 | esr.value = l_apic[ESR]; |
179 | 180 | ||
180 | if (esr.send_checksum_error) |
181 | if (esr.send_checksum_error) |
181 | printf("Send CS Error\n"); |
182 | printf("Send Checksum Error\n"); |
182 | if (esr.receive_checksum_error) |
183 | if (esr.receive_checksum_error) |
183 | printf("Receive CS Error\n"); |
184 | printf("Receive Checksum Error\n"); |
184 | if (esr.send_accept_error) |
185 | if (esr.send_accept_error) |
185 | printf("Send Accept Error\n"); |
186 | printf("Send Accept Error\n"); |
186 | if (esr.receive_accept_error) |
187 | if (esr.receive_accept_error) |
187 | printf("Receive Accept Error\n"); |
188 | printf("Receive Accept Error\n"); |
188 | if (esr.send_illegal_vector) |
189 | if (esr.send_illegal_vector) |
189 | printf("Send Illegal Vector\n"); |
190 | printf("Send Illegal Vector\n"); |
190 | if (esr.received_illegal_vector) |
191 | if (esr.received_illegal_vector) |
191 | printf("Received Illegal Vector\n"); |
192 | printf("Received Illegal Vector\n"); |
192 | if (esr.illegal_register_address) |
193 | if (esr.illegal_register_address) |
193 | printf("Illegal Register Address\n"); |
194 | printf("Illegal Register Address\n"); |
194 | 195 | ||
195 | return !esr.err_bitmap; |
196 | return !esr.err_bitmap; |
196 | } |
197 | } |
197 | 198 | ||
198 | /** Send all CPUs excluding CPU IPI vector. |
199 | /** Send all CPUs excluding CPU IPI vector. |
199 | * |
200 | * |
200 | * @param vector Interrupt vector to be sent. |
201 | * @param vector Interrupt vector to be sent. |
201 | * |
202 | * |
202 | * @return 0 on failure, 1 on success. |
203 | * @return 0 on failure, 1 on success. |
203 | */ |
204 | */ |
204 | int l_apic_broadcast_custom_ipi(__u8 vector) |
205 | int l_apic_broadcast_custom_ipi(__u8 vector) |
205 | { |
206 | { |
206 | icr_t icr; |
207 | icr_t icr; |
207 | 208 | ||
208 | icr.lo = l_apic[ICRlo]; |
209 | icr.lo = l_apic[ICRlo]; |
209 | icr.delmod = DELMOD_FIXED; |
210 | icr.delmod = DELMOD_FIXED; |
210 | icr.destmod = DESTMOD_LOGIC; |
211 | icr.destmod = DESTMOD_LOGIC; |
211 | icr.level = LEVEL_ASSERT; |
212 | icr.level = LEVEL_ASSERT; |
212 | icr.shorthand = SHORTHAND_ALL_EXCL; |
213 | icr.shorthand = SHORTHAND_ALL_EXCL; |
213 | icr.trigger_mode = TRIGMOD_LEVEL; |
214 | icr.trigger_mode = TRIGMOD_LEVEL; |
214 | icr.vector = vector; |
215 | icr.vector = vector; |
215 | 216 | ||
216 | l_apic[ICRlo] = icr.lo; |
217 | l_apic[ICRlo] = icr.lo; |
217 | 218 | ||
218 | icr.lo = l_apic[ICRlo]; |
219 | icr.lo = l_apic[ICRlo]; |
219 | if (icr.lo & SEND_PENDING) |
220 | if (icr.delivs == DELIVS_PENDING) |
220 | printf("IPI is pending.\n"); |
221 | printf("IPI is pending.\n"); |
221 | 222 | ||
222 | return apic_poll_errors(); |
223 | return apic_poll_errors(); |
223 | } |
224 | } |
224 | 225 | ||
225 | /** Universal Start-up Algorithm for bringing up the AP processors. |
226 | /** Universal Start-up Algorithm for bringing up the AP processors. |
226 | * |
227 | * |
227 | * @param apicid APIC ID of the processor to be brought up. |
228 | * @param apicid APIC ID of the processor to be brought up. |
228 | * |
229 | * |
229 | * @return 0 on failure, 1 on success. |
230 | * @return 0 on failure, 1 on success. |
230 | */ |
231 | */ |
231 | int l_apic_send_init_ipi(__u8 apicid) |
232 | int l_apic_send_init_ipi(__u8 apicid) |
232 | { |
233 | { |
233 | icr_t icr; |
234 | icr_t icr; |
234 | int i; |
235 | int i; |
235 | 236 | ||
236 | /* |
237 | /* |
237 | * Read the ICR register in and zero all non-reserved fields. |
238 | * Read the ICR register in and zero all non-reserved fields. |
238 | */ |
239 | */ |
239 | icr.lo = l_apic[ICRlo]; |
240 | icr.lo = l_apic[ICRlo]; |
240 | icr.hi = l_apic[ICRhi]; |
241 | icr.hi = l_apic[ICRhi]; |
241 | 242 | ||
242 | icr.delmod = DELMOD_INIT; |
243 | icr.delmod = DELMOD_INIT; |
243 | icr.destmod = DESTMOD_PHYS; |
244 | icr.destmod = DESTMOD_PHYS; |
244 | icr.level = LEVEL_ASSERT; |
245 | icr.level = LEVEL_ASSERT; |
245 | icr.trigger_mode = TRIGMOD_LEVEL; |
246 | icr.trigger_mode = TRIGMOD_LEVEL; |
246 | icr.shorthand = SHORTHAND_NONE; |
247 | icr.shorthand = SHORTHAND_NONE; |
247 | icr.vector = 0; |
248 | icr.vector = 0; |
248 | icr.dest = apicid; |
249 | icr.dest = apicid; |
249 | 250 | ||
250 | l_apic[ICRhi] = icr.hi; |
251 | l_apic[ICRhi] = icr.hi; |
251 | l_apic[ICRlo] = icr.lo; |
252 | l_apic[ICRlo] = icr.lo; |
252 | 253 | ||
253 | /* |
254 | /* |
254 | * According to MP Specification, 20us should be enough to |
255 | * According to MP Specification, 20us should be enough to |
255 | * deliver the IPI. |
256 | * deliver the IPI. |
256 | */ |
257 | */ |
257 | delay(20); |
258 | delay(20); |
258 | 259 | ||
259 | if (!apic_poll_errors()) return 0; |
260 | if (!apic_poll_errors()) return 0; |
260 | 261 | ||
261 | icr.lo = l_apic[ICRlo]; |
262 | icr.lo = l_apic[ICRlo]; |
262 | if (icr.lo & SEND_PENDING) |
263 | if (icr.delivs == DELIVS_PENDING) |
263 | printf("IPI is pending.\n"); |
264 | printf("IPI is pending.\n"); |
264 | 265 | ||
265 | icr.delmod = DELMOD_INIT; |
266 | icr.delmod = DELMOD_INIT; |
266 | icr.destmod = DESTMOD_PHYS; |
267 | icr.destmod = DESTMOD_PHYS; |
267 | icr.level = LEVEL_DEASSERT; |
268 | icr.level = LEVEL_DEASSERT; |
268 | icr.shorthand = SHORTHAND_NONE; |
269 | icr.shorthand = SHORTHAND_NONE; |
269 | icr.trigger_mode = TRIGMOD_LEVEL; |
270 | icr.trigger_mode = TRIGMOD_LEVEL; |
270 | icr.vector = 0; |
271 | icr.vector = 0; |
271 | l_apic[ICRlo] = icr.lo; |
272 | l_apic[ICRlo] = icr.lo; |
272 | 273 | ||
273 | /* |
274 | /* |
274 | * Wait 10ms as MP Specification specifies. |
275 | * Wait 10ms as MP Specification specifies. |
275 | */ |
276 | */ |
276 | delay(10000); |
277 | delay(10000); |
277 | 278 | ||
278 | if (!is_82489DX_apic(l_apic[LAVR])) { |
279 | if (!is_82489DX_apic(l_apic[LAVR])) { |
279 | /* |
280 | /* |
280 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
281 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
281 | */ |
282 | */ |
282 | for (i = 0; i<2; i++) { |
283 | for (i = 0; i<2; i++) { |
283 | icr.lo = l_apic[ICRlo]; |
284 | icr.lo = l_apic[ICRlo]; |
284 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
285 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
285 | icr.delmod = DELMOD_STARTUP; |
286 | icr.delmod = DELMOD_STARTUP; |
286 | icr.destmod = DESTMOD_PHYS; |
287 | icr.destmod = DESTMOD_PHYS; |
287 | icr.level = LEVEL_ASSERT; |
288 | icr.level = LEVEL_ASSERT; |
288 | icr.shorthand = SHORTHAND_NONE; |
289 | icr.shorthand = SHORTHAND_NONE; |
289 | icr.trigger_mode = TRIGMOD_LEVEL; |
290 | icr.trigger_mode = TRIGMOD_LEVEL; |
290 | l_apic[ICRlo] = icr.lo; |
291 | l_apic[ICRlo] = icr.lo; |
291 | delay(200); |
292 | delay(200); |
292 | } |
293 | } |
293 | } |
294 | } |
294 | 295 | ||
295 | - | ||
296 | return apic_poll_errors(); |
296 | return apic_poll_errors(); |
297 | } |
297 | } |
298 | 298 | ||
299 | /** Initialize Local APIC. */ |
299 | /** Initialize Local APIC. */ |
300 | void l_apic_init(void) |
300 | void l_apic_init(void) |
301 | { |
301 | { |
302 | lvt_error_t error; |
302 | lvt_error_t error; |
303 | lvt_lint_t lint; |
303 | lvt_lint_t lint; |
304 | svr_t svr; |
304 | svr_t svr; |
305 | icr_t icr; |
305 | icr_t icr; |
306 | tdcr_t tdcr; |
306 | tdcr_t tdcr; |
307 | lvt_tm_t tm; |
307 | lvt_tm_t tm; |
308 | __u32 t1, t2; |
308 | __u32 t1, t2; |
309 | 309 | ||
310 | /* Initialize LVT Error register. */ |
310 | /* Initialize LVT Error register. */ |
311 | error.value = l_apic[LVT_Err]; |
311 | error.value = l_apic[LVT_Err]; |
312 | error.masked = true; |
312 | error.masked = true; |
313 | l_apic[LVT_Err] = error.value; |
313 | l_apic[LVT_Err] = error.value; |
314 | 314 | ||
315 | /* Initialize LVT LINT0 register. */ |
315 | /* Initialize LVT LINT0 register. */ |
316 | lint.value = l_apic[LVT_LINT0]; |
316 | lint.value = l_apic[LVT_LINT0]; |
317 | lint.masked = true; |
317 | lint.masked = true; |
318 | l_apic[LVT_LINT0] = lint.value; |
318 | l_apic[LVT_LINT0] = lint.value; |
319 | 319 | ||
320 | /* Initialize LVT LINT1 register. */ |
320 | /* Initialize LVT LINT1 register. */ |
321 | lint.value = l_apic[LVT_LINT1]; |
321 | lint.value = l_apic[LVT_LINT1]; |
322 | lint.masked = true; |
322 | lint.masked = true; |
323 | l_apic[LVT_LINT1] = lint.value; |
323 | l_apic[LVT_LINT1] = lint.value; |
324 | 324 | ||
325 | /* Spurious-Interrupt Vector Register initialization. */ |
325 | /* Spurious-Interrupt Vector Register initialization. */ |
326 | svr.value = l_apic[SVR]; |
326 | svr.value = l_apic[SVR]; |
327 | svr.vector = VECTOR_APIC_SPUR; |
327 | svr.vector = VECTOR_APIC_SPUR; |
328 | svr.lapic_enabled = true; |
328 | svr.lapic_enabled = true; |
329 | l_apic[SVR] = svr.value; |
329 | l_apic[SVR] = svr.value; |
330 | 330 | ||
331 | l_apic[TPR] &= TPRClear; |
331 | l_apic[TPR] &= TPRClear; |
332 | 332 | ||
333 | if (CPU->arch.family >= 6) |
333 | if (CPU->arch.family >= 6) |
334 | enable_l_apic_in_msr(); |
334 | enable_l_apic_in_msr(); |
335 | 335 | ||
336 | /* Interrupt Command Register initialization. */ |
336 | /* Interrupt Command Register initialization. */ |
337 | icr.lo = l_apic[ICRlo]; |
337 | icr.lo = l_apic[ICRlo]; |
338 | icr.delmod = DELMOD_INIT; |
338 | icr.delmod = DELMOD_INIT; |
339 | icr.destmod = DESTMOD_PHYS; |
339 | icr.destmod = DESTMOD_PHYS; |
340 | icr.level = LEVEL_DEASSERT; |
340 | icr.level = LEVEL_DEASSERT; |
341 | icr.shorthand = SHORTHAND_ALL_INCL; |
341 | icr.shorthand = SHORTHAND_ALL_INCL; |
342 | icr.trigger_mode = TRIGMOD_LEVEL; |
342 | icr.trigger_mode = TRIGMOD_LEVEL; |
343 | l_apic[ICRlo] = icr.lo; |
343 | l_apic[ICRlo] = icr.lo; |
344 | 344 | ||
345 | /* Timer Divide Configuration Register initialization. */ |
345 | /* Timer Divide Configuration Register initialization. */ |
346 | tdcr.value = l_apic[TDCR]; |
346 | tdcr.value = l_apic[TDCR]; |
347 | tdcr.div_value = DIVIDE_1; |
347 | tdcr.div_value = DIVIDE_1; |
348 | l_apic[TDCR] = tdcr.value; |
348 | l_apic[TDCR] = tdcr.value; |
349 | 349 | ||
350 | /* Program local timer. */ |
350 | /* Program local timer. */ |
351 | tm.value = l_apic[LVT_Tm]; |
351 | tm.value = l_apic[LVT_Tm]; |
352 | tm.vector = VECTOR_CLK; |
352 | tm.vector = VECTOR_CLK; |
353 | tm.mode = TIMER_PERIODIC; |
353 | tm.mode = TIMER_PERIODIC; |
354 | tm.masked = false; |
354 | tm.masked = false; |
355 | l_apic[LVT_Tm] = tm.value; |
355 | l_apic[LVT_Tm] = tm.value; |
356 | 356 | ||
357 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
357 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
358 | t1 = l_apic[CCRT]; |
358 | t1 = l_apic[CCRT]; |
359 | l_apic[ICRT] = 0xffffffff; |
359 | l_apic[ICRT] = 0xffffffff; |
360 | 360 | ||
361 | while (l_apic[CCRT] == t1) |
361 | while (l_apic[CCRT] == t1) |
362 | ; |
362 | ; |
363 | 363 | ||
364 | t1 = l_apic[CCRT]; |
364 | t1 = l_apic[CCRT]; |
365 | delay(1000); |
365 | delay(1000); |
366 | t2 = l_apic[CCRT]; |
366 | t2 = l_apic[CCRT]; |
367 | 367 | ||
368 | l_apic[ICRT] = t1-t2; |
368 | l_apic[ICRT] = t1-t2; |
369 | - | ||
370 | } |
369 | } |
371 | 370 | ||
372 | /** Local APIC End of Interrupt. */ |
371 | /** Local APIC End of Interrupt. */ |
373 | void l_apic_eoi(void) |
372 | void l_apic_eoi(void) |
374 | { |
373 | { |
375 | l_apic[EOI] = 0; |
374 | l_apic[EOI] = 0; |
376 | } |
375 | } |
377 | 376 | ||
378 | /** Dump content of Local APIC registers. */ |
377 | /** Dump content of Local APIC registers. */ |
379 | void l_apic_debug(void) |
378 | void l_apic_debug(void) |
380 | { |
379 | { |
381 | #ifdef LAPIC_VERBOSE |
380 | #ifdef LAPIC_VERBOSE |
382 | lvt_tm_t tm; |
381 | lvt_tm_t tm; |
383 | lvt_lint_t lint; |
382 | lvt_lint_t lint; |
384 | lvt_error_t error; |
383 | lvt_error_t error; |
385 | 384 | ||
386 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
385 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
387 | 386 | ||
388 | tm.value = l_apic[LVT_Tm]; |
387 | tm.value = l_apic[LVT_Tm]; |
389 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
388 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
390 | lint.value = l_apic[LVT_LINT0]; |
389 | lint.value = l_apic[LVT_LINT0]; |
391 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
390 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
392 | lint.value = l_apic[LVT_LINT1]; |
391 | lint.value = l_apic[LVT_LINT1]; |
393 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
392 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
394 | error.value = l_apic[LVT_Err]; |
393 | error.value = l_apic[LVT_Err]; |
395 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
394 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
396 | #endif |
395 | #endif |
397 | } |
396 | } |
398 | 397 | ||
399 | /** Local APIC Timer Interrupt. |
398 | /** Local APIC Timer Interrupt. |
400 | * |
399 | * |
401 | * @param n Interrupt vector number. |
400 | * @param n Interrupt vector number. |
402 | * @param stack Interrupted stack. |
401 | * @param stack Interrupted stack. |
403 | */ |
402 | */ |
404 | void l_apic_timer_interrupt(__u8 n, __native stack[]) |
403 | void l_apic_timer_interrupt(__u8 n, __native stack[]) |
405 | { |
404 | { |
406 | l_apic_eoi(); |
405 | l_apic_eoi(); |
407 | clock(); |
406 | clock(); |
408 | } |
407 | } |
409 | 408 | ||
410 | /** Get Local APIC ID. |
409 | /** Get Local APIC ID. |
411 | * |
410 | * |
412 | * @return Local APIC ID. |
411 | * @return Local APIC ID. |
413 | */ |
412 | */ |
414 | __u8 l_apic_id(void) |
413 | __u8 l_apic_id(void) |
415 | { |
414 | { |
416 | lapic_id_t lapic_id; |
415 | l_apic_id_t idreg; |
417 | 416 | ||
418 | lapic_id.value = l_apic[L_APIC_ID]; |
417 | idreg.value = l_apic[L_APIC_ID]; |
419 | return lapic_id.apic_id; |
418 | return idreg.apic_id; |
420 | } |
419 | } |
421 | 420 | ||
422 | /** Read from IO APIC register. |
421 | /** Read from IO APIC register. |
423 | * |
422 | * |
424 | * @param address IO APIC register address. |
423 | * @param address IO APIC register address. |
425 | * |
424 | * |
426 | * @return Content of the addressed IO APIC register. |
425 | * @return Content of the addressed IO APIC register. |
427 | */ |
426 | */ |
428 | __u32 io_apic_read(__u8 address) |
427 | __u32 io_apic_read(__u8 address) |
429 | { |
428 | { |
430 | io_regsel_t regsel; |
429 | io_regsel_t regsel; |
431 | 430 | ||
432 | regsel.value = io_apic[IOREGSEL]; |
431 | regsel.value = io_apic[IOREGSEL]; |
433 | regsel.reg_addr = address; |
432 | regsel.reg_addr = address; |
434 | io_apic[IOREGSEL] = regsel.value; |
433 | io_apic[IOREGSEL] = regsel.value; |
435 | return io_apic[IOWIN]; |
434 | return io_apic[IOWIN]; |
436 | } |
435 | } |
437 | 436 | ||
438 | /** Write to IO APIC register. |
437 | /** Write to IO APIC register. |
439 | * |
438 | * |
440 | * @param address IO APIC register address. |
439 | * @param address IO APIC register address. |
441 | * @param Content to be written to the addressed IO APIC register. |
440 | * @param Content to be written to the addressed IO APIC register. |
442 | */ |
441 | */ |
443 | void io_apic_write(__u8 address, __u32 x) |
442 | void io_apic_write(__u8 address, __u32 x) |
444 | { |
443 | { |
445 | io_regsel_t regsel; |
444 | io_regsel_t regsel; |
446 | 445 | ||
447 | regsel.value = io_apic[IOREGSEL]; |
446 | regsel.value = io_apic[IOREGSEL]; |
448 | regsel.reg_addr = address; |
447 | regsel.reg_addr = address; |
449 | io_apic[IOREGSEL] = regsel.value; |
448 | io_apic[IOREGSEL] = regsel.value; |
450 | io_apic[IOWIN] = x; |
449 | io_apic[IOWIN] = x; |
451 | } |
450 | } |
452 | 451 | ||
453 | /** Change some attributes of one item in I/O Redirection Table. |
452 | /** Change some attributes of one item in I/O Redirection Table. |
454 | * |
453 | * |
455 | * @param pin IO APIC pin number. |
454 | * @param pin IO APIC pin number. |
456 | * @param dest Interrupt destination address. |
455 | * @param dest Interrupt destination address. |
457 | * @param v Interrupt vector to trigger. |
456 | * @param v Interrupt vector to trigger. |
458 | * @param flags Flags. |
457 | * @param flags Flags. |
459 | */ |
458 | */ |
460 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
459 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
461 | { |
460 | { |
462 | io_redirection_reg_t reg; |
461 | io_redirection_reg_t reg; |
463 | int dlvr = DELMOD_FIXED; |
462 | int dlvr = DELMOD_FIXED; |
464 | 463 | ||
465 | if (flags & LOPRI) |
464 | if (flags & LOPRI) |
466 | dlvr = DELMOD_LOWPRI; |
465 | dlvr = DELMOD_LOWPRI; |
467 | 466 | ||
468 | 467 | ||
469 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
468 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
470 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
469 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
471 | 470 | ||
472 | reg.dest = dest; |
471 | reg.dest = dest; |
473 | reg.destmod = DESTMOD_LOGIC; |
472 | reg.destmod = DESTMOD_LOGIC; |
474 | reg.trigger_mode = TRIGMOD_EDGE; |
473 | reg.trigger_mode = TRIGMOD_EDGE; |
475 | reg.intpol = POLARITY_HIGH; |
474 | reg.intpol = POLARITY_HIGH; |
476 | reg.delmod = dlvr; |
475 | reg.delmod = dlvr; |
477 | reg.intvec = v; |
476 | reg.intvec = v; |
478 | 477 | ||
479 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
478 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
480 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
479 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
481 | } |
480 | } |
482 | 481 | ||
483 | /** Mask IRQs in IO APIC. |
482 | /** Mask IRQs in IO APIC. |
484 | * |
483 | * |
485 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
484 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
486 | */ |
485 | */ |
487 | void io_apic_disable_irqs(__u16 irqmask) |
486 | void io_apic_disable_irqs(__u16 irqmask) |
488 | { |
487 | { |
489 | io_redirection_reg_t reg; |
488 | io_redirection_reg_t reg; |
490 | int i, pin; |
489 | int i, pin; |
491 | 490 | ||
492 | for (i=0;i<16;i++) { |
491 | for (i=0;i<16;i++) { |
493 | if ((irqmask>>i) & 1) { |
492 | if (irqmask & (1<<i)) { |
494 | /* |
493 | /* |
495 | * Mask the signal input in IO APIC if there is a |
494 | * Mask the signal input in IO APIC if there is a |
496 | * mapping for the respective IRQ number. |
495 | * mapping for the respective IRQ number. |
497 | */ |
496 | */ |
498 | pin = smp_irq_to_pin(i); |
497 | pin = smp_irq_to_pin(i); |
499 | if (pin != -1) { |
498 | if (pin != -1) { |
500 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
499 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
501 | reg.masked = true; |
500 | reg.masked = true; |
502 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
501 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
503 | } |
502 | } |
504 | 503 | ||
505 | } |
504 | } |
506 | } |
505 | } |
507 | } |
506 | } |
508 | 507 | ||
509 | /** Unmask IRQs in IO APIC. |
508 | /** Unmask IRQs in IO APIC. |
510 | * |
509 | * |
511 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
510 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
512 | */ |
511 | */ |
513 | void io_apic_enable_irqs(__u16 irqmask) |
512 | void io_apic_enable_irqs(__u16 irqmask) |
514 | { |
513 | { |
515 | int i, pin; |
514 | int i, pin; |
516 | io_redirection_reg_t reg; |
515 | io_redirection_reg_t reg; |
517 | 516 | ||
518 | for (i=0;i<16;i++) { |
517 | for (i=0;i<16;i++) { |
519 | if ((irqmask>>i) & 1) { |
518 | if (irqmask & (1<<i)) { |
520 | /* |
519 | /* |
521 | * Unmask the signal input in IO APIC if there is a |
520 | * Unmask the signal input in IO APIC if there is a |
522 | * mapping for the respective IRQ number. |
521 | * mapping for the respective IRQ number. |
523 | */ |
522 | */ |
524 | pin = smp_irq_to_pin(i); |
523 | pin = smp_irq_to_pin(i); |
525 | if (pin != -1) { |
524 | if (pin != -1) { |
526 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
525 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
527 | reg.masked = false; |
526 | reg.masked = false; |
528 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
527 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
529 | } |
528 | } |
530 | 529 | ||
531 | } |
530 | } |
532 | } |
531 | } |
533 | - | ||
534 | } |
532 | } |
535 | 533 | ||
536 | #endif /* CONFIG_SMP */ |
534 | #endif /* CONFIG_SMP */ |
537 | 535 |