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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/types.h> |
29 | #include <arch/types.h> |
30 | #include <arch/smp/apic.h> |
30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
31 | #include <arch/smp/ap.h> |
32 | #include <arch/smp/mps.h> |
32 | #include <arch/smp/mps.h> |
33 | #include <mm/page.h> |
33 | #include <mm/page.h> |
34 | #include <time/delay.h> |
34 | #include <time/delay.h> |
35 | #include <interrupt.h> |
35 | #include <interrupt.h> |
36 | #include <arch/interrupt.h> |
36 | #include <arch/interrupt.h> |
37 | #include <print.h> |
37 | #include <print.h> |
38 | #include <arch/asm.h> |
38 | #include <arch/asm.h> |
39 | #include <arch.h> |
39 | #include <arch.h> |
40 | 40 | ||
41 | #ifdef CONFIG_SMP |
41 | #ifdef CONFIG_SMP |
42 | 42 | ||
43 | /* |
43 | /* |
44 | * Advanced Programmable Interrupt Controller for SMP systems. |
44 | * Advanced Programmable Interrupt Controller for SMP systems. |
45 | * Tested on: |
45 | * Tested on: |
46 | * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs |
46 | * Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs |
47 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
47 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
48 | * VMware Workstation 5.5 with 2 CPUs |
48 | * VMware Workstation 5.5 with 2 CPUs |
49 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
49 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
50 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
50 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
51 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
51 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
52 | */ |
52 | */ |
53 | 53 | ||
54 | /* |
54 | /* |
55 | * These variables either stay configured as initilalized, or are changed by |
55 | * These variables either stay configured as initilalized, or are changed by |
56 | * the MP configuration code. |
56 | * the MP configuration code. |
57 | * |
57 | * |
58 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
58 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
59 | * optimize the code too much and accesses to l_apic and io_apic, that must |
59 | * optimize the code too much and accesses to l_apic and io_apic, that must |
60 | * always be 32-bit, would use byte oriented instructions. |
60 | * always be 32-bit, would use byte oriented instructions. |
61 | */ |
61 | */ |
62 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
62 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
63 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
63 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
64 | 64 | ||
65 | __u32 apic_id_mask = 0; |
65 | __u32 apic_id_mask = 0; |
66 | 66 | ||
67 | static int apic_poll_errors(void); |
67 | static int apic_poll_errors(void); |
68 | 68 | ||
69 | #ifdef LAPIC_VERBOSE |
69 | #ifdef LAPIC_VERBOSE |
70 | static char *delmod_str[] = { |
70 | static char *delmod_str[] = { |
71 | "Fixed", |
71 | "Fixed", |
72 | "Lowest Priority", |
72 | "Lowest Priority", |
73 | "SMI", |
73 | "SMI", |
74 | "Reserved", |
74 | "Reserved", |
75 | "NMI", |
75 | "NMI", |
76 | "INIT", |
76 | "INIT", |
77 | "STARTUP", |
77 | "STARTUP", |
78 | "ExtInt" |
78 | "ExtInt" |
79 | }; |
79 | }; |
80 | 80 | ||
81 | static char *destmod_str[] = { |
81 | static char *destmod_str[] = { |
82 | "Physical", |
82 | "Physical", |
83 | "Logical" |
83 | "Logical" |
84 | }; |
84 | }; |
85 | 85 | ||
86 | static char *trigmod_str[] = { |
86 | static char *trigmod_str[] = { |
87 | "Edge", |
87 | "Edge", |
88 | "Level" |
88 | "Level" |
89 | }; |
89 | }; |
90 | 90 | ||
91 | static char *mask_str[] = { |
91 | static char *mask_str[] = { |
92 | "Unmasked", |
92 | "Unmasked", |
93 | "Masked" |
93 | "Masked" |
94 | }; |
94 | }; |
95 | 95 | ||
96 | static char *delivs_str[] = { |
96 | static char *delivs_str[] = { |
97 | "Idle", |
97 | "Idle", |
98 | "Send Pending" |
98 | "Send Pending" |
99 | }; |
99 | }; |
100 | 100 | ||
101 | static char *tm_mode_str[] = { |
101 | static char *tm_mode_str[] = { |
102 | "One-shot", |
102 | "One-shot", |
103 | "Periodic" |
103 | "Periodic" |
104 | }; |
104 | }; |
105 | 105 | ||
106 | static char *intpol_str[] = { |
106 | static char *intpol_str[] = { |
107 | "Polarity High", |
107 | "Polarity High", |
108 | "Polarity Low" |
108 | "Polarity Low" |
109 | }; |
109 | }; |
110 | #endif /* LAPIC_VERBOSE */ |
110 | #endif /* LAPIC_VERBOSE */ |
111 | 111 | ||
112 | 112 | ||
113 | static void apic_spurious(int n, void *stack); |
113 | static void apic_spurious(int n, void *stack); |
114 | static void l_apic_timer_interrupt(int n, void *stack); |
114 | static void l_apic_timer_interrupt(int n, void *stack); |
115 | 115 | ||
116 | /** Initialize APIC on BSP. */ |
116 | /** Initialize APIC on BSP. */ |
117 | void apic_init(void) |
117 | void apic_init(void) |
118 | { |
118 | { |
119 | io_apic_id_t idreg; |
119 | io_apic_id_t idreg; |
120 | int i; |
120 | int i; |
121 | 121 | ||
122 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious); |
122 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious); |
123 | 123 | ||
124 | enable_irqs_function = io_apic_enable_irqs; |
124 | enable_irqs_function = io_apic_enable_irqs; |
125 | disable_irqs_function = io_apic_disable_irqs; |
125 | disable_irqs_function = io_apic_disable_irqs; |
126 | eoi_function = l_apic_eoi; |
126 | eoi_function = l_apic_eoi; |
127 | 127 | ||
128 | /* |
128 | /* |
129 | * Configure interrupt routing. |
129 | * Configure interrupt routing. |
130 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
130 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
131 | * Other interrupts will be forwarded to the lowest priority CPU. |
131 | * Other interrupts will be forwarded to the lowest priority CPU. |
132 | */ |
132 | */ |
133 | io_apic_disable_irqs(0xffff); |
133 | io_apic_disable_irqs(0xffff); |
134 | exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt); |
134 | exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt); |
135 | for (i = 0; i < IRQ_COUNT; i++) { |
135 | for (i = 0; i < IRQ_COUNT; i++) { |
136 | int pin; |
136 | int pin; |
137 | 137 | ||
138 | if ((pin = smp_irq_to_pin(i)) != -1) { |
138 | if ((pin = smp_irq_to_pin(i)) != -1) { |
139 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
139 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
140 | } |
140 | } |
141 | } |
141 | } |
142 | 142 | ||
143 | /* |
143 | /* |
144 | * Ensure that io_apic has unique ID. |
144 | * Ensure that io_apic has unique ID. |
145 | */ |
145 | */ |
146 | idreg.value = io_apic_read(IOAPICID); |
146 | idreg.value = io_apic_read(IOAPICID); |
147 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
147 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
148 | for (i = 0; i < APIC_ID_COUNT; i++) { |
148 | for (i = 0; i < APIC_ID_COUNT; i++) { |
149 | if (!((1<<i) & apic_id_mask)) { |
149 | if (!((1<<i) & apic_id_mask)) { |
150 | idreg.apic_id = i; |
150 | idreg.apic_id = i; |
151 | io_apic_write(IOAPICID, idreg.value); |
151 | io_apic_write(IOAPICID, idreg.value); |
152 | break; |
152 | break; |
153 | } |
153 | } |
154 | } |
154 | } |
155 | } |
155 | } |
156 | 156 | ||
157 | /* |
157 | /* |
158 | * Configure the BSP's lapic. |
158 | * Configure the BSP's lapic. |
159 | */ |
159 | */ |
160 | l_apic_init(); |
160 | l_apic_init(); |
161 | 161 | ||
162 | l_apic_debug(); |
162 | l_apic_debug(); |
163 | } |
163 | } |
164 | 164 | ||
165 | /** APIC spurious interrupt handler. |
165 | /** APIC spurious interrupt handler. |
166 | * |
166 | * |
167 | * @param n Interrupt vector. |
167 | * @param n Interrupt vector. |
168 | * @param stack Interrupted stack. |
168 | * @param stack Interrupted stack. |
169 | */ |
169 | */ |
170 | void apic_spurious(int n, void *stack) |
170 | void apic_spurious(int n, void *stack) |
171 | { |
171 | { |
172 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
172 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
173 | } |
173 | } |
174 | 174 | ||
175 | /** Poll for APIC errors. |
175 | /** Poll for APIC errors. |
176 | * |
176 | * |
177 | * Examine Error Status Register and report all errors found. |
177 | * Examine Error Status Register and report all errors found. |
178 | * |
178 | * |
179 | * @return 0 on error, 1 on success. |
179 | * @return 0 on error, 1 on success. |
180 | */ |
180 | */ |
181 | int apic_poll_errors(void) |
181 | int apic_poll_errors(void) |
182 | { |
182 | { |
183 | esr_t esr; |
183 | esr_t esr; |
184 | 184 | ||
185 | esr.value = l_apic[ESR]; |
185 | esr.value = l_apic[ESR]; |
186 | 186 | ||
187 | if (esr.send_checksum_error) |
187 | if (esr.send_checksum_error) |
188 | printf("Send Checksum Error\n"); |
188 | printf("Send Checksum Error\n"); |
189 | if (esr.receive_checksum_error) |
189 | if (esr.receive_checksum_error) |
190 | printf("Receive Checksum Error\n"); |
190 | printf("Receive Checksum Error\n"); |
191 | if (esr.send_accept_error) |
191 | if (esr.send_accept_error) |
192 | printf("Send Accept Error\n"); |
192 | printf("Send Accept Error\n"); |
193 | if (esr.receive_accept_error) |
193 | if (esr.receive_accept_error) |
194 | printf("Receive Accept Error\n"); |
194 | printf("Receive Accept Error\n"); |
195 | if (esr.send_illegal_vector) |
195 | if (esr.send_illegal_vector) |
196 | printf("Send Illegal Vector\n"); |
196 | printf("Send Illegal Vector\n"); |
197 | if (esr.received_illegal_vector) |
197 | if (esr.received_illegal_vector) |
198 | printf("Received Illegal Vector\n"); |
198 | printf("Received Illegal Vector\n"); |
199 | if (esr.illegal_register_address) |
199 | if (esr.illegal_register_address) |
200 | printf("Illegal Register Address\n"); |
200 | printf("Illegal Register Address\n"); |
201 | 201 | ||
202 | return !esr.err_bitmap; |
202 | return !esr.err_bitmap; |
203 | } |
203 | } |
204 | 204 | ||
205 | /** Send all CPUs excluding CPU IPI vector. |
205 | /** Send all CPUs excluding CPU IPI vector. |
206 | * |
206 | * |
207 | * @param vector Interrupt vector to be sent. |
207 | * @param vector Interrupt vector to be sent. |
208 | * |
208 | * |
209 | * @return 0 on failure, 1 on success. |
209 | * @return 0 on failure, 1 on success. |
210 | */ |
210 | */ |
211 | int l_apic_broadcast_custom_ipi(__u8 vector) |
211 | int l_apic_broadcast_custom_ipi(__u8 vector) |
212 | { |
212 | { |
213 | icr_t icr; |
213 | icr_t icr; |
214 | 214 | ||
215 | icr.lo = l_apic[ICRlo]; |
215 | icr.lo = l_apic[ICRlo]; |
216 | icr.delmod = DELMOD_FIXED; |
216 | icr.delmod = DELMOD_FIXED; |
217 | icr.destmod = DESTMOD_LOGIC; |
217 | icr.destmod = DESTMOD_LOGIC; |
218 | icr.level = LEVEL_ASSERT; |
218 | icr.level = LEVEL_ASSERT; |
219 | icr.shorthand = SHORTHAND_ALL_EXCL; |
219 | icr.shorthand = SHORTHAND_ALL_EXCL; |
220 | icr.trigger_mode = TRIGMOD_LEVEL; |
220 | icr.trigger_mode = TRIGMOD_LEVEL; |
221 | icr.vector = vector; |
221 | icr.vector = vector; |
222 | 222 | ||
223 | l_apic[ICRlo] = icr.lo; |
223 | l_apic[ICRlo] = icr.lo; |
224 | 224 | ||
225 | icr.lo = l_apic[ICRlo]; |
225 | icr.lo = l_apic[ICRlo]; |
226 | if (icr.delivs == DELIVS_PENDING) |
226 | if (icr.delivs == DELIVS_PENDING) |
227 | printf("IPI is pending.\n"); |
227 | printf("IPI is pending.\n"); |
228 | 228 | ||
229 | return apic_poll_errors(); |
229 | return apic_poll_errors(); |
230 | } |
230 | } |
231 | 231 | ||
232 | /** Universal Start-up Algorithm for bringing up the AP processors. |
232 | /** Universal Start-up Algorithm for bringing up the AP processors. |
233 | * |
233 | * |
234 | * @param apicid APIC ID of the processor to be brought up. |
234 | * @param apicid APIC ID of the processor to be brought up. |
235 | * |
235 | * |
236 | * @return 0 on failure, 1 on success. |
236 | * @return 0 on failure, 1 on success. |
237 | */ |
237 | */ |
238 | int l_apic_send_init_ipi(__u8 apicid) |
238 | int l_apic_send_init_ipi(__u8 apicid) |
239 | { |
239 | { |
240 | icr_t icr; |
240 | icr_t icr; |
241 | int i; |
241 | int i; |
242 | 242 | ||
243 | /* |
243 | /* |
244 | * Read the ICR register in and zero all non-reserved fields. |
244 | * Read the ICR register in and zero all non-reserved fields. |
245 | */ |
245 | */ |
246 | icr.lo = l_apic[ICRlo]; |
246 | icr.lo = l_apic[ICRlo]; |
247 | icr.hi = l_apic[ICRhi]; |
247 | icr.hi = l_apic[ICRhi]; |
248 | 248 | ||
249 | icr.delmod = DELMOD_INIT; |
249 | icr.delmod = DELMOD_INIT; |
250 | icr.destmod = DESTMOD_PHYS; |
250 | icr.destmod = DESTMOD_PHYS; |
251 | icr.level = LEVEL_ASSERT; |
251 | icr.level = LEVEL_ASSERT; |
252 | icr.trigger_mode = TRIGMOD_LEVEL; |
252 | icr.trigger_mode = TRIGMOD_LEVEL; |
253 | icr.shorthand = SHORTHAND_NONE; |
253 | icr.shorthand = SHORTHAND_NONE; |
254 | icr.vector = 0; |
254 | icr.vector = 0; |
255 | icr.dest = apicid; |
255 | icr.dest = apicid; |
256 | 256 | ||
257 | l_apic[ICRhi] = icr.hi; |
257 | l_apic[ICRhi] = icr.hi; |
258 | l_apic[ICRlo] = icr.lo; |
258 | l_apic[ICRlo] = icr.lo; |
259 | 259 | ||
260 | /* |
260 | /* |
261 | * According to MP Specification, 20us should be enough to |
261 | * According to MP Specification, 20us should be enough to |
262 | * deliver the IPI. |
262 | * deliver the IPI. |
263 | */ |
263 | */ |
264 | delay(20); |
264 | delay(20); |
265 | 265 | ||
266 | if (!apic_poll_errors()) return 0; |
266 | if (!apic_poll_errors()) return 0; |
267 | 267 | ||
268 | icr.lo = l_apic[ICRlo]; |
268 | icr.lo = l_apic[ICRlo]; |
269 | if (icr.delivs == DELIVS_PENDING) |
269 | if (icr.delivs == DELIVS_PENDING) |
270 | printf("IPI is pending.\n"); |
270 | printf("IPI is pending.\n"); |
271 | 271 | ||
272 | icr.delmod = DELMOD_INIT; |
272 | icr.delmod = DELMOD_INIT; |
273 | icr.destmod = DESTMOD_PHYS; |
273 | icr.destmod = DESTMOD_PHYS; |
274 | icr.level = LEVEL_DEASSERT; |
274 | icr.level = LEVEL_DEASSERT; |
275 | icr.shorthand = SHORTHAND_NONE; |
275 | icr.shorthand = SHORTHAND_NONE; |
276 | icr.trigger_mode = TRIGMOD_LEVEL; |
276 | icr.trigger_mode = TRIGMOD_LEVEL; |
277 | icr.vector = 0; |
277 | icr.vector = 0; |
278 | l_apic[ICRlo] = icr.lo; |
278 | l_apic[ICRlo] = icr.lo; |
279 | 279 | ||
280 | /* |
280 | /* |
281 | * Wait 10ms as MP Specification specifies. |
281 | * Wait 10ms as MP Specification specifies. |
282 | */ |
282 | */ |
283 | delay(10000); |
283 | delay(10000); |
284 | 284 | ||
285 | if (!is_82489DX_apic(l_apic[LAVR])) { |
285 | if (!is_82489DX_apic(l_apic[LAVR])) { |
286 | /* |
286 | /* |
287 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
287 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
288 | */ |
288 | */ |
289 | for (i = 0; i<2; i++) { |
289 | for (i = 0; i<2; i++) { |
290 | icr.lo = l_apic[ICRlo]; |
290 | icr.lo = l_apic[ICRlo]; |
291 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
291 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
292 | icr.delmod = DELMOD_STARTUP; |
292 | icr.delmod = DELMOD_STARTUP; |
293 | icr.destmod = DESTMOD_PHYS; |
293 | icr.destmod = DESTMOD_PHYS; |
294 | icr.level = LEVEL_ASSERT; |
294 | icr.level = LEVEL_ASSERT; |
295 | icr.shorthand = SHORTHAND_NONE; |
295 | icr.shorthand = SHORTHAND_NONE; |
296 | icr.trigger_mode = TRIGMOD_LEVEL; |
296 | icr.trigger_mode = TRIGMOD_LEVEL; |
297 | l_apic[ICRlo] = icr.lo; |
297 | l_apic[ICRlo] = icr.lo; |
298 | delay(200); |
298 | delay(200); |
299 | } |
299 | } |
300 | } |
300 | } |
301 | 301 | ||
302 | return apic_poll_errors(); |
302 | return apic_poll_errors(); |
303 | } |
303 | } |
304 | 304 | ||
305 | /** Initialize Local APIC. */ |
305 | /** Initialize Local APIC. */ |
306 | void l_apic_init(void) |
306 | void l_apic_init(void) |
307 | { |
307 | { |
308 | lvt_error_t error; |
308 | lvt_error_t error; |
309 | lvt_lint_t lint; |
309 | lvt_lint_t lint; |
310 | svr_t svr; |
310 | svr_t svr; |
311 | icr_t icr; |
311 | icr_t icr; |
312 | tdcr_t tdcr; |
312 | tdcr_t tdcr; |
313 | lvt_tm_t tm; |
313 | lvt_tm_t tm; |
- | 314 | ldr_t ldr; |
|
- | 315 | dfr_t dfr; |
|
314 | __u32 t1, t2; |
316 | __u32 t1, t2; |
315 | 317 | ||
316 | /* Initialize LVT Error register. */ |
318 | /* Initialize LVT Error register. */ |
317 | error.value = l_apic[LVT_Err]; |
319 | error.value = l_apic[LVT_Err]; |
318 | error.masked = true; |
320 | error.masked = true; |
319 | l_apic[LVT_Err] = error.value; |
321 | l_apic[LVT_Err] = error.value; |
320 | 322 | ||
321 | /* Initialize LVT LINT0 register. */ |
323 | /* Initialize LVT LINT0 register. */ |
322 | lint.value = l_apic[LVT_LINT0]; |
324 | lint.value = l_apic[LVT_LINT0]; |
323 | lint.masked = true; |
325 | lint.masked = true; |
324 | l_apic[LVT_LINT0] = lint.value; |
326 | l_apic[LVT_LINT0] = lint.value; |
325 | 327 | ||
326 | /* Initialize LVT LINT1 register. */ |
328 | /* Initialize LVT LINT1 register. */ |
327 | lint.value = l_apic[LVT_LINT1]; |
329 | lint.value = l_apic[LVT_LINT1]; |
328 | lint.masked = true; |
330 | lint.masked = true; |
329 | l_apic[LVT_LINT1] = lint.value; |
331 | l_apic[LVT_LINT1] = lint.value; |
330 | 332 | ||
331 | /* Spurious-Interrupt Vector Register initialization. */ |
333 | /* Spurious-Interrupt Vector Register initialization. */ |
332 | svr.value = l_apic[SVR]; |
334 | svr.value = l_apic[SVR]; |
333 | svr.vector = VECTOR_APIC_SPUR; |
335 | svr.vector = VECTOR_APIC_SPUR; |
334 | svr.lapic_enabled = true; |
336 | svr.lapic_enabled = true; |
335 | l_apic[SVR] = svr.value; |
337 | l_apic[SVR] = svr.value; |
336 | 338 | ||
337 | l_apic[TPR] &= TPRClear; |
339 | l_apic[TPR] &= TPRClear; |
338 | 340 | ||
339 | if (CPU->arch.family >= 6) |
341 | if (CPU->arch.family >= 6) |
340 | enable_l_apic_in_msr(); |
342 | enable_l_apic_in_msr(); |
341 | 343 | ||
342 | /* Interrupt Command Register initialization. */ |
344 | /* Interrupt Command Register initialization. */ |
343 | icr.lo = l_apic[ICRlo]; |
345 | icr.lo = l_apic[ICRlo]; |
344 | icr.delmod = DELMOD_INIT; |
346 | icr.delmod = DELMOD_INIT; |
345 | icr.destmod = DESTMOD_PHYS; |
347 | icr.destmod = DESTMOD_PHYS; |
346 | icr.level = LEVEL_DEASSERT; |
348 | icr.level = LEVEL_DEASSERT; |
347 | icr.shorthand = SHORTHAND_ALL_INCL; |
349 | icr.shorthand = SHORTHAND_ALL_INCL; |
348 | icr.trigger_mode = TRIGMOD_LEVEL; |
350 | icr.trigger_mode = TRIGMOD_LEVEL; |
349 | l_apic[ICRlo] = icr.lo; |
351 | l_apic[ICRlo] = icr.lo; |
350 | 352 | ||
351 | /* Timer Divide Configuration Register initialization. */ |
353 | /* Timer Divide Configuration Register initialization. */ |
352 | tdcr.value = l_apic[TDCR]; |
354 | tdcr.value = l_apic[TDCR]; |
353 | tdcr.div_value = DIVIDE_1; |
355 | tdcr.div_value = DIVIDE_1; |
354 | l_apic[TDCR] = tdcr.value; |
356 | l_apic[TDCR] = tdcr.value; |
355 | 357 | ||
356 | /* Program local timer. */ |
358 | /* Program local timer. */ |
357 | tm.value = l_apic[LVT_Tm]; |
359 | tm.value = l_apic[LVT_Tm]; |
358 | tm.vector = VECTOR_CLK; |
360 | tm.vector = VECTOR_CLK; |
359 | tm.mode = TIMER_PERIODIC; |
361 | tm.mode = TIMER_PERIODIC; |
360 | tm.masked = false; |
362 | tm.masked = false; |
361 | l_apic[LVT_Tm] = tm.value; |
363 | l_apic[LVT_Tm] = tm.value; |
362 | 364 | ||
363 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
365 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
364 | t1 = l_apic[CCRT]; |
366 | t1 = l_apic[CCRT]; |
365 | l_apic[ICRT] = 0xffffffff; |
367 | l_apic[ICRT] = 0xffffffff; |
366 | 368 | ||
367 | while (l_apic[CCRT] == t1) |
369 | while (l_apic[CCRT] == t1) |
368 | ; |
370 | ; |
369 | 371 | ||
370 | t1 = l_apic[CCRT]; |
372 | t1 = l_apic[CCRT]; |
371 | delay(1000); |
373 | delay(1000); |
372 | t2 = l_apic[CCRT]; |
374 | t2 = l_apic[CCRT]; |
373 | 375 | ||
374 | l_apic[ICRT] = t1-t2; |
376 | l_apic[ICRT] = t1-t2; |
- | 377 | ||
- | 378 | /* Program Logical Destination Register. */ |
|
- | 379 | ldr.value = l_apic[LDR]; |
|
- | 380 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
|
- | 381 | ldr.id = (1<<CPU->id); |
|
- | 382 | l_apic[LDR] = ldr.value; |
|
- | 383 | ||
- | 384 | /* Program Destination Format Register for Flat mode. */ |
|
- | 385 | dfr.value = l_apic[DFR]; |
|
- | 386 | dfr.model = MODEL_FLAT; |
|
- | 387 | l_apic[DFR] = dfr.value; |
|
375 | } |
388 | } |
376 | 389 | ||
377 | /** Local APIC End of Interrupt. */ |
390 | /** Local APIC End of Interrupt. */ |
378 | void l_apic_eoi(void) |
391 | void l_apic_eoi(void) |
379 | { |
392 | { |
380 | l_apic[EOI] = 0; |
393 | l_apic[EOI] = 0; |
381 | } |
394 | } |
382 | 395 | ||
383 | /** Dump content of Local APIC registers. */ |
396 | /** Dump content of Local APIC registers. */ |
384 | void l_apic_debug(void) |
397 | void l_apic_debug(void) |
385 | { |
398 | { |
386 | #ifdef LAPIC_VERBOSE |
399 | #ifdef LAPIC_VERBOSE |
387 | lvt_tm_t tm; |
400 | lvt_tm_t tm; |
388 | lvt_lint_t lint; |
401 | lvt_lint_t lint; |
389 | lvt_error_t error; |
402 | lvt_error_t error; |
390 | 403 | ||
391 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
404 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
392 | 405 | ||
393 | tm.value = l_apic[LVT_Tm]; |
406 | tm.value = l_apic[LVT_Tm]; |
394 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
407 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
395 | lint.value = l_apic[LVT_LINT0]; |
408 | lint.value = l_apic[LVT_LINT0]; |
396 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
409 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
397 | lint.value = l_apic[LVT_LINT1]; |
410 | lint.value = l_apic[LVT_LINT1]; |
398 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
411 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
399 | error.value = l_apic[LVT_Err]; |
412 | error.value = l_apic[LVT_Err]; |
400 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
413 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
401 | #endif |
414 | #endif |
402 | } |
415 | } |
403 | 416 | ||
404 | /** Local APIC Timer Interrupt. |
417 | /** Local APIC Timer Interrupt. |
405 | * |
418 | * |
406 | * @param n Interrupt vector number. |
419 | * @param n Interrupt vector number. |
407 | * @param stack Interrupted stack. |
420 | * @param stack Interrupted stack. |
408 | */ |
421 | */ |
409 | void l_apic_timer_interrupt(int n, void *stack) |
422 | void l_apic_timer_interrupt(int n, void *stack) |
410 | { |
423 | { |
411 | l_apic_eoi(); |
424 | l_apic_eoi(); |
412 | clock(); |
425 | clock(); |
413 | } |
426 | } |
414 | 427 | ||
415 | /** Get Local APIC ID. |
428 | /** Get Local APIC ID. |
416 | * |
429 | * |
417 | * @return Local APIC ID. |
430 | * @return Local APIC ID. |
418 | */ |
431 | */ |
419 | __u8 l_apic_id(void) |
432 | __u8 l_apic_id(void) |
420 | { |
433 | { |
421 | l_apic_id_t idreg; |
434 | l_apic_id_t idreg; |
422 | 435 | ||
423 | idreg.value = l_apic[L_APIC_ID]; |
436 | idreg.value = l_apic[L_APIC_ID]; |
424 | return idreg.apic_id; |
437 | return idreg.apic_id; |
425 | } |
438 | } |
426 | 439 | ||
427 | /** Read from IO APIC register. |
440 | /** Read from IO APIC register. |
428 | * |
441 | * |
429 | * @param address IO APIC register address. |
442 | * @param address IO APIC register address. |
430 | * |
443 | * |
431 | * @return Content of the addressed IO APIC register. |
444 | * @return Content of the addressed IO APIC register. |
432 | */ |
445 | */ |
433 | __u32 io_apic_read(__u8 address) |
446 | __u32 io_apic_read(__u8 address) |
434 | { |
447 | { |
435 | io_regsel_t regsel; |
448 | io_regsel_t regsel; |
436 | 449 | ||
437 | regsel.value = io_apic[IOREGSEL]; |
450 | regsel.value = io_apic[IOREGSEL]; |
438 | regsel.reg_addr = address; |
451 | regsel.reg_addr = address; |
439 | io_apic[IOREGSEL] = regsel.value; |
452 | io_apic[IOREGSEL] = regsel.value; |
440 | return io_apic[IOWIN]; |
453 | return io_apic[IOWIN]; |
441 | } |
454 | } |
442 | 455 | ||
443 | /** Write to IO APIC register. |
456 | /** Write to IO APIC register. |
444 | * |
457 | * |
445 | * @param address IO APIC register address. |
458 | * @param address IO APIC register address. |
446 | * @param Content to be written to the addressed IO APIC register. |
459 | * @param Content to be written to the addressed IO APIC register. |
447 | */ |
460 | */ |
448 | void io_apic_write(__u8 address, __u32 x) |
461 | void io_apic_write(__u8 address, __u32 x) |
449 | { |
462 | { |
450 | io_regsel_t regsel; |
463 | io_regsel_t regsel; |
451 | 464 | ||
452 | regsel.value = io_apic[IOREGSEL]; |
465 | regsel.value = io_apic[IOREGSEL]; |
453 | regsel.reg_addr = address; |
466 | regsel.reg_addr = address; |
454 | io_apic[IOREGSEL] = regsel.value; |
467 | io_apic[IOREGSEL] = regsel.value; |
455 | io_apic[IOWIN] = x; |
468 | io_apic[IOWIN] = x; |
456 | } |
469 | } |
457 | 470 | ||
458 | /** Change some attributes of one item in I/O Redirection Table. |
471 | /** Change some attributes of one item in I/O Redirection Table. |
459 | * |
472 | * |
460 | * @param pin IO APIC pin number. |
473 | * @param pin IO APIC pin number. |
461 | * @param dest Interrupt destination address. |
474 | * @param dest Interrupt destination address. |
462 | * @param v Interrupt vector to trigger. |
475 | * @param v Interrupt vector to trigger. |
463 | * @param flags Flags. |
476 | * @param flags Flags. |
464 | */ |
477 | */ |
465 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
478 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
466 | { |
479 | { |
467 | io_redirection_reg_t reg; |
480 | io_redirection_reg_t reg; |
468 | int dlvr = DELMOD_FIXED; |
481 | int dlvr = DELMOD_FIXED; |
469 | 482 | ||
470 | if (flags & LOPRI) |
483 | if (flags & LOPRI) |
471 | dlvr = DELMOD_LOWPRI; |
484 | dlvr = DELMOD_LOWPRI; |
472 | 485 | ||
473 | - | ||
474 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
486 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
475 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
487 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
476 | 488 | ||
477 | reg.dest = dest; |
489 | reg.dest = dest; |
478 | reg.destmod = DESTMOD_LOGIC; |
490 | reg.destmod = DESTMOD_LOGIC; |
479 | reg.trigger_mode = TRIGMOD_EDGE; |
491 | reg.trigger_mode = TRIGMOD_EDGE; |
480 | reg.intpol = POLARITY_HIGH; |
492 | reg.intpol = POLARITY_HIGH; |
481 | reg.delmod = dlvr; |
493 | reg.delmod = dlvr; |
482 | reg.intvec = v; |
494 | reg.intvec = v; |
483 | 495 | ||
484 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
496 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
485 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
497 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
486 | } |
498 | } |
487 | 499 | ||
488 | /** Mask IRQs in IO APIC. |
500 | /** Mask IRQs in IO APIC. |
489 | * |
501 | * |
490 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
502 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
491 | */ |
503 | */ |
492 | void io_apic_disable_irqs(__u16 irqmask) |
504 | void io_apic_disable_irqs(__u16 irqmask) |
493 | { |
505 | { |
494 | io_redirection_reg_t reg; |
506 | io_redirection_reg_t reg; |
495 | int i, pin; |
507 | int i, pin; |
496 | 508 | ||
497 | for (i=0;i<16;i++) { |
509 | for (i=0;i<16;i++) { |
498 | if (irqmask & (1<<i)) { |
510 | if (irqmask & (1<<i)) { |
499 | /* |
511 | /* |
500 | * Mask the signal input in IO APIC if there is a |
512 | * Mask the signal input in IO APIC if there is a |
501 | * mapping for the respective IRQ number. |
513 | * mapping for the respective IRQ number. |
502 | */ |
514 | */ |
503 | pin = smp_irq_to_pin(i); |
515 | pin = smp_irq_to_pin(i); |
504 | if (pin != -1) { |
516 | if (pin != -1) { |
505 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
517 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
506 | reg.masked = true; |
518 | reg.masked = true; |
507 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
519 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
508 | } |
520 | } |
509 | 521 | ||
510 | } |
522 | } |
511 | } |
523 | } |
512 | } |
524 | } |
513 | 525 | ||
514 | /** Unmask IRQs in IO APIC. |
526 | /** Unmask IRQs in IO APIC. |
515 | * |
527 | * |
516 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
528 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
517 | */ |
529 | */ |
518 | void io_apic_enable_irqs(__u16 irqmask) |
530 | void io_apic_enable_irqs(__u16 irqmask) |
519 | { |
531 | { |
520 | int i, pin; |
532 | int i, pin; |
521 | io_redirection_reg_t reg; |
533 | io_redirection_reg_t reg; |
522 | 534 | ||
523 | for (i=0;i<16;i++) { |
535 | for (i=0;i<16;i++) { |
524 | if (irqmask & (1<<i)) { |
536 | if (irqmask & (1<<i)) { |
525 | /* |
537 | /* |
526 | * Unmask the signal input in IO APIC if there is a |
538 | * Unmask the signal input in IO APIC if there is a |
527 | * mapping for the respective IRQ number. |
539 | * mapping for the respective IRQ number. |
528 | */ |
540 | */ |
529 | pin = smp_irq_to_pin(i); |
541 | pin = smp_irq_to_pin(i); |
530 | if (pin != -1) { |
542 | if (pin != -1) { |
531 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
543 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
532 | reg.masked = false; |
544 | reg.masked = false; |
533 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
545 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
534 | } |
546 | } |
535 | 547 | ||
536 | } |
548 | } |
537 | } |
549 | } |
538 | } |
550 | } |
539 | 551 | ||
540 | #endif /* CONFIG_SMP */ |
552 | #endif /* CONFIG_SMP */ |
541 | 553 |