WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/smp/apic.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <mm/page.h>
#include <time/delay.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef CONFIG_SMP
 
/*
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
 *  VMware Workstation 5.5 with 2 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
static int apic_poll_errors(void);
 
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {
    "Fixed",
    "Lowest Priority",
    "SMI",
    "Reserved",
    "NMI",
    "INIT",
    "STARTUP",
    "ExtInt"
};
 
static char *destmod_str[] = {
    "Physical",
    "Logical"
};
 
static char *trigmod_str[] = {
    "Edge",
    "Level"
};
 
static char *mask_str[] = {
    "Unmasked",
    "Masked"
};
 
static char *delivs_str[] = {
    "Idle",
    "Send Pending"
};
 
static char *tm_mode_str[] = {
    "One-shot",
    "Periodic"
};
 
static char *intpol_str[] = {
    "Polarity High",
    "Polarity Low"
};
#endif /* LAPIC_VERBOSE */
 
/** Initialize APIC on BSP. */
void apic_init(void)
{
    io_apic_id_t idreg;
    int i;
 
    trap_register(VECTOR_APIC_SPUR, apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    trap_register(VECTOR_CLK, l_apic_timer_interrupt);
    for (i = 0; i < IRQ_COUNT; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1) {
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
        }
    }
   
    /*
     * Ensure that io_apic has unique ID.
     */
    idreg.value = io_apic_read(IOAPICID);
    if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
        for (i = 0; i < APIC_ID_COUNT; i++) {
            if (!((1<<i) & apic_id_mask)) {
                idreg.apic_id = i;
                io_apic_write(IOAPICID, idreg.value);
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
 
    l_apic_debug();
}
 
/** APIC spurious interrupt handler.
 *
 * @param n Interrupt vector.
 * @param stack Interrupted stack.
 */
void apic_spurious(__u8 n, __native stack[])
{
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
 
/** Poll for APIC errors.
 *
 * Examine Error Status Register and report all errors found.
 *
 * @return 0 on error, 1 on success.
 */
int apic_poll_errors(void)
{
    esr_t esr;
   
    esr.value = l_apic[ESR];
   
    if (esr.send_checksum_error)
        printf("Send Checksum Error\n");
    if (esr.receive_checksum_error)
        printf("Receive Checksum Error\n");
    if (esr.send_accept_error)
        printf("Send Accept Error\n");
    if (esr.receive_accept_error)
        printf("Receive Accept Error\n");
    if (esr.send_illegal_vector)
        printf("Send Illegal Vector\n");
    if (esr.received_illegal_vector)
        printf("Received Illegal Vector\n");
    if (esr.illegal_register_address)
        printf("Illegal Register Address\n");
 
    return !esr.err_bitmap;
}
 
/** Send all CPUs excluding CPU IPI vector.
 *
 * @param vector Interrupt vector to be sent.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_broadcast_custom_ipi(__u8 vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;
    icr.destmod = DESTMOD_LOGIC;
    icr.level = LEVEL_ASSERT;
    icr.shorthand = SHORTHAND_ALL_EXCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = vector;
 
    l_apic[ICRlo] = icr.lo;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING)
        printf("IPI is pending.\n");
 
    return apic_poll_errors();
}
 
/** Universal Start-up Algorithm for bringing up the AP processors.
 *
 * @param apicid APIC ID of the processor to be brought up.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_send_init_ipi(__u8 apicid)
{
    icr_t icr;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    icr.lo = l_apic[ICRlo];
    icr.hi = l_apic[ICRhi];
   
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_ASSERT;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.shorthand = SHORTHAND_NONE;
    icr.vector = 0;
    icr.dest = apicid;
   
    l_apic[ICRhi] = icr.hi;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors()) return 0;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING)
        printf("IPI is pending.\n");
 
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_NONE;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = 0;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;
            l_apic[ICRlo] = icr.lo;
            delay(200);
        }
    }
   
    return apic_poll_errors();
}
 
/** Initialize Local APIC. */
void l_apic_init(void)
{
    lvt_error_t error;
    lvt_lint_t lint;
    svr_t svr;
    icr_t icr;
    tdcr_t tdcr;
    lvt_tm_t tm;
    __u32 t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;
 
    /* Initialize LVT LINT0 register. */
    lint.value = l_apic[LVT_LINT0];
    lint.masked = true;
    l_apic[LVT_LINT0] = lint.value;
 
    /* Initialize LVT LINT1 register. */
    lint.value = l_apic[LVT_LINT1];
    lint.masked = true;
    l_apic[LVT_LINT1] = lint.value;
   
    /* Spurious-Interrupt Vector Register initialization. */
    svr.value = l_apic[SVR];
    svr.vector = VECTOR_APIC_SPUR;
    svr.lapic_enabled = true;
    l_apic[SVR] = svr.value;
 
    l_apic[TPR] &= TPRClear;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    /* Interrupt Command Register initialization. */
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_ALL_INCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    l_apic[ICRlo] = icr.lo;
   
    /* Timer Divide Configuration Register initialization. */
    tdcr.value = l_apic[TDCR];
    tdcr.div_value = DIVIDE_1;
    l_apic[TDCR] = tdcr.value;
 
    /* Program local timer. */
    tm.value = l_apic[LVT_Tm];
    tm.vector = VECTOR_CLK;
    tm.mode = TIMER_PERIODIC;
    tm.masked = false;
    l_apic[LVT_Tm] = tm.value;
 
    /* Measure and configure the timer to generate timer interrupt each ms. */
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
}
 
/** Local APIC End of Interrupt. */
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
/** Dump content of Local APIC registers. */
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    lvt_tm_t tm;
    lvt_lint_t lint;
    lvt_error_t error; 
   
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    tm.value = l_apic[LVT_Tm];
    printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
    lint.value = l_apic[LVT_LINT0];
    printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
    lint.value = l_apic[LVT_LINT1];
    printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);   
    error.value = l_apic[LVT_Err];
    printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
#endif
}
 
/** Local APIC Timer Interrupt.
 *
 * @param n Interrupt vector number.
 * @param stack Interrupted stack.
 */
void l_apic_timer_interrupt(__u8 n, __native stack[])
{
    l_apic_eoi();
    clock();
}
 
/** Get Local APIC ID.
 *
 * @return Local APIC ID.
 */
__u8 l_apic_id(void)
{
    l_apic_id_t idreg;
   
    idreg.value = l_apic[L_APIC_ID];
    return idreg.apic_id;
}
 
/** Read from IO APIC register.
 *
 * @param address IO APIC register address.
 *
 * @return Content of the addressed IO APIC register.
 */
__u32 io_apic_read(__u8 address)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    return io_apic[IOWIN];
}
 
/** Write to IO APIC register.
 *
 * @param address IO APIC register address.
 * @param Content to be written to the addressed IO APIC register.
 */
void io_apic_write(__u8 address, __u32 x)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    io_apic[IOWIN] = x;
}
 
/** Change some attributes of one item in I/O Redirection Table.
 *
 * @param pin IO APIC pin number.
 * @param dest Interrupt destination address.
 * @param v Interrupt vector to trigger.
 * @param flags Flags.
 */
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = DELMOD_FIXED;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
   
    reg.lo = io_apic_read(IOREDTBL + pin*2);
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
   
    reg.dest =  dest;
    reg.destmod = DESTMOD_LOGIC;
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + pin*2, reg.lo);
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
}
 
/** Mask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
 */
void io_apic_disable_irqs(__u16 irqmask)
{
    io_redirection_reg_t reg;
    int i, pin;
   
    for (i=0;i<16;i++) {
        if (irqmask & (1<<i)) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
/** Unmask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
 */
void io_apic_enable_irqs(__u16 irqmask)
{
    int i, pin;
    io_redirection_reg_t reg;  
   
    for (i=0;i<16;i++) {
        if (irqmask & (1<<i)) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
#endif /* CONFIG_SMP */
 

Rev 516	Rev 523
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/types.h>	29	#include <arch/types.h>
30	#include <arch/smp/apic.h>	30	#include <arch/smp/apic.h>
31	#include <arch/smp/ap.h>	31	#include <arch/smp/ap.h>
32	#include <arch/smp/mps.h>	32	#include <arch/smp/mps.h>
33	#include <mm/page.h>	33	#include <mm/page.h>
34	#include <time/delay.h>	34	#include <time/delay.h>
35	#include <arch/interrupt.h>	35	#include <arch/interrupt.h>
36	#include <print.h>	36	#include <print.h>
37	#include <arch/asm.h>	37	#include <arch/asm.h>
38	#include <arch.h>	38	#include <arch.h>
39		39
40	#ifdef CONFIG_SMP	40	#ifdef CONFIG_SMP
41		41
42	/*	42	/*
43	* Advanced Programmable Interrupt Controller for SMP systems.	43	* Advanced Programmable Interrupt Controller for SMP systems.
44	* Tested on:	44	* Tested on:
45	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs	45	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
46	* Simics 2.0.28 - Simics 2.2.19 2-8 CPUs	46	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
47	* VMware Workstation 5.5 with 2 CPUs	47	* VMware Workstation 5.5 with 2 CPUs
48	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	48	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
49	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	49	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
50	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	50	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
51	*/	51	*/
52		52
53	/*	53	/*
54	* These variables either stay configured as initilalized, or are changed by	54	* These variables either stay configured as initilalized, or are changed by
55	* the MP configuration code.	55	* the MP configuration code.
56	*	56	*
57	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	57	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
58	* optimize the code too much and accesses to l_apic and io_apic, that must	58	* optimize the code too much and accesses to l_apic and io_apic, that must
59	* always be 32-bit, would use byte oriented instructions.	59	* always be 32-bit, would use byte oriented instructions.
60	*/	60	*/
61	volatile __u32 l_apic = (__u32 ) 0xfee00000;	61	volatile __u32 l_apic = (__u32 ) 0xfee00000;
62	volatile __u32 io_apic = (__u32 ) 0xfec00000;	62	volatile __u32 io_apic = (__u32 ) 0xfec00000;
63		63
64	__u32 apic_id_mask = 0;	64	__u32 apic_id_mask = 0;
65		65
66	static int apic_poll_errors(void);	66	static int apic_poll_errors(void);
67		67
68	#ifdef LAPIC_VERBOSE	68	#ifdef LAPIC_VERBOSE
69	static char *delmod_str[] = {	69	static char *delmod_str[] = {
70	"Fixed",	70	"Fixed",
71	"Lowest Priority",	71	"Lowest Priority",
72	"SMI",	72	"SMI",
73	"Reserved",	73	"Reserved",
74	"NMI",	74	"NMI",
75	"INIT",	75	"INIT",
76	"STARTUP",	76	"STARTUP",
77	"ExtInt"	77	"ExtInt"
78	};	78	};
79		79
80	static char *destmod_str[] = {	80	static char *destmod_str[] = {
81	"Physical",	81	"Physical",
82	"Logical"	82	"Logical"
83	};	83	};
84		84
85	static char *trigmod_str[] = {	85	static char *trigmod_str[] = {
86	"Edge",	86	"Edge",
87	"Level"	87	"Level"
88	};	88	};
89		89
90	static char *mask_str[] = {	90	static char *mask_str[] = {
91	"Unmasked",	91	"Unmasked",
92	"Masked"	92	"Masked"
93	};	93	};
94		94
95	static char *delivs_str[] = {	95	static char *delivs_str[] = {
96	"Idle",	96	"Idle",
97	"Send Pending"	97	"Send Pending"
98	};	98	};
99		99
100	static char *tm_mode_str[] = {	100	static char *tm_mode_str[] = {
101	"One-shot",	101	"One-shot",
102	"Periodic"	102	"Periodic"
103	};	103	};
104		104
105	static char *intpol_str[] = {	105	static char *intpol_str[] = {
106	"Polarity High",	106	"Polarity High",
107	"Polarity Low"	107	"Polarity Low"
108	};	108	};
109	#endif /* LAPIC_VERBOSE */	109	#endif /* LAPIC_VERBOSE */
110		110
111	/** Initialize APIC on BSP. */	111	/** Initialize APIC on BSP. */
112	void apic_init(void)	112	void apic_init(void)
113	{	113	{
114	io_apic_id_t idreg;	114	io_apic_id_t idreg;
115	int i;	115	int i;
116		116
117	trap_register(VECTOR_APIC_SPUR, apic_spurious);	117	trap_register(VECTOR_APIC_SPUR, apic_spurious);
118		118
119	enable_irqs_function = io_apic_enable_irqs;	119	enable_irqs_function = io_apic_enable_irqs;
120	disable_irqs_function = io_apic_disable_irqs;	120	disable_irqs_function = io_apic_disable_irqs;
121	eoi_function = l_apic_eoi;	121	eoi_function = l_apic_eoi;
122		122
123	/*	123	/*
124	* Configure interrupt routing.	124	* Configure interrupt routing.
125	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	125	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
126	* Other interrupts will be forwarded to the lowest priority CPU.	126	* Other interrupts will be forwarded to the lowest priority CPU.
127	*/	127	*/
128	io_apic_disable_irqs(0xffff);	128	io_apic_disable_irqs(0xffff);
129	trap_register(VECTOR_CLK, l_apic_timer_interrupt);	129	trap_register(VECTOR_CLK, l_apic_timer_interrupt);
130	for (i = 0; i < IRQ_COUNT; i++) {	130	for (i = 0; i < IRQ_COUNT; i++) {
131	int pin;	131	int pin;
132		132
133	if ((pin = smp_irq_to_pin(i)) != -1) {	133	if ((pin = smp_irq_to_pin(i)) != -1) {
134	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);	134	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
135	}	135	}
136	}	136	}
137		137
138	/*	138	/*
139	* Ensure that io_apic has unique ID.	139	* Ensure that io_apic has unique ID.
140	*/	140	*/
141	idreg.value = io_apic_read(IOAPICID);	141	idreg.value = io_apic_read(IOAPICID);
142	if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */	142	if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
143	for (i = 0; i < APIC_ID_COUNT; i++) {	143	for (i = 0; i < APIC_ID_COUNT; i++) {
144	if (!((1<<i) & apic_id_mask)) {	144	if (!((1<<i) & apic_id_mask)) {
145	idreg.apic_id = i;	145	idreg.apic_id = i;
146	io_apic_write(IOAPICID, idreg.value);	146	io_apic_write(IOAPICID, idreg.value);
147	break;	147	break;
148	}	148	}
149	}	149	}
150	}	150	}
151		151
152	/*	152	/*
153	* Configure the BSP's lapic.	153	* Configure the BSP's lapic.
154	*/	154	*/
155	l_apic_init();	155	l_apic_init();
156		156
157	l_apic_debug();	157	l_apic_debug();
158	}	158	}
159		159
160	/** APIC spurious interrupt handler.	160	/** APIC spurious interrupt handler.
161	*	161	*
162	* @param n Interrupt vector.	162	* @param n Interrupt vector.
163	* @param stack Interrupted stack.	163	* @param stack Interrupted stack.
164	*/	164	*/
165	void apic_spurious(__u8 n, __native stack[])	165	void apic_spurious(__u8 n, __native stack[])
166	{	166	{
167	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	167	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
168	}	168	}
169		169
170	/** Poll for APIC errors.	170	/** Poll for APIC errors.
171	*	171	*
172	* Examine Error Status Register and report all errors found.	172	* Examine Error Status Register and report all errors found.
173	*	173	*
174	* @return 0 on error, 1 on success.	174	* @return 0 on error, 1 on success.
175	*/	175	*/
176	int apic_poll_errors(void)	176	int apic_poll_errors(void)
177	{	177	{
178	esr_t esr;	178	esr_t esr;
179		179
180	esr.value = l_apic[ESR];	180	esr.value = l_apic[ESR];
181		181
182	if (esr.send_checksum_error)	182	if (esr.send_checksum_error)
183	printf("Send Checksum Error\n");	183	printf("Send Checksum Error\n");
184	if (esr.receive_checksum_error)	184	if (esr.receive_checksum_error)
185	printf("Receive Checksum Error\n");	185	printf("Receive Checksum Error\n");
186	if (esr.send_accept_error)	186	if (esr.send_accept_error)
187	printf("Send Accept Error\n");	187	printf("Send Accept Error\n");
188	if (esr.receive_accept_error)	188	if (esr.receive_accept_error)
189	printf("Receive Accept Error\n");	189	printf("Receive Accept Error\n");
190	if (esr.send_illegal_vector)	190	if (esr.send_illegal_vector)
191	printf("Send Illegal Vector\n");	191	printf("Send Illegal Vector\n");
192	if (esr.received_illegal_vector)	192	if (esr.received_illegal_vector)
193	printf("Received Illegal Vector\n");	193	printf("Received Illegal Vector\n");
194	if (esr.illegal_register_address)	194	if (esr.illegal_register_address)
195	printf("Illegal Register Address\n");	195	printf("Illegal Register Address\n");
196		196
197	return !esr.err_bitmap;	197	return !esr.err_bitmap;
198	}	198	}
199		199
200	/** Send all CPUs excluding CPU IPI vector.	200	/** Send all CPUs excluding CPU IPI vector.
201	*	201	*
202	* @param vector Interrupt vector to be sent.	202	* @param vector Interrupt vector to be sent.
203	*	203	*
204	* @return 0 on failure, 1 on success.	204	* @return 0 on failure, 1 on success.
205	*/	205	*/
206	int l_apic_broadcast_custom_ipi(__u8 vector)	206	int l_apic_broadcast_custom_ipi(__u8 vector)
207	{	207	{
208	icr_t icr;	208	icr_t icr;
209		209
210	icr.lo = l_apic[ICRlo];	210	icr.lo = l_apic[ICRlo];
211	icr.delmod = DELMOD_FIXED;	211	icr.delmod = DELMOD_FIXED;
212	icr.destmod = DESTMOD_LOGIC;	212	icr.destmod = DESTMOD_LOGIC;
213	icr.level = LEVEL_ASSERT;	213	icr.level = LEVEL_ASSERT;
214	icr.shorthand = SHORTHAND_ALL_EXCL;	214	icr.shorthand = SHORTHAND_ALL_EXCL;
215	icr.trigger_mode = TRIGMOD_LEVEL;	215	icr.trigger_mode = TRIGMOD_LEVEL;
216	icr.vector = vector;	216	icr.vector = vector;
217		217
218	l_apic[ICRlo] = icr.lo;	218	l_apic[ICRlo] = icr.lo;
219		219
220	icr.lo = l_apic[ICRlo];	220	icr.lo = l_apic[ICRlo];
221	if (icr.delivs == DELIVS_PENDING)	221	if (icr.delivs == DELIVS_PENDING)
222	printf("IPI is pending.\n");	222	printf("IPI is pending.\n");
223		223
224	return apic_poll_errors();	224	return apic_poll_errors();
225	}	225	}
226		226
227	/** Universal Start-up Algorithm for bringing up the AP processors.	227	/** Universal Start-up Algorithm for bringing up the AP processors.
228	*	228	*
229	* @param apicid APIC ID of the processor to be brought up.	229	* @param apicid APIC ID of the processor to be brought up.
230	*	230	*
231	* @return 0 on failure, 1 on success.	231	* @return 0 on failure, 1 on success.
232	*/	232	*/
233	int l_apic_send_init_ipi(__u8 apicid)	233	int l_apic_send_init_ipi(__u8 apicid)
234	{	234	{
235	icr_t icr;	235	icr_t icr;
236	int i;	236	int i;
237		237
238	/*	238	/*
239	* Read the ICR register in and zero all non-reserved fields.	239	* Read the ICR register in and zero all non-reserved fields.
240	*/	240	*/
241	icr.lo = l_apic[ICRlo];	241	icr.lo = l_apic[ICRlo];
242	icr.hi = l_apic[ICRhi];	242	icr.hi = l_apic[ICRhi];
243		243
244	icr.delmod = DELMOD_INIT;	244	icr.delmod = DELMOD_INIT;
245	icr.destmod = DESTMOD_PHYS;	245	icr.destmod = DESTMOD_PHYS;
246	icr.level = LEVEL_ASSERT;	246	icr.level = LEVEL_ASSERT;
247	icr.trigger_mode = TRIGMOD_LEVEL;	247	icr.trigger_mode = TRIGMOD_LEVEL;
248	icr.shorthand = SHORTHAND_NONE;	248	icr.shorthand = SHORTHAND_NONE;
249	icr.vector = 0;	249	icr.vector = 0;
250	icr.dest = apicid;	250	icr.dest = apicid;
251		251
252	l_apic[ICRhi] = icr.hi;	252	l_apic[ICRhi] = icr.hi;
253	l_apic[ICRlo] = icr.lo;	253	l_apic[ICRlo] = icr.lo;
254		254
255	/*	255	/*
256	* According to MP Specification, 20us should be enough to	256	* According to MP Specification, 20us should be enough to
257	* deliver the IPI.	257	* deliver the IPI.
258	*/	258	*/
259	delay(20);	259	delay(20);
260		260
261	if (!apic_poll_errors()) return 0;	261	if (!apic_poll_errors()) return 0;
262		262
263	icr.lo = l_apic[ICRlo];	263	icr.lo = l_apic[ICRlo];
264	if (icr.delivs == DELIVS_PENDING)	264	if (icr.delivs == DELIVS_PENDING)
265	printf("IPI is pending.\n");	265	printf("IPI is pending.\n");
266		266
267	icr.delmod = DELMOD_INIT;	267	icr.delmod = DELMOD_INIT;
268	icr.destmod = DESTMOD_PHYS;	268	icr.destmod = DESTMOD_PHYS;
269	icr.level = LEVEL_DEASSERT;	269	icr.level = LEVEL_DEASSERT;
270	icr.shorthand = SHORTHAND_NONE;	270	icr.shorthand = SHORTHAND_NONE;
271	icr.trigger_mode = TRIGMOD_LEVEL;	271	icr.trigger_mode = TRIGMOD_LEVEL;
272	icr.vector = 0;	272	icr.vector = 0;
273	l_apic[ICRlo] = icr.lo;	273	l_apic[ICRlo] = icr.lo;
274		274
275	/*	275	/*
276	* Wait 10ms as MP Specification specifies.	276	* Wait 10ms as MP Specification specifies.
277	*/	277	*/
278	delay(10000);	278	delay(10000);
279		279
280	if (!is_82489DX_apic(l_apic[LAVR])) {	280	if (!is_82489DX_apic(l_apic[LAVR])) {
281	/*	281	/*
282	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	282	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
283	*/	283	*/
284	for (i = 0; i<2; i++) {	284	for (i = 0; i<2; i++) {
285	icr.lo = l_apic[ICRlo];	285	icr.lo = l_apic[ICRlo];
286	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */	286	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
287	icr.delmod = DELMOD_STARTUP;	287	icr.delmod = DELMOD_STARTUP;
288	icr.destmod = DESTMOD_PHYS;	288	icr.destmod = DESTMOD_PHYS;
289	icr.level = LEVEL_ASSERT;	289	icr.level = LEVEL_ASSERT;
290	icr.shorthand = SHORTHAND_NONE;	290	icr.shorthand = SHORTHAND_NONE;
291	icr.trigger_mode = TRIGMOD_LEVEL;	291	icr.trigger_mode = TRIGMOD_LEVEL;
292	l_apic[ICRlo] = icr.lo;	292	l_apic[ICRlo] = icr.lo;
293	delay(200);	293	delay(200);
294	}	294	}
295	}	295	}
296		296
297	return apic_poll_errors();	297	return apic_poll_errors();
298	}	298	}
299		299
300	/** Initialize Local APIC. */	300	/** Initialize Local APIC. */
301	void l_apic_init(void)	301	void l_apic_init(void)
302	{	302	{
303	lvt_error_t error;	303	lvt_error_t error;
304	lvt_lint_t lint;	304	lvt_lint_t lint;
305	svr_t svr;	305	svr_t svr;
306	icr_t icr;	306	icr_t icr;
307	tdcr_t tdcr;	307	tdcr_t tdcr;
308	lvt_tm_t tm;	308	lvt_tm_t tm;
309	__u32 t1, t2;	309	__u32 t1, t2;
310		310
311	/* Initialize LVT Error register. */	311	/* Initialize LVT Error register. */
312	error.value = l_apic[LVT_Err];	312	error.value = l_apic[LVT_Err];
313	error.masked = true;	313	error.masked = true;
314	l_apic[LVT_Err] = error.value;	314	l_apic[LVT_Err] = error.value;
315		315
316	/* Initialize LVT LINT0 register. */	316	/* Initialize LVT LINT0 register. */
317	lint.value = l_apic[LVT_LINT0];	317	lint.value = l_apic[LVT_LINT0];
318	lint.masked = true;	318	lint.masked = true;
319	l_apic[LVT_LINT0] = lint.value;	319	l_apic[LVT_LINT0] = lint.value;
320		320
321	/* Initialize LVT LINT1 register. */	321	/* Initialize LVT LINT1 register. */
322	lint.value = l_apic[LVT_LINT1];	322	lint.value = l_apic[LVT_LINT1];
323	lint.masked = true;	323	lint.masked = true;
324	l_apic[LVT_LINT1] = lint.value;	324	l_apic[LVT_LINT1] = lint.value;
325		325
326	/* Spurious-Interrupt Vector Register initialization. */	326	/* Spurious-Interrupt Vector Register initialization. */
327	svr.value = l_apic[SVR];	327	svr.value = l_apic[SVR];
328	svr.vector = VECTOR_APIC_SPUR;	328	svr.vector = VECTOR_APIC_SPUR;
329	svr.lapic_enabled = true;	329	svr.lapic_enabled = true;
330	l_apic[SVR] = svr.value;	330	l_apic[SVR] = svr.value;
331		331
332	l_apic[TPR] &= TPRClear;	332	l_apic[TPR] &= TPRClear;
333		333
334	if (CPU->arch.family >= 6)	334	if (CPU->arch.family >= 6)
335	enable_l_apic_in_msr();	335	enable_l_apic_in_msr();
336		336
337	/* Interrupt Command Register initialization. */	337	/* Interrupt Command Register initialization. */
338	icr.lo = l_apic[ICRlo];	338	icr.lo = l_apic[ICRlo];
339	icr.delmod = DELMOD_INIT;	339	icr.delmod = DELMOD_INIT;
340	icr.destmod = DESTMOD_PHYS;	340	icr.destmod = DESTMOD_PHYS;
341	icr.level = LEVEL_DEASSERT;	341	icr.level = LEVEL_DEASSERT;
342	icr.shorthand = SHORTHAND_ALL_INCL;	342	icr.shorthand = SHORTHAND_ALL_INCL;
343	icr.trigger_mode = TRIGMOD_LEVEL;	343	icr.trigger_mode = TRIGMOD_LEVEL;
344	l_apic[ICRlo] = icr.lo;	344	l_apic[ICRlo] = icr.lo;
345		345
346	/* Timer Divide Configuration Register initialization. */	346	/* Timer Divide Configuration Register initialization. */
347	tdcr.value = l_apic[TDCR];	347	tdcr.value = l_apic[TDCR];
348	tdcr.div_value = DIVIDE_1;	348	tdcr.div_value = DIVIDE_1;
349	l_apic[TDCR] = tdcr.value;	349	l_apic[TDCR] = tdcr.value;
350		350
351	/* Program local timer. */	351	/* Program local timer. */
352	tm.value = l_apic[LVT_Tm];	352	tm.value = l_apic[LVT_Tm];
353	tm.vector = VECTOR_CLK;	353	tm.vector = VECTOR_CLK;
354	tm.mode = TIMER_PERIODIC;	354	tm.mode = TIMER_PERIODIC;
355	tm.masked = false;	355	tm.masked = false;
356	l_apic[LVT_Tm] = tm.value;	356	l_apic[LVT_Tm] = tm.value;
357		357
358	/* Measure and configure the timer to generate timer interrupt each ms. */	358	/* Measure and configure the timer to generate timer interrupt each ms. */
359	t1 = l_apic[CCRT];	359	t1 = l_apic[CCRT];
360	l_apic[ICRT] = 0xffffffff;	360	l_apic[ICRT] = 0xffffffff;
361		361
362	while (l_apic[CCRT] == t1)	362	while (l_apic[CCRT] == t1)
363	;	363	;
364		364
365	t1 = l_apic[CCRT];	365	t1 = l_apic[CCRT];
366	delay(1000);	366	delay(1000);
367	t2 = l_apic[CCRT];	367	t2 = l_apic[CCRT];
368		368
369	l_apic[ICRT] = t1-t2;	369	l_apic[ICRT] = t1-t2;
370	}	370	}
371		371
372	/** Local APIC End of Interrupt. */	372	/** Local APIC End of Interrupt. */
373	void l_apic_eoi(void)	373	void l_apic_eoi(void)
374	{	374	{
375	l_apic[EOI] = 0;	375	l_apic[EOI] = 0;
376	}	376	}
377		377
378	/** Dump content of Local APIC registers. */	378	/** Dump content of Local APIC registers. */
379	void l_apic_debug(void)	379	void l_apic_debug(void)
380	{	380	{
381	#ifdef LAPIC_VERBOSE	381	#ifdef LAPIC_VERBOSE
382	lvt_tm_t tm;	382	lvt_tm_t tm;
383	lvt_lint_t lint;	383	lvt_lint_t lint;
384	lvt_error_t error;	384	lvt_error_t error;
385		385
386	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	386	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
387		387
388	tm.value = l_apic[LVT_Tm];	388	tm.value = l_apic[LVT_Tm];
389	printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);	389	printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
390	lint.value = l_apic[LVT_LINT0];	390	lint.value = l_apic[LVT_LINT0];
391	printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	391	printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
392	lint.value = l_apic[LVT_LINT1];	392	lint.value = l_apic[LVT_LINT1];
393	printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	393	printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
394	error.value = l_apic[LVT_Err];	394	error.value = l_apic[LVT_Err];
395	printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);	395	printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
396	#endif	396	#endif
397	}	397	}
398		398
399	/** Local APIC Timer Interrupt.	399	/** Local APIC Timer Interrupt.
400	*	400	*
401	* @param n Interrupt vector number.	401	* @param n Interrupt vector number.
402	* @param stack Interrupted stack.	402	* @param stack Interrupted stack.
403	*/	403	*/
404	void l_apic_timer_interrupt(__u8 n, __native stack[])	404	void l_apic_timer_interrupt(__u8 n, __native stack[])
405	{	405	{
406	l_apic_eoi();	406	l_apic_eoi();
407	clock();	407	clock();
408	}	408	}
409		409
410	/** Get Local APIC ID.	410	/** Get Local APIC ID.
411	*	411	*
412	* @return Local APIC ID.	412	* @return Local APIC ID.
413	*/	413	*/
414	__u8 l_apic_id(void)	414	__u8 l_apic_id(void)
415	{	415	{
416	l_apic_id_t idreg;	416	l_apic_id_t idreg;
417		417
418	idreg.value = l_apic[L_APIC_ID];	418	idreg.value = l_apic[L_APIC_ID];
419	return idreg.apic_id;	419	return idreg.apic_id;
420	}	420	}
421		421
422	/** Read from IO APIC register.	422	/** Read from IO APIC register.
423	*	423	*
424	* @param address IO APIC register address.	424	* @param address IO APIC register address.
425	*	425	*
426	* @return Content of the addressed IO APIC register.	426	* @return Content of the addressed IO APIC register.
427	*/	427	*/
428	__u32 io_apic_read(__u8 address)	428	__u32 io_apic_read(__u8 address)
429	{	429	{
430	io_regsel_t regsel;	430	io_regsel_t regsel;
431		431
432	regsel.value = io_apic[IOREGSEL];	432	regsel.value = io_apic[IOREGSEL];
433	regsel.reg_addr = address;	433	regsel.reg_addr = address;
434	io_apic[IOREGSEL] = regsel.value;	434	io_apic[IOREGSEL] = regsel.value;
435	return io_apic[IOWIN];	435	return io_apic[IOWIN];
436	}	436	}
437		437
438	/** Write to IO APIC register.	438	/** Write to IO APIC register.
439	*	439	*
440	* @param address IO APIC register address.	440	* @param address IO APIC register address.
441	* @param Content to be written to the addressed IO APIC register.	441	* @param Content to be written to the addressed IO APIC register.
442	*/	442	*/
443	void io_apic_write(__u8 address, __u32 x)	443	void io_apic_write(__u8 address, __u32 x)
444	{	444	{
445	io_regsel_t regsel;	445	io_regsel_t regsel;
446		446
447	regsel.value = io_apic[IOREGSEL];	447	regsel.value = io_apic[IOREGSEL];
448	regsel.reg_addr = address;	448	regsel.reg_addr = address;
449	io_apic[IOREGSEL] = regsel.value;	449	io_apic[IOREGSEL] = regsel.value;
450	io_apic[IOWIN] = x;	450	io_apic[IOWIN] = x;
451	}	451	}
452		452
453	/** Change some attributes of one item in I/O Redirection Table.	453	/** Change some attributes of one item in I/O Redirection Table.
454	*	454	*
455	* @param pin IO APIC pin number.	455	* @param pin IO APIC pin number.
456	* @param dest Interrupt destination address.	456	* @param dest Interrupt destination address.
457	* @param v Interrupt vector to trigger.	457	* @param v Interrupt vector to trigger.
458	* @param flags Flags.	458	* @param flags Flags.
459	*/	459	*/
460	void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)	460	void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
461	{	461	{
462	io_redirection_reg_t reg;	462	io_redirection_reg_t reg;
463	int dlvr = DELMOD_FIXED;	463	int dlvr = DELMOD_FIXED;
464		464
465	if (flags & LOPRI)	465	if (flags & LOPRI)
466	dlvr = DELMOD_LOWPRI;	466	dlvr = DELMOD_LOWPRI;
467		467
468		468
469	reg.lo = io_apic_read(IOREDTBL + pin*2);	469	reg.lo = io_apic_read(IOREDTBL + pin*2);
470	reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);	470	reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
471		471
472	reg.dest = dest;	472	reg.dest = dest;
473	reg.destmod = DESTMOD_LOGIC;	473	reg.destmod = DESTMOD_LOGIC;
474	reg.trigger_mode = TRIGMOD_EDGE;	474	reg.trigger_mode = TRIGMOD_EDGE;
475	reg.intpol = POLARITY_HIGH;	475	reg.intpol = POLARITY_HIGH;
476	reg.delmod = dlvr;	476	reg.delmod = dlvr;
477	reg.intvec = v;	477	reg.intvec = v;
478		478
479	io_apic_write(IOREDTBL + pin*2, reg.lo);	479	io_apic_write(IOREDTBL + pin*2, reg.lo);
480	io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);	480	io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
481	}	481	}
482		482
483	/** Mask IRQs in IO APIC.	483	/** Mask IRQs in IO APIC.
484	*	484	*
485	* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).	485	* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
486	*/	486	*/
487	void io_apic_disable_irqs(__u16 irqmask)	487	void io_apic_disable_irqs(__u16 irqmask)
488	{	488	{
489	io_redirection_reg_t reg;	489	io_redirection_reg_t reg;
490	int i, pin;	490	int i, pin;
491		491
492	for (i=0;i<16;i++) {	492	for (i=0;i<16;i++) {
493	if (irqmask & (1<<i)) {	493	if (irqmask & (1<<i)) {
494	/*	494	/*
495	* Mask the signal input in IO APIC if there is a	495	* Mask the signal input in IO APIC if there is a
496	* mapping for the respective IRQ number.	496	* mapping for the respective IRQ number.
497	*/	497	*/
498	pin = smp_irq_to_pin(i);	498	pin = smp_irq_to_pin(i);
499	if (pin != -1) {	499	if (pin != -1) {
500	reg.lo = io_apic_read(IOREDTBL + pin*2);	500	reg.lo = io_apic_read(IOREDTBL + pin*2);

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(root)/kernel/trunk/arch/ia32/src/smp/apic.c @ 1667 – Rev 516 → 523