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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/pm.h> |
29 | #include <arch/pm.h> |
30 | #include <config.h> |
30 | #include <config.h> |
31 | #include <arch/types.h> |
31 | #include <arch/types.h> |
32 | #include <typedefs.h> |
32 | #include <typedefs.h> |
33 | #include <arch/interrupt.h> |
33 | #include <arch/interrupt.h> |
34 | #include <arch/asm.h> |
34 | #include <arch/asm.h> |
35 | #include <arch/context.h> |
35 | #include <arch/context.h> |
36 | #include <panic.h> |
36 | #include <panic.h> |
37 | #include <arch/mm/page.h> |
37 | #include <arch/mm/page.h> |
- | 38 | #include <mm/heap.h> |
|
- | 39 | #include <memstr.h> |
|
38 | 40 | ||
39 | /* |
41 | /* |
40 | * Early ia32 configuration functions and data structures. |
42 | * Early ia32 configuration functions and data structures. |
41 | */ |
43 | */ |
42 | 44 | ||
43 | /* |
45 | /* |
44 | * We have no use for segmentation so we set up flat mode. In this |
46 | * We have no use for segmentation so we set up flat mode. In this |
45 | * mode, we use, for each privilege level, two segments spanning the |
47 | * mode, we use, for each privilege level, two segments spanning the |
46 | * whole memory. One is for code and one is for data. |
48 | * whole memory. One is for code and one is for data. |
47 | */ |
49 | */ |
48 | struct descriptor gdt[GDT_ITEMS] = { |
50 | struct descriptor gdt[GDT_ITEMS] = { |
49 | /* NULL descriptor */ |
51 | /* NULL descriptor */ |
50 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
52 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
51 | /* KTEXT descriptor */ |
53 | /* KTEXT descriptor */ |
52 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
54 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
53 | /* KDATA descriptor */ |
55 | /* KDATA descriptor */ |
54 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
56 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
55 | /* UTEXT descriptor */ |
57 | /* UTEXT descriptor */ |
56 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
58 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
57 | /* UDATA descriptor */ |
59 | /* UDATA descriptor */ |
58 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
60 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
59 | /* TSS descriptor - set up will be completed later */ |
61 | /* TSS descriptor - set up will be completed later */ |
60 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } |
62 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } |
61 | }; |
63 | }; |
62 | 64 | ||
63 | static struct idescriptor idt[IDT_ITEMS]; |
65 | static struct idescriptor idt[IDT_ITEMS]; |
64 | 66 | ||
65 | static struct tss tss; |
67 | static struct tss tss; |
66 | 68 | ||
67 | struct tss *tss_p = NULL; |
69 | struct tss *tss_p = NULL; |
68 | 70 | ||
69 | /* gdtr is changed by kmp before next CPU is initialized */ |
71 | /* gdtr is changed by kmp before next CPU is initialized */ |
70 | struct ptr_16_32 gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) }; |
72 | struct ptr_16_32 gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) }; |
71 | struct ptr_16_32 idtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(idt), .base = KA2PA((__address) idt) }; |
73 | struct ptr_16_32 idtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(idt), .base = KA2PA((__address) idt) }; |
72 | 74 | ||
73 | void gdt_setbase(struct descriptor *d, __address base) |
75 | void gdt_setbase(struct descriptor *d, __address base) |
74 | { |
76 | { |
75 | d->base_0_15 = base & 0xffff; |
77 | d->base_0_15 = base & 0xffff; |
76 | d->base_16_23 = ((base) >> 16) & 0xff; |
78 | d->base_16_23 = ((base) >> 16) & 0xff; |
77 | d->base_24_31 = ((base) >> 24) & 0xff; |
79 | d->base_24_31 = ((base) >> 24) & 0xff; |
78 | } |
80 | } |
79 | 81 | ||
80 | void gdt_setlimit(struct descriptor *d, __u32 limit) |
82 | void gdt_setlimit(struct descriptor *d, __u32 limit) |
81 | { |
83 | { |
82 | d->limit_0_15 = limit & 0xffff; |
84 | d->limit_0_15 = limit & 0xffff; |
83 | d->limit_16_19 = (limit >> 16) & 0xf; |
85 | d->limit_16_19 = (limit >> 16) & 0xf; |
84 | } |
86 | } |
85 | 87 | ||
86 | void idt_setoffset(struct idescriptor *d, __address offset) |
88 | void idt_setoffset(struct idescriptor *d, __address offset) |
87 | { |
89 | { |
88 | /* |
90 | /* |
89 | * Offset is a linear address. |
91 | * Offset is a linear address. |
90 | */ |
92 | */ |
91 | d->offset_0_15 = offset & 0xffff; |
93 | d->offset_0_15 = offset & 0xffff; |
92 | d->offset_16_31 = offset >> 16; |
94 | d->offset_16_31 = offset >> 16; |
93 | } |
95 | } |
94 | 96 | ||
95 | void tss_initialize(struct tss *t) |
97 | void tss_initialize(struct tss *t) |
96 | { |
98 | { |
97 | memsetb((__address) t, sizeof(struct tss), 0); |
99 | memsetb((__address) t, sizeof(struct tss), 0); |
98 | } |
100 | } |
99 | 101 | ||
100 | /* |
102 | /* |
101 | * This function takes care of proper setup of IDT and IDTR. |
103 | * This function takes care of proper setup of IDT and IDTR. |
102 | */ |
104 | */ |
103 | void idt_init(void) |
105 | void idt_init(void) |
104 | { |
106 | { |
105 | struct idescriptor *d; |
107 | struct idescriptor *d; |
106 | int i; |
108 | int i; |
107 | 109 | ||
108 | for (i = 0; i < IDT_ITEMS; i++) { |
110 | for (i = 0; i < IDT_ITEMS; i++) { |
109 | d = &idt[i]; |
111 | d = &idt[i]; |
110 | 112 | ||
111 | d->unused = 0; |
113 | d->unused = 0; |
112 | d->selector = selector(KTEXT_DES); |
114 | d->selector = selector(KTEXT_DES); |
113 | 115 | ||
114 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
116 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
115 | 117 | ||
116 | if (i == VECTOR_SYSCALL) { |
118 | if (i == VECTOR_SYSCALL) { |
117 | /* |
119 | /* |
118 | * The syscall interrupt gate must be calleable from userland. |
120 | * The syscall interrupt gate must be calleable from userland. |
119 | */ |
121 | */ |
120 | d->access |= DPL_USER; |
122 | d->access |= DPL_USER; |
121 | } |
123 | } |
122 | 124 | ||
123 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
125 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
124 | trap_register(i, null_interrupt); |
126 | trap_register(i, null_interrupt); |
125 | } |
127 | } |
126 | trap_register(13, gp_fault); |
128 | trap_register(13, gp_fault); |
127 | trap_register( 7, nm_fault); |
129 | trap_register( 7, nm_fault); |
128 | trap_register(12, ss_fault); |
130 | trap_register(12, ss_fault); |
129 | } |
131 | } |
130 | 132 | ||
131 | 133 | ||
132 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
134 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
133 | static void clean_IOPL_NT_flags(void) |
135 | static void clean_IOPL_NT_flags(void) |
134 | { |
136 | { |
135 | asm |
137 | asm |
136 | ( |
138 | ( |
137 | "pushfl;" |
139 | "pushfl;" |
138 | "pop %%eax;" |
140 | "pop %%eax;" |
139 | "and $0xffff8fff,%%eax;" |
141 | "and $0xffff8fff,%%eax;" |
140 | "push %%eax;" |
142 | "push %%eax;" |
141 | "popfl;" |
143 | "popfl;" |
142 | : |
144 | : |
143 | : |
145 | : |
144 | :"%eax" |
146 | :"%eax" |
145 | ); |
147 | ); |
146 | } |
148 | } |
147 | 149 | ||
148 | /* Clean AM(18) flag in CR0 register */ |
150 | /* Clean AM(18) flag in CR0 register */ |
149 | static void clean_AM_flag(void) |
151 | static void clean_AM_flag(void) |
150 | { |
152 | { |
151 | asm |
153 | asm |
152 | ( |
154 | ( |
153 | "mov %%cr0,%%eax;" |
155 | "mov %%cr0,%%eax;" |
154 | "and $0xFFFBFFFF,%%eax;" |
156 | "and $0xFFFBFFFF,%%eax;" |
155 | "mov %%eax,%%cr0;" |
157 | "mov %%eax,%%cr0;" |
156 | : |
158 | : |
157 | : |
159 | : |
158 | :"%eax" |
160 | :"%eax" |
159 | ); |
161 | ); |
160 | } |
162 | } |
161 | 163 | ||
162 | void pm_init(void) |
164 | void pm_init(void) |
163 | { |
165 | { |
164 | struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base); |
166 | struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base); |
165 | 167 | ||
166 | /* |
168 | /* |
167 | * Each CPU has its private GDT and TSS. |
169 | * Each CPU has its private GDT and TSS. |
168 | * All CPUs share one IDT. |
170 | * All CPUs share one IDT. |
169 | */ |
171 | */ |
170 | 172 | ||
171 | if (config.cpu_active == 1) { |
173 | if (config.cpu_active == 1) { |
172 | idt_init(); |
174 | idt_init(); |
173 | /* |
175 | /* |
174 | * NOTE: bootstrap CPU has statically allocated TSS, because |
176 | * NOTE: bootstrap CPU has statically allocated TSS, because |
175 | * the heap hasn't been initialized so far. |
177 | * the heap hasn't been initialized so far. |
176 | */ |
178 | */ |
177 | tss_p = &tss; |
179 | tss_p = &tss; |
178 | } |
180 | } |
179 | else { |
181 | else { |
180 | tss_p = (struct tss *) malloc(sizeof(struct tss)); |
182 | tss_p = (struct tss *) malloc(sizeof(struct tss)); |
181 | if (!tss_p) |
183 | if (!tss_p) |
182 | panic("could not allocate TSS\n"); |
184 | panic("could not allocate TSS\n"); |
183 | } |
185 | } |
184 | 186 | ||
185 | tss_initialize(tss_p); |
187 | tss_initialize(tss_p); |
186 | 188 | ||
187 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
189 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
188 | gdt_p[TSS_DES].special = 1; |
190 | gdt_p[TSS_DES].special = 1; |
189 | gdt_p[TSS_DES].granularity = 1; |
191 | gdt_p[TSS_DES].granularity = 1; |
190 | 192 | ||
191 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
193 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
192 | gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1); |
194 | gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1); |
193 | 195 | ||
194 | /* |
196 | /* |
195 | * As of this moment, the current CPU has its own GDT pointing |
197 | * As of this moment, the current CPU has its own GDT pointing |
196 | * to its own TSS. We just need to load the TR register. |
198 | * to its own TSS. We just need to load the TR register. |
197 | */ |
199 | */ |
198 | __asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
200 | __asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
199 | 201 | ||
200 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ |
202 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ |
201 | clean_AM_flag(); /* Disable alignment check */ |
203 | clean_AM_flag(); /* Disable alignment check */ |
202 | } |
204 | } |
203 | 205 |