WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/pm.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/pm.h>
#include <config.h>
#include <arch/types.h>
#include <typedefs.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <arch/context.h>
#include <panic.h>
#include <arch/mm/page.h>
#include <mm/heap.h>
#include <memstr.h>
#include <arch/boot/boot.h>
 
/*
 * Early ia32 configuration functions and data structures.
 */
 
/*
 * We have no use for segmentation so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 */
struct descriptor gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
    /* KDATA descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
    /* UTEXT descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    /* UDATA descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    /* TSS descriptor - set up will be completed later */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
 
static struct idescriptor idt[IDT_ITEMS];
 
static struct tss tss;
 
struct tss *tss_p = NULL;
 
/* gdtr is changed by kmp before next CPU is initialized */
struct ptr_16_32 bsp_bootstrap_gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt - BOOT_OFFSET) };
struct ptr_16_32 ap_bootstrap_gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
struct ptr_16_32 gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
 
 
void gdt_setbase(struct descriptor *d, __address base)
{
    d->base_0_15 = base & 0xffff;
    d->base_16_23 = ((base) >> 16) & 0xff;
    d->base_24_31 = ((base) >> 24) & 0xff;
}
 
void gdt_setlimit(struct descriptor *d, __u32 limit)
{
    d->limit_0_15 = limit & 0xffff;
    d->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(struct idescriptor *d, __address offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16;
}
 
void tss_initialize(struct tss *t)
{
    memsetb((__address) t, sizeof(struct tss), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    struct idescriptor *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 
        d->unused = 0;
        d->selector = selector(KTEXT_DES);
 
        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
 
        if (i == VECTOR_SYSCALL) {
            /*
             * The syscall interrupt gate must be calleable from userland.
             */
            d->access |= DPL_USER;
        }
       
        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
        trap_register(i, null_interrupt);
    }
    trap_register(13, gp_fault);
    trap_register( 7, nm_fault);
    trap_register(12, ss_fault);
}
 
 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
static void clean_IOPL_NT_flags(void)
{
    asm
    (
        "pushfl;"
        "pop %%eax;"
        "and $0xffff8fff,%%eax;"
        "push %%eax;"
        "popfl;"
        :
        :
        :"%eax"
    );
}
 
/* Clean AM(18) flag in CR0 register */
static void clean_AM_flag(void)
{
    asm
    (
        "mov %%cr0,%%eax;"
        "and $0xFFFBFFFF,%%eax;"
        "mov %%eax,%%cr0;"
        :
        :
        :"%eax"
    );
}
 
void pm_init(void)
{
    struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
 
    struct ptr_16_32 idtr;
 
    /*
     * Update addresses in GDT and IDT to their virtual counterparts.
     */
 
    idtr.limit = sizeof(idt);
    idtr.base = (__address) idt;
    __asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
    __asm__ volatile ("lidt %0\n" : : "m" (idtr)); 
   
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */
 
    if (config.cpu_active == 1) {
        idt_init();
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    }
    else {
        tss_p = (struct tss *) malloc(sizeof(struct tss));
        if (!tss_p)
            panic("could not allocate TSS\n");
    }
 
    tss_initialize(tss_p);
   
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
    gdt_p[TSS_DES].special = 1;
    gdt_p[TSS_DES].granularity = 1;
   
    gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
    gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
 
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
    __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
   
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
    clean_AM_flag();          /* Disable alignment check */
}
 

Rev 269	Rev 271
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/pm.h>	29	#include <arch/pm.h>
30	#include <config.h>	30	#include <config.h>
31	#include <arch/types.h>	31	#include <arch/types.h>
32	#include <typedefs.h>	32	#include <typedefs.h>
33	#include <arch/interrupt.h>	33	#include <arch/interrupt.h>
34	#include <arch/asm.h>	34	#include <arch/asm.h>
35	#include <arch/context.h>	35	#include <arch/context.h>
36	#include <panic.h>	36	#include <panic.h>
37	#include <arch/mm/page.h>	37	#include <arch/mm/page.h>
38	#include <mm/heap.h>	38	#include <mm/heap.h>
39	#include <memstr.h>	39	#include <memstr.h>
40	#include <arch/boot/boot.h>	40	#include <arch/boot/boot.h>
41		41
42	/*	42	/*
43	* Early ia32 configuration functions and data structures.	43	* Early ia32 configuration functions and data structures.
44	*/	44	*/
45		45
46	/*	46	/*
47	* We have no use for segmentation so we set up flat mode. In this	47	* We have no use for segmentation so we set up flat mode. In this
48	* mode, we use, for each privilege level, two segments spanning the	48	* mode, we use, for each privilege level, two segments spanning the
49	* whole memory. One is for code and one is for data.	49	* whole memory. One is for code and one is for data.
50	*/	50	*/
51	struct descriptor gdt[GDT_ITEMS] = {	51	struct descriptor gdt[GDT_ITEMS] = {
52	/* NULL descriptor */	52	/* NULL descriptor */
53	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	53	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
54	/* KTEXT descriptor */	54	/* KTEXT descriptor */
55	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },	55	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
56	/* KDATA descriptor */	56	/* KDATA descriptor */
57	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },	57	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
58	/* UTEXT descriptor */	58	/* UTEXT descriptor */
59	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },	59	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
60	/* UDATA descriptor */	60	/* UDATA descriptor */
61	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },	61	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
62	/* TSS descriptor - set up will be completed later */	62	/* TSS descriptor - set up will be completed later */
63	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }	63	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
64	};	64	};
65		65
66	static struct idescriptor idt[IDT_ITEMS];	66	static struct idescriptor idt[IDT_ITEMS];
67		67
68	static struct tss tss;	68	static struct tss tss;
69		69
70	struct tss *tss_p = NULL;	70	struct tss *tss_p = NULL;
71		71
72	/* gdtr is changed by kmp before next CPU is initialized */	72	/* gdtr is changed by kmp before next CPU is initialized */
73	struct ptr_16_32 bsp_bootstrap_gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt - BOOT_OFFSET) };	73	struct ptr_16_32 bsp_bootstrap_gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt - BOOT_OFFSET) };
74	struct ptr_16_32 ap_bootstrap_gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };	74	struct ptr_16_32 ap_bootstrap_gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
75	struct ptr_16_32 gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };	75	struct ptr_16_32 gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
76	struct ptr_16_32 idtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(idt), .base = KA2PA((__address) idt) };	-
77		76
78	void gdt_setbase(struct descriptor *d, __address base)	77	void gdt_setbase(struct descriptor *d, __address base)
79	{	78	{
80	d->base_0_15 = base & 0xffff;	79	d->base_0_15 = base & 0xffff;
81	d->base_16_23 = ((base) >> 16) & 0xff;	80	d->base_16_23 = ((base) >> 16) & 0xff;
82	d->base_24_31 = ((base) >> 24) & 0xff;	81	d->base_24_31 = ((base) >> 24) & 0xff;
83	}	82	}
84		83
85	void gdt_setlimit(struct descriptor *d, __u32 limit)	84	void gdt_setlimit(struct descriptor *d, __u32 limit)
86	{	85	{
87	d->limit_0_15 = limit & 0xffff;	86	d->limit_0_15 = limit & 0xffff;
88	d->limit_16_19 = (limit >> 16) & 0xf;	87	d->limit_16_19 = (limit >> 16) & 0xf;
89	}	88	}
90		89
91	void idt_setoffset(struct idescriptor *d, __address offset)	90	void idt_setoffset(struct idescriptor *d, __address offset)
92	{	91	{
93	/*	92	/*
94	* Offset is a linear address.	93	* Offset is a linear address.
95	*/	94	*/
96	d->offset_0_15 = offset & 0xffff;	95	d->offset_0_15 = offset & 0xffff;
97	d->offset_16_31 = offset >> 16;	96	d->offset_16_31 = offset >> 16;
98	}	97	}
99		98
100	void tss_initialize(struct tss *t)	99	void tss_initialize(struct tss *t)
101	{	100	{
102	memsetb((__address) t, sizeof(struct tss), 0);	101	memsetb((__address) t, sizeof(struct tss), 0);
103	}	102	}
104		103
105	/*	104	/*
106	* This function takes care of proper setup of IDT and IDTR.	105	* This function takes care of proper setup of IDT and IDTR.
107	*/	106	*/
108	void idt_init(void)	107	void idt_init(void)
109	{	108	{
110	struct idescriptor *d;	109	struct idescriptor *d;
111	int i;	110	int i;
112		111
113	for (i = 0; i < IDT_ITEMS; i++) {	112	for (i = 0; i < IDT_ITEMS; i++) {
114	d = &idt[i];	113	d = &idt[i];
115		114
116	d->unused = 0;	115	d->unused = 0;
117	d->selector = selector(KTEXT_DES);	116	d->selector = selector(KTEXT_DES);
118		117
119	d->access = AR_PRESENT \| AR_INTERRUPT; /* masking interrupt */	118	d->access = AR_PRESENT \| AR_INTERRUPT; /* masking interrupt */
120		119
121	if (i == VECTOR_SYSCALL) {	120	if (i == VECTOR_SYSCALL) {
122	/*	121	/*
123	* The syscall interrupt gate must be calleable from userland.	122	* The syscall interrupt gate must be calleable from userland.
124	*/	123	*/
125	d->access \|= DPL_USER;	124	d->access \|= DPL_USER;
126	}	125	}
127		126
128	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);	127	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
129	trap_register(i, null_interrupt);	128	trap_register(i, null_interrupt);
130	}	129	}
131	trap_register(13, gp_fault);	130	trap_register(13, gp_fault);
132	trap_register( 7, nm_fault);	131	trap_register( 7, nm_fault);
133	trap_register(12, ss_fault);	132	trap_register(12, ss_fault);
134	}	133	}
135		134
136		135
137	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */	136	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
138	static void clean_IOPL_NT_flags(void)	137	static void clean_IOPL_NT_flags(void)
139	{	138	{
140	asm	139	asm
141	(	140	(
142	"pushfl;"	141	"pushfl;"
143	"pop %%eax;"	142	"pop %%eax;"
144	"and $0xffff8fff,%%eax;"	143	"and $0xffff8fff,%%eax;"
145	"push %%eax;"	144	"push %%eax;"
146	"popfl;"	145	"popfl;"
147	:	146	:
148	:	147	:
149	:"%eax"	148	:"%eax"
150	);	149	);
151	}	150	}
152		151
153	/* Clean AM(18) flag in CR0 register */	152	/* Clean AM(18) flag in CR0 register */
154	static void clean_AM_flag(void)	153	static void clean_AM_flag(void)
155	{	154	{
156	asm	155	asm
157	(	156	(
158	"mov %%cr0,%%eax;"	157	"mov %%cr0,%%eax;"
159	"and $0xFFFBFFFF,%%eax;"	158	"and $0xFFFBFFFF,%%eax;"
160	"mov %%eax,%%cr0;"	159	"mov %%eax,%%cr0;"
161	:	160	:
162	:	161	:
163	:"%eax"	162	:"%eax"
164	);	163	);
165	}	164	}
166		165
167	void pm_init(void)	166	void pm_init(void)
168	{	167	{
169	struct descriptor gdt_p = (struct descriptor ) PA2KA(gdtr.base);	168	struct descriptor gdt_p = (struct descriptor ) gdtr.base;
170		-
-		169	struct ptr_16_32 idtr;
171		170
172	/*	171	/*
173	* Update addresses in GDT and IDT to their virtual counterparts.	172	* Update addresses in GDT and IDT to their virtual counterparts.
174	*/	173	*/
175	if (config.cpu_active == 1)	-
176	gdtr.base = (__address) gdt;	174	idtr.limit = sizeof(idt);
177	idtr.base = (__address) idt;	175	idtr.base = (__address) idt;
178	__asm__ volatile ("lgdt %0\n" : : "m" (gdtr));	176	__asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
179	__asm__ volatile ("lidt %0\n" : : "m" (idtr));	177	__asm__ volatile ("lidt %0\n" : : "m" (idtr));
180		178
181	/*	179	/*
182	* Each CPU has its private GDT and TSS.	180	* Each CPU has its private GDT and TSS.
183	* All CPUs share one IDT.	181	* All CPUs share one IDT.
184	*/	182	*/
185		183
186	if (config.cpu_active == 1) {	184	if (config.cpu_active == 1) {
187	idt_init();	185	idt_init();
188	/*	186	/*
189	* NOTE: bootstrap CPU has statically allocated TSS, because	187	* NOTE: bootstrap CPU has statically allocated TSS, because
190	* the heap hasn't been initialized so far.	188	* the heap hasn't been initialized so far.
191	*/	189	*/
192	tss_p = &tss;	190	tss_p = &tss;
193	}	191	}
194	else {	192	else {
195	tss_p = (struct tss *) malloc(sizeof(struct tss));	193	tss_p = (struct tss *) malloc(sizeof(struct tss));
196	if (!tss_p)	194	if (!tss_p)
197	panic("could not allocate TSS\n");	195	panic("could not allocate TSS\n");
198	}	196	}
199		197
200	tss_initialize(tss_p);	198	tss_initialize(tss_p);
201		199
202	gdt_p[TSS_DES].access = AR_PRESENT \| AR_TSS \| DPL_KERNEL;	200	gdt_p[TSS_DES].access = AR_PRESENT \| AR_TSS \| DPL_KERNEL;
203	gdt_p[TSS_DES].special = 1;	201	gdt_p[TSS_DES].special = 1;
204	gdt_p[TSS_DES].granularity = 1;	202	gdt_p[TSS_DES].granularity = 1;
205		203
206	gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);	204	gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
207	gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);	205	gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
208		206
209	/*	207	/*
210	* As of this moment, the current CPU has its own GDT pointing	208	* As of this moment, the current CPU has its own GDT pointing
211	* to its own TSS. We just need to load the TR register.	209	* to its own TSS. We just need to load the TR register.
212	*/	210	*/
213	__asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));	211	__asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
214		212
215	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */	213	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */
216	clean_AM_flag(); /* Disable alignment check */	214	clean_AM_flag(); /* Disable alignment check */
217	}	215	}
218		216

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia32/src/pm.c @ 1780 – Rev 269 → 271