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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/pm.h> |
29 | #include <arch/pm.h> |
30 | #include <config.h> |
30 | #include <config.h> |
31 | #include <arch/types.h> |
31 | #include <arch/types.h> |
32 | #include <typedefs.h> |
32 | #include <typedefs.h> |
33 | #include <arch/interrupt.h> |
33 | #include <arch/interrupt.h> |
34 | #include <arch/asm.h> |
34 | #include <arch/asm.h> |
35 | #include <arch/context.h> |
35 | #include <arch/context.h> |
36 | #include <panic.h> |
36 | #include <panic.h> |
37 | #include <arch/mm/page.h> |
37 | #include <arch/mm/page.h> |
38 | #include <mm/slab.h> |
38 | #include <mm/slab.h> |
39 | #include <memstr.h> |
39 | #include <memstr.h> |
40 | #include <arch/boot/boot.h> |
40 | #include <arch/boot/boot.h> |
41 | #include <interrupt.h> |
41 | #include <interrupt.h> |
42 | 42 | ||
43 | /* |
43 | /* |
44 | * Early ia32 configuration functions and data structures. |
44 | * Early ia32 configuration functions and data structures. |
45 | */ |
45 | */ |
46 | 46 | ||
47 | /* |
47 | /* |
48 | * We have no use for segmentation so we set up flat mode. In this |
48 | * We have no use for segmentation so we set up flat mode. In this |
49 | * mode, we use, for each privilege level, two segments spanning the |
49 | * mode, we use, for each privilege level, two segments spanning the |
50 | * whole memory. One is for code and one is for data. |
50 | * whole memory. One is for code and one is for data. |
51 | * |
51 | * |
52 | * One is for GS register which holds pointer to the TLS thread |
52 | * One is for GS register which holds pointer to the TLS thread |
53 | * structure in it's base. |
53 | * structure in it's base. |
54 | */ |
54 | */ |
55 | descriptor_t gdt[GDT_ITEMS] = { |
55 | descriptor_t gdt[GDT_ITEMS] = { |
56 | /* NULL descriptor */ |
56 | /* NULL descriptor */ |
57 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
57 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
58 | /* KTEXT descriptor */ |
58 | /* KTEXT descriptor */ |
59 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
59 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
60 | /* KDATA descriptor */ |
60 | /* KDATA descriptor */ |
61 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
61 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
62 | /* UTEXT descriptor */ |
62 | /* UTEXT descriptor */ |
63 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
63 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
64 | /* UDATA descriptor */ |
64 | /* UDATA descriptor */ |
65 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
65 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
66 | /* TSS descriptor - set up will be completed later */ |
66 | /* TSS descriptor - set up will be completed later */ |
67 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
67 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
68 | /* TLS descriptor */ |
68 | /* TLS descriptor */ |
69 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
69 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
70 | /* VESA Init descriptor */ |
70 | /* VESA Init descriptor */ |
- | 71 | #ifdef CONFIG_FB |
|
71 | { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 } |
72 | { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 } |
72 | 73 | #endif |
|
73 | }; |
74 | }; |
74 | 75 | ||
75 | static idescriptor_t idt[IDT_ITEMS]; |
76 | static idescriptor_t idt[IDT_ITEMS]; |
76 | 77 | ||
77 | static tss_t tss; |
78 | static tss_t tss; |
78 | 79 | ||
79 | tss_t *tss_p = NULL; |
80 | tss_t *tss_p = NULL; |
80 | 81 | ||
81 | /* gdtr is changed by kmp before next CPU is initialized */ |
82 | /* gdtr is changed by kmp before next CPU is initialized */ |
82 | ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) }; |
83 | ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) }; |
83 | ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (__address) gdt }; |
84 | ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (__address) gdt }; |
84 | 85 | ||
85 | void gdt_setbase(descriptor_t *d, __address base) |
86 | void gdt_setbase(descriptor_t *d, __address base) |
86 | { |
87 | { |
87 | d->base_0_15 = base & 0xffff; |
88 | d->base_0_15 = base & 0xffff; |
88 | d->base_16_23 = ((base) >> 16) & 0xff; |
89 | d->base_16_23 = ((base) >> 16) & 0xff; |
89 | d->base_24_31 = ((base) >> 24) & 0xff; |
90 | d->base_24_31 = ((base) >> 24) & 0xff; |
90 | } |
91 | } |
91 | 92 | ||
92 | void gdt_setlimit(descriptor_t *d, __u32 limit) |
93 | void gdt_setlimit(descriptor_t *d, __u32 limit) |
93 | { |
94 | { |
94 | d->limit_0_15 = limit & 0xffff; |
95 | d->limit_0_15 = limit & 0xffff; |
95 | d->limit_16_19 = (limit >> 16) & 0xf; |
96 | d->limit_16_19 = (limit >> 16) & 0xf; |
96 | } |
97 | } |
97 | 98 | ||
98 | void idt_setoffset(idescriptor_t *d, __address offset) |
99 | void idt_setoffset(idescriptor_t *d, __address offset) |
99 | { |
100 | { |
100 | /* |
101 | /* |
101 | * Offset is a linear address. |
102 | * Offset is a linear address. |
102 | */ |
103 | */ |
103 | d->offset_0_15 = offset & 0xffff; |
104 | d->offset_0_15 = offset & 0xffff; |
104 | d->offset_16_31 = offset >> 16; |
105 | d->offset_16_31 = offset >> 16; |
105 | } |
106 | } |
106 | 107 | ||
107 | void tss_initialize(tss_t *t) |
108 | void tss_initialize(tss_t *t) |
108 | { |
109 | { |
109 | memsetb((__address) t, sizeof(struct tss), 0); |
110 | memsetb((__address) t, sizeof(struct tss), 0); |
110 | } |
111 | } |
111 | 112 | ||
112 | /* |
113 | /* |
113 | * This function takes care of proper setup of IDT and IDTR. |
114 | * This function takes care of proper setup of IDT and IDTR. |
114 | */ |
115 | */ |
115 | void idt_init(void) |
116 | void idt_init(void) |
116 | { |
117 | { |
117 | idescriptor_t *d; |
118 | idescriptor_t *d; |
118 | int i; |
119 | int i; |
119 | 120 | ||
120 | for (i = 0; i < IDT_ITEMS; i++) { |
121 | for (i = 0; i < IDT_ITEMS; i++) { |
121 | d = &idt[i]; |
122 | d = &idt[i]; |
122 | 123 | ||
123 | d->unused = 0; |
124 | d->unused = 0; |
124 | d->selector = selector(KTEXT_DES); |
125 | d->selector = selector(KTEXT_DES); |
125 | 126 | ||
126 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
127 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
127 | 128 | ||
128 | if (i == VECTOR_SYSCALL) { |
129 | if (i == VECTOR_SYSCALL) { |
129 | /* |
130 | /* |
130 | * The syscall interrupt gate must be calleable from userland. |
131 | * The syscall interrupt gate must be calleable from userland. |
131 | */ |
132 | */ |
132 | d->access |= DPL_USER; |
133 | d->access |= DPL_USER; |
133 | } |
134 | } |
134 | 135 | ||
135 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
136 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
136 | exc_register(i, "undef", (iroutine) null_interrupt); |
137 | exc_register(i, "undef", (iroutine) null_interrupt); |
137 | } |
138 | } |
138 | exc_register(13, "gp_fault", (iroutine) gp_fault); |
139 | exc_register(13, "gp_fault", (iroutine) gp_fault); |
139 | exc_register( 7, "nm_fault", (iroutine) nm_fault); |
140 | exc_register( 7, "nm_fault", (iroutine) nm_fault); |
140 | exc_register(12, "ss_fault", (iroutine) ss_fault); |
141 | exc_register(12, "ss_fault", (iroutine) ss_fault); |
141 | exc_register(19, "simd_fp", (iroutine) simd_fp_exception); |
142 | exc_register(19, "simd_fp", (iroutine) simd_fp_exception); |
142 | } |
143 | } |
143 | 144 | ||
144 | 145 | ||
145 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
146 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
146 | static void clean_IOPL_NT_flags(void) |
147 | static void clean_IOPL_NT_flags(void) |
147 | { |
148 | { |
148 | __asm__ volatile ( |
149 | __asm__ volatile ( |
149 | "pushfl\n" |
150 | "pushfl\n" |
150 | "pop %%eax\n" |
151 | "pop %%eax\n" |
151 | "and $0xffff8fff, %%eax\n" |
152 | "and $0xffff8fff, %%eax\n" |
152 | "push %%eax\n" |
153 | "push %%eax\n" |
153 | "popfl\n" |
154 | "popfl\n" |
154 | : : : "eax" |
155 | : : : "eax" |
155 | ); |
156 | ); |
156 | } |
157 | } |
157 | 158 | ||
158 | /* Clean AM(18) flag in CR0 register */ |
159 | /* Clean AM(18) flag in CR0 register */ |
159 | static void clean_AM_flag(void) |
160 | static void clean_AM_flag(void) |
160 | { |
161 | { |
161 | __asm__ volatile ( |
162 | __asm__ volatile ( |
162 | "mov %%cr0, %%eax\n" |
163 | "mov %%cr0, %%eax\n" |
163 | "and $0xfffbffff, %%eax\n" |
164 | "and $0xfffbffff, %%eax\n" |
164 | "mov %%eax, %%cr0\n" |
165 | "mov %%eax, %%cr0\n" |
165 | : : : "eax" |
166 | : : : "eax" |
166 | ); |
167 | ); |
167 | } |
168 | } |
168 | 169 | ||
169 | void pm_init(void) |
170 | void pm_init(void) |
170 | { |
171 | { |
171 | descriptor_t *gdt_p = (descriptor_t *) gdtr.base; |
172 | descriptor_t *gdt_p = (descriptor_t *) gdtr.base; |
172 | ptr_16_32_t idtr; |
173 | ptr_16_32_t idtr; |
173 | 174 | ||
174 | /* |
175 | /* |
175 | * Update addresses in GDT and IDT to their virtual counterparts. |
176 | * Update addresses in GDT and IDT to their virtual counterparts. |
176 | */ |
177 | */ |
177 | idtr.limit = sizeof(idt); |
178 | idtr.limit = sizeof(idt); |
178 | idtr.base = (__address) idt; |
179 | idtr.base = (__address) idt; |
179 | gdtr_load(&gdtr); |
180 | gdtr_load(&gdtr); |
180 | idtr_load(&idtr); |
181 | idtr_load(&idtr); |
181 | 182 | ||
182 | /* |
183 | /* |
183 | * Each CPU has its private GDT and TSS. |
184 | * Each CPU has its private GDT and TSS. |
184 | * All CPUs share one IDT. |
185 | * All CPUs share one IDT. |
185 | */ |
186 | */ |
186 | 187 | ||
187 | if (config.cpu_active == 1) { |
188 | if (config.cpu_active == 1) { |
188 | idt_init(); |
189 | idt_init(); |
189 | /* |
190 | /* |
190 | * NOTE: bootstrap CPU has statically allocated TSS, because |
191 | * NOTE: bootstrap CPU has statically allocated TSS, because |
191 | * the heap hasn't been initialized so far. |
192 | * the heap hasn't been initialized so far. |
192 | */ |
193 | */ |
193 | tss_p = &tss; |
194 | tss_p = &tss; |
194 | } |
195 | } |
195 | else { |
196 | else { |
196 | tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
197 | tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
197 | if (!tss_p) |
198 | if (!tss_p) |
198 | panic("could not allocate TSS\n"); |
199 | panic("could not allocate TSS\n"); |
199 | } |
200 | } |
200 | 201 | ||
201 | tss_initialize(tss_p); |
202 | tss_initialize(tss_p); |
202 | 203 | ||
203 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
204 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
204 | gdt_p[TSS_DES].special = 1; |
205 | gdt_p[TSS_DES].special = 1; |
205 | gdt_p[TSS_DES].granularity = 0; |
206 | gdt_p[TSS_DES].granularity = 0; |
206 | 207 | ||
207 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
208 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
208 | gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
209 | gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
209 | 210 | ||
210 | /* |
211 | /* |
211 | * As of this moment, the current CPU has its own GDT pointing |
212 | * As of this moment, the current CPU has its own GDT pointing |
212 | * to its own TSS. We just need to load the TR register. |
213 | * to its own TSS. We just need to load the TR register. |
213 | */ |
214 | */ |
214 | tr_load(selector(TSS_DES)); |
215 | tr_load(selector(TSS_DES)); |
215 | 216 | ||
216 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
217 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
217 | clean_AM_flag(); /* Disable alignment check */ |
218 | clean_AM_flag(); /* Disable alignment check */ |
218 | } |
219 | } |
219 | 220 | ||
220 | void set_tls_desc(__address tls) |
221 | void set_tls_desc(__address tls) |
221 | { |
222 | { |
222 | ptr_16_32_t cpugdtr; |
223 | ptr_16_32_t cpugdtr; |
223 | descriptor_t *gdt_p; |
224 | descriptor_t *gdt_p; |
224 | 225 | ||
225 | gdtr_store(&cpugdtr); |
226 | gdtr_store(&cpugdtr); |
226 | gdt_p = (descriptor_t *) cpugdtr.base; |
227 | gdt_p = (descriptor_t *) cpugdtr.base; |
227 | gdt_setbase(&gdt_p[TLS_DES], tls); |
228 | gdt_setbase(&gdt_p[TLS_DES], tls); |
228 | /* Reload gdt register to update GS in CPU */ |
229 | /* Reload gdt register to update GS in CPU */ |
229 | gdtr_load(&cpugdtr); |
230 | gdtr_load(&cpugdtr); |
230 | } |
231 | } |
231 | 232 |