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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __APIC_H__ |
29 | #ifndef __APIC_H__ |
30 | #define __APIC_H__ |
30 | #define __APIC_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <cpu.h> |
33 | #include <cpu.h> |
34 | 34 | ||
35 | #define FIXED (0<<0) |
35 | #define FIXED (0<<0) |
36 | #define LOPRI (1<<0) |
36 | #define LOPRI (1<<0) |
37 | 37 | ||
- | 38 | #define APIC_ID_COUNT 16 |
|
- | 39 | ||
38 | /* local APIC macros */ |
40 | /* local APIC macros */ |
39 | #define IPI_INIT 0 |
41 | #define IPI_INIT 0 |
40 | #define IPI_STARTUP 0 |
42 | #define IPI_STARTUP 0 |
41 | 43 | ||
42 | /** Delivery modes. */ |
44 | /** Delivery modes. */ |
43 | #define DELMOD_FIXED 0x0 |
45 | #define DELMOD_FIXED 0x0 |
44 | #define DELMOD_LOWPRI 0x1 |
46 | #define DELMOD_LOWPRI 0x1 |
45 | #define DELMOD_SMI 0x2 |
47 | #define DELMOD_SMI 0x2 |
46 | /* 0x3 reserved */ |
48 | /* 0x3 reserved */ |
47 | #define DELMOD_NMI 0x4 |
49 | #define DELMOD_NMI 0x4 |
48 | #define DELMOD_INIT 0x5 |
50 | #define DELMOD_INIT 0x5 |
49 | #define DELMOD_STARTUP 0x6 |
51 | #define DELMOD_STARTUP 0x6 |
50 | #define DELMOD_EXTINT 0x7 |
52 | #define DELMOD_EXTINT 0x7 |
51 | 53 | ||
52 | /** Destination modes. */ |
54 | /** Destination modes. */ |
53 | #define DESTMOD_PHYS 0x0 |
55 | #define DESTMOD_PHYS 0x0 |
54 | #define DESTMOD_LOGIC 0x1 |
56 | #define DESTMOD_LOGIC 0x1 |
55 | 57 | ||
56 | /** Trigger Modes. */ |
58 | /** Trigger Modes. */ |
57 | #define TRIGMOD_EDGE 0x0 |
59 | #define TRIGMOD_EDGE 0x0 |
58 | #define TRIGMOD_LEVEL 0x1 |
60 | #define TRIGMOD_LEVEL 0x1 |
59 | 61 | ||
60 | /** Levels. */ |
62 | /** Levels. */ |
61 | #define LEVEL_DEASSERT 0x0 |
63 | #define LEVEL_DEASSERT 0x0 |
62 | #define LEVEL_ASSERT 0x1 |
64 | #define LEVEL_ASSERT 0x1 |
63 | 65 | ||
64 | /** Destination Shorthands. */ |
66 | /** Destination Shorthands. */ |
65 | #define SHORTHAND_NONE 0x0 |
67 | #define SHORTHAND_NONE 0x0 |
66 | #define SHORTHAND_SELF 0x1 |
68 | #define SHORTHAND_SELF 0x1 |
67 | #define SHORTHAND_ALL_INCL 0x2 |
69 | #define SHORTHAND_ALL_INCL 0x2 |
68 | #define SHORTHAND_ALL_EXCL 0x3 |
70 | #define SHORTHAND_ALL_EXCL 0x3 |
69 | 71 | ||
70 | /** Interrupt Input Pin Polarities. */ |
72 | /** Interrupt Input Pin Polarities. */ |
71 | #define POLARITY_HIGH 0x0 |
73 | #define POLARITY_HIGH 0x0 |
72 | #define POLARITY_LOW 0x1 |
74 | #define POLARITY_LOW 0x1 |
73 | 75 | ||
74 | /** Divide Values. (Bit 2 is always 0) */ |
76 | /** Divide Values. (Bit 2 is always 0) */ |
75 | #define DIVIDE_2 0x0 |
77 | #define DIVIDE_2 0x0 |
76 | #define DIVIDE_4 0x1 |
78 | #define DIVIDE_4 0x1 |
77 | #define DIVIDE_8 0x2 |
79 | #define DIVIDE_8 0x2 |
78 | #define DIVIDE_16 0x3 |
80 | #define DIVIDE_16 0x3 |
79 | #define DIVIDE_32 0x8 |
81 | #define DIVIDE_32 0x8 |
80 | #define DIVIDE_64 0x9 |
82 | #define DIVIDE_64 0x9 |
81 | #define DIVIDE_128 0xa |
83 | #define DIVIDE_128 0xa |
82 | #define DIVIDE_1 0xb |
84 | #define DIVIDE_1 0xb |
83 | 85 | ||
84 | /** Timer Modes. */ |
86 | /** Timer Modes. */ |
85 | #define TIMER_ONESHOT 0x0 |
87 | #define TIMER_ONESHOT 0x0 |
86 | #define TIMER_PERIODIC 0x1 |
88 | #define TIMER_PERIODIC 0x1 |
87 | 89 | ||
- | 90 | /** Delivery status. */ |
|
- | 91 | #define DELIVS_IDLE 0x0 |
|
88 | #define SEND_PENDING (1<<12) |
92 | #define DELIVS_PENDING 0x1 |
- | 93 | ||
- | 94 | /** Destination masks. */ |
|
- | 95 | #define DEST_ALL 0xff |
|
89 | 96 | ||
90 | /** Interrupt Command Register. */ |
97 | /** Interrupt Command Register. */ |
91 | #define ICRlo (0x300/sizeof(__u32)) |
98 | #define ICRlo (0x300/sizeof(__u32)) |
92 | #define ICRhi (0x310/sizeof(__u32)) |
99 | #define ICRhi (0x310/sizeof(__u32)) |
93 | struct icr { |
100 | struct icr { |
94 | union { |
101 | union { |
95 | __u32 lo; |
102 | __u32 lo; |
96 | struct { |
103 | struct { |
97 | __u8 vector; /**< Interrupt Vector. */ |
104 | __u8 vector; /**< Interrupt Vector. */ |
98 | unsigned delmod : 3; /**< Delivery Mode. */ |
105 | unsigned delmod : 3; /**< Delivery Mode. */ |
99 | unsigned destmod : 1; /**< Destination Mode. */ |
106 | unsigned destmod : 1; /**< Destination Mode. */ |
100 | unsigned delivs : 1; /**< Delivery status (RO). */ |
107 | unsigned delivs : 1; /**< Delivery status (RO). */ |
101 | unsigned : 1; /**< Reserved. */ |
108 | unsigned : 1; /**< Reserved. */ |
102 | unsigned level : 1; /**< Level. */ |
109 | unsigned level : 1; /**< Level. */ |
103 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
110 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
104 | unsigned : 2; /**< Reserved. */ |
111 | unsigned : 2; /**< Reserved. */ |
105 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
112 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
106 | unsigned : 12; /**< Reserved. */ |
113 | unsigned : 12; /**< Reserved. */ |
107 | } __attribute__ ((packed)); |
114 | } __attribute__ ((packed)); |
108 | }; |
115 | }; |
109 | union { |
116 | union { |
110 | __u32 hi; |
117 | __u32 hi; |
111 | struct { |
118 | struct { |
112 | unsigned : 24; /**< Reserved. */ |
119 | unsigned : 24; /**< Reserved. */ |
113 | __u8 dest; /**< Destination field. */ |
120 | __u8 dest; /**< Destination field. */ |
114 | } __attribute__ ((packed)); |
121 | } __attribute__ ((packed)); |
115 | }; |
122 | }; |
116 | } __attribute__ ((packed)); |
123 | } __attribute__ ((packed)); |
117 | typedef struct icr icr_t; |
124 | typedef struct icr icr_t; |
118 | 125 | ||
119 | /* End Of Interrupt */ |
126 | /* End Of Interrupt */ |
120 | #define EOI (0x0b0/sizeof(__u32)) |
127 | #define EOI (0x0b0/sizeof(__u32)) |
121 | 128 | ||
122 | /** Error Status Register. */ |
129 | /** Error Status Register. */ |
123 | #define ESR (0x280/sizeof(__u32)) |
130 | #define ESR (0x280/sizeof(__u32)) |
124 | union esr { |
131 | union esr { |
125 | __u32 value; |
132 | __u32 value; |
126 | __u8 err_bitmap; |
133 | __u8 err_bitmap; |
127 | struct { |
134 | struct { |
128 | unsigned send_checksum_error : 1; |
135 | unsigned send_checksum_error : 1; |
129 | unsigned receive_checksum_error : 1; |
136 | unsigned receive_checksum_error : 1; |
130 | unsigned send_accept_error : 1; |
137 | unsigned send_accept_error : 1; |
131 | unsigned receive_accept_error : 1; |
138 | unsigned receive_accept_error : 1; |
132 | unsigned : 1; |
139 | unsigned : 1; |
133 | unsigned send_illegal_vector : 1; |
140 | unsigned send_illegal_vector : 1; |
134 | unsigned received_illegal_vector : 1; |
141 | unsigned received_illegal_vector : 1; |
135 | unsigned illegal_register_address : 1; |
142 | unsigned illegal_register_address : 1; |
136 | unsigned : 24; |
143 | unsigned : 24; |
137 | } __attribute__ ((packed)); |
144 | } __attribute__ ((packed)); |
138 | }; |
145 | }; |
139 | typedef union esr esr_t; |
146 | typedef union esr esr_t; |
140 | 147 | ||
141 | /* Task Priority Register */ |
148 | /* Task Priority Register */ |
142 | #define TPR (0x080/sizeof(__u32)) |
149 | #define TPR (0x080/sizeof(__u32)) |
143 | #define TPRClear 0xffffff00 |
150 | #define TPRClear 0xffffff00 |
144 | 151 | ||
145 | /** Spurious-Interrupt Vector Register. */ |
152 | /** Spurious-Interrupt Vector Register. */ |
146 | #define SVR (0x0f0/sizeof(__u32)) |
153 | #define SVR (0x0f0/sizeof(__u32)) |
147 | union svr { |
154 | union svr { |
148 | __u32 value; |
155 | __u32 value; |
149 | struct { |
156 | struct { |
150 | __u8 vector; /**< Spurious Vector */ |
157 | __u8 vector; /**< Spurious Vector */ |
151 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */ |
158 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */ |
152 | unsigned focus_checking : 1; /**< Focus Processor Checking */ |
159 | unsigned focus_checking : 1; /**< Focus Processor Checking */ |
153 | unsigned : 22; /**< Reserved. */ |
160 | unsigned : 22; /**< Reserved. */ |
154 | } __attribute__ ((packed)); |
161 | } __attribute__ ((packed)); |
155 | }; |
162 | }; |
156 | typedef union svr svr_t; |
163 | typedef union svr svr_t; |
157 | 164 | ||
158 | /** Time Divide Configuration Register. */ |
165 | /** Time Divide Configuration Register. */ |
159 | #define TDCR (0x3e0/sizeof(__u32)) |
166 | #define TDCR (0x3e0/sizeof(__u32)) |
160 | union tdcr { |
167 | union tdcr { |
161 | __u32 value; |
168 | __u32 value; |
162 | struct { |
169 | struct { |
163 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
170 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
164 | unsigned : 28; /**< Reserved. */ |
171 | unsigned : 28; /**< Reserved. */ |
165 | } __attribute__ ((packed)); |
172 | } __attribute__ ((packed)); |
166 | }; |
173 | }; |
167 | typedef union tdcr tdcr_t; |
174 | typedef union tdcr tdcr_t; |
168 | 175 | ||
169 | /* Initial Count Register for Timer */ |
176 | /* Initial Count Register for Timer */ |
170 | #define ICRT (0x380/sizeof(__u32)) |
177 | #define ICRT (0x380/sizeof(__u32)) |
171 | 178 | ||
172 | /* Current Count Register for Timer */ |
179 | /* Current Count Register for Timer */ |
173 | #define CCRT (0x390/sizeof(__u32)) |
180 | #define CCRT (0x390/sizeof(__u32)) |
174 | 181 | ||
175 | /** LVT Timer register. */ |
182 | /** LVT Timer register. */ |
176 | #define LVT_Tm (0x320/sizeof(__u32)) |
183 | #define LVT_Tm (0x320/sizeof(__u32)) |
177 | union lvt_tm { |
184 | union lvt_tm { |
178 | __u32 value; |
185 | __u32 value; |
179 | struct { |
186 | struct { |
180 | __u8 vector; /**< Local Timer Interrupt vector. */ |
187 | __u8 vector; /**< Local Timer Interrupt vector. */ |
181 | unsigned : 4; /**< Reserved. */ |
188 | unsigned : 4; /**< Reserved. */ |
182 | unsigned delivs : 1; /**< Delivery status (RO). */ |
189 | unsigned delivs : 1; /**< Delivery status (RO). */ |
183 | unsigned : 3; /**< Reserved. */ |
190 | unsigned : 3; /**< Reserved. */ |
184 | unsigned masked : 1; /**< Interrupt Mask. */ |
191 | unsigned masked : 1; /**< Interrupt Mask. */ |
185 | unsigned mode : 1; /**< Timer Mode. */ |
192 | unsigned mode : 1; /**< Timer Mode. */ |
186 | unsigned : 14; /**< Reserved. */ |
193 | unsigned : 14; /**< Reserved. */ |
187 | } __attribute__ ((packed)); |
194 | } __attribute__ ((packed)); |
188 | }; |
195 | }; |
189 | typedef union lvt_tm lvt_tm_t; |
196 | typedef union lvt_tm lvt_tm_t; |
190 | 197 | ||
191 | /** LVT LINT registers. */ |
198 | /** LVT LINT registers. */ |
192 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
199 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
193 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
200 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
194 | union lvt_lint { |
201 | union lvt_lint { |
195 | __u32 value; |
202 | __u32 value; |
196 | struct { |
203 | struct { |
197 | __u8 vector; /**< LINT Interrupt vector. */ |
204 | __u8 vector; /**< LINT Interrupt vector. */ |
198 | unsigned delmod : 3; /**< Delivery Mode. */ |
205 | unsigned delmod : 3; /**< Delivery Mode. */ |
199 | unsigned : 1; /**< Reserved. */ |
206 | unsigned : 1; /**< Reserved. */ |
200 | unsigned delivs : 1; /**< Delivery status (RO). */ |
207 | unsigned delivs : 1; /**< Delivery status (RO). */ |
201 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
208 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
202 | unsigned irr : 1; /**< Remote IRR (RO). */ |
209 | unsigned irr : 1; /**< Remote IRR (RO). */ |
203 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
210 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
204 | unsigned masked : 1; /**< Interrupt Mask. */ |
211 | unsigned masked : 1; /**< Interrupt Mask. */ |
205 | unsigned : 15; /**< Reserved. */ |
212 | unsigned : 15; /**< Reserved. */ |
206 | } __attribute__ ((packed)); |
213 | } __attribute__ ((packed)); |
207 | }; |
214 | }; |
208 | typedef union lvt_lint lvt_lint_t; |
215 | typedef union lvt_lint lvt_lint_t; |
209 | 216 | ||
210 | /** LVT Error register. */ |
217 | /** LVT Error register. */ |
211 | #define LVT_Err (0x370/sizeof(__u32)) |
218 | #define LVT_Err (0x370/sizeof(__u32)) |
212 | union lvt_error { |
219 | union lvt_error { |
213 | __u32 value; |
220 | __u32 value; |
214 | struct { |
221 | struct { |
215 | __u8 vector; /**< Local Timer Interrupt vector. */ |
222 | __u8 vector; /**< Local Timer Interrupt vector. */ |
216 | unsigned : 4; /**< Reserved. */ |
223 | unsigned : 4; /**< Reserved. */ |
217 | unsigned delivs : 1; /**< Delivery status (RO). */ |
224 | unsigned delivs : 1; /**< Delivery status (RO). */ |
218 | unsigned : 3; /**< Reserved. */ |
225 | unsigned : 3; /**< Reserved. */ |
219 | unsigned masked : 1; /**< Interrupt Mask. */ |
226 | unsigned masked : 1; /**< Interrupt Mask. */ |
220 | unsigned : 15; /**< Reserved. */ |
227 | unsigned : 15; /**< Reserved. */ |
221 | } __attribute__ ((packed)); |
228 | } __attribute__ ((packed)); |
222 | }; |
229 | }; |
223 | typedef union lvt_error lvt_error_t; |
230 | typedef union lvt_error lvt_error_t; |
224 | 231 | ||
225 | /** Local APIC ID Register. */ |
232 | /** Local APIC ID Register. */ |
226 | #define L_APIC_ID (0x020/sizeof(__u32)) |
233 | #define L_APIC_ID (0x020/sizeof(__u32)) |
227 | union lapic_id { |
234 | union l_apic_id { |
228 | __u32 value; |
235 | __u32 value; |
229 | struct { |
236 | struct { |
230 | unsigned : 24; /**< Reserved. */ |
237 | unsigned : 24; /**< Reserved. */ |
231 | __u8 apic_id; /**< Local APIC ID. */ |
238 | __u8 apic_id; /**< Local APIC ID. */ |
232 | } __attribute__ ((packed)); |
239 | } __attribute__ ((packed)); |
233 | }; |
240 | }; |
234 | typedef union lapic_id lapic_id_t; |
241 | typedef union l_apic_id l_apic_id_t; |
235 | 242 | ||
236 | /* Local APIC Version Register */ |
243 | /* Local APIC Version Register */ |
237 | #define LAVR (0x030/sizeof(__u32)) |
244 | #define LAVR (0x030/sizeof(__u32)) |
238 | #define LAVR_Mask 0xff |
245 | #define LAVR_Mask 0xff |
239 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
246 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
240 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
247 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
241 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
248 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
242 | 249 | ||
243 | /* IO APIC */ |
250 | /* IO APIC */ |
244 | #define IOREGSEL (0x00/sizeof(__u32)) |
251 | #define IOREGSEL (0x00/sizeof(__u32)) |
245 | #define IOWIN (0x10/sizeof(__u32)) |
252 | #define IOWIN (0x10/sizeof(__u32)) |
246 | 253 | ||
247 | #define IOAPICID 0x00 |
254 | #define IOAPICID 0x00 |
248 | #define IOAPICVER 0x01 |
255 | #define IOAPICVER 0x01 |
249 | #define IOAPICARB 0x02 |
256 | #define IOAPICARB 0x02 |
250 | #define IOREDTBL 0x10 |
257 | #define IOREDTBL 0x10 |
251 | 258 | ||
252 | /** I/O Register Select Register. */ |
259 | /** I/O Register Select Register. */ |
253 | union io_regsel { |
260 | union io_regsel { |
254 | __u32 value; |
261 | __u32 value; |
255 | struct { |
262 | struct { |
256 | __u8 reg_addr; /**< APIC Register Address. */ |
263 | __u8 reg_addr; /**< APIC Register Address. */ |
257 | unsigned : 24; /**< Reserved. */ |
264 | unsigned : 24; /**< Reserved. */ |
258 | } __attribute__ ((packed)); |
265 | } __attribute__ ((packed)); |
259 | }; |
266 | }; |
260 | typedef union io_regsel io_regsel_t; |
267 | typedef union io_regsel io_regsel_t; |
261 | 268 | ||
262 | /** I/O Redirection Register. */ |
269 | /** I/O Redirection Register. */ |
263 | struct io_redirection_reg { |
270 | struct io_redirection_reg { |
264 | union { |
271 | union { |
265 | __u32 lo; |
272 | __u32 lo; |
266 | struct { |
273 | struct { |
267 | __u8 intvec; /**< Interrupt Vector. */ |
274 | __u8 intvec; /**< Interrupt Vector. */ |
268 | unsigned delmod : 3; /**< Delivery Mode. */ |
275 | unsigned delmod : 3; /**< Delivery Mode. */ |
269 | unsigned destmod : 1; /**< Destination mode. */ |
276 | unsigned destmod : 1; /**< Destination mode. */ |
270 | unsigned delivs : 1; /**< Delivery status (RO). */ |
277 | unsigned delivs : 1; /**< Delivery status (RO). */ |
271 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
278 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
272 | unsigned irr : 1; /**< Remote IRR (RO). */ |
279 | unsigned irr : 1; /**< Remote IRR (RO). */ |
273 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
280 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
274 | unsigned masked : 1; /**< Interrupt Mask. */ |
281 | unsigned masked : 1; /**< Interrupt Mask. */ |
275 | unsigned : 15; /**< Reserved. */ |
282 | unsigned : 15; /**< Reserved. */ |
276 | } __attribute__ ((packed)); |
283 | } __attribute__ ((packed)); |
277 | }; |
284 | }; |
278 | union { |
285 | union { |
279 | __u32 hi; |
286 | __u32 hi; |
280 | struct { |
287 | struct { |
281 | unsigned : 24; /**< Reserved. */ |
288 | unsigned : 24; /**< Reserved. */ |
282 | __u8 dest : 8; /**< Destination Field. */ |
289 | __u8 dest : 8; /**< Destination Field. */ |
283 | } __attribute__ ((packed)); |
290 | } __attribute__ ((packed)); |
284 | }; |
291 | }; |
285 | 292 | ||
286 | } __attribute__ ((packed)); |
293 | } __attribute__ ((packed)); |
287 | - | ||
288 | typedef struct io_redirection_reg io_redirection_reg_t; |
294 | typedef struct io_redirection_reg io_redirection_reg_t; |
289 | 295 | ||
- | 296 | ||
- | 297 | /** IO APIC Identification Register. */ |
|
- | 298 | union io_apic_id { |
|
- | 299 | __u32 value; |
|
- | 300 | struct { |
|
- | 301 | unsigned : 24; /**< Reserved. */ |
|
- | 302 | unsigned apic_id : 4; /**< IO APIC ID. */ |
|
- | 303 | unsigned : 4; /**< Reserved. */ |
|
- | 304 | } __attribute__ ((packed)); |
|
- | 305 | }; |
|
- | 306 | typedef union io_apic_id io_apic_id_t; |
|
- | 307 | ||
290 | extern volatile __u32 *l_apic; |
308 | extern volatile __u32 *l_apic; |
291 | extern volatile __u32 *io_apic; |
309 | extern volatile __u32 *io_apic; |
292 | 310 | ||
293 | extern __u32 apic_id_mask; |
311 | extern __u32 apic_id_mask; |
294 | 312 | ||
295 | extern void apic_init(void); |
313 | extern void apic_init(void); |
296 | extern void apic_spurious(__u8 n, __native stack[]); |
314 | extern void apic_spurious(__u8 n, __native stack[]); |
297 | 315 | ||
298 | extern void l_apic_init(void); |
316 | extern void l_apic_init(void); |
299 | extern void l_apic_eoi(void); |
317 | extern void l_apic_eoi(void); |
300 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
318 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
301 | extern int l_apic_send_init_ipi(__u8 apicid); |
319 | extern int l_apic_send_init_ipi(__u8 apicid); |
302 | extern void l_apic_debug(void); |
320 | extern void l_apic_debug(void); |
303 | extern void l_apic_timer_interrupt(__u8 n, __native stack[]); |
321 | extern void l_apic_timer_interrupt(__u8 n, __native stack[]); |
304 | extern __u8 l_apic_id(void); |
322 | extern __u8 l_apic_id(void); |
305 | 323 | ||
306 | extern __u32 io_apic_read(__u8 address); |
324 | extern __u32 io_apic_read(__u8 address); |
307 | extern void io_apic_write(__u8 address , __u32 x); |
325 | extern void io_apic_write(__u8 address , __u32 x); |
308 | extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
326 | extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
309 | extern void io_apic_disable_irqs(__u16 irqmask); |
327 | extern void io_apic_disable_irqs(__u16 irqmask); |
310 | extern void io_apic_enable_irqs(__u16 irqmask); |
328 | extern void io_apic_enable_irqs(__u16 irqmask); |
311 | 329 | ||
312 | #endif |
330 | #endif |
313 | 331 |