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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __APIC_H__ |
29 | #ifndef __APIC_H__ |
30 | #define __APIC_H__ |
30 | #define __APIC_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <cpu.h> |
33 | #include <cpu.h> |
34 | 34 | ||
35 | #define FIXED (0<<0) |
35 | #define FIXED (0<<0) |
36 | #define LOPRI (1<<0) |
36 | #define LOPRI (1<<0) |
37 | 37 | ||
38 | /* local APIC macros */ |
38 | /* local APIC macros */ |
39 | #define IPI_INIT 0 |
39 | #define IPI_INIT 0 |
40 | #define IPI_STARTUP 0 |
40 | #define IPI_STARTUP 0 |
41 | 41 | ||
42 | #define DLVRMODE_FIXED (0<<8) |
42 | #define DLVRMODE_FIXED (0<<8) |
43 | #define DLVRMODE_INIT (5<<8) |
43 | #define DLVRMODE_INIT (5<<8) |
44 | #define DLVRMODE_STUP (6<<8) |
44 | #define DLVRMODE_STUP (6<<8) |
45 | #define DESTMODE_PHYS (0<<11) |
45 | #define DESTMODE_PHYS (0<<11) |
46 | #define DESTMODE_LOGIC (1<<11) |
46 | #define DESTMODE_LOGIC (1<<11) |
47 | #define LEVEL_ASSERT (1<<14) |
47 | #define LEVEL_ASSERT (1<<14) |
48 | #define LEVEL_DEASSERT (0<<14) |
48 | #define LEVEL_DEASSERT (0<<14) |
49 | #define TRGRMODE_LEVEL (1<<15) |
49 | #define TRGRMODE_LEVEL (1<<15) |
50 | #define TRGRMODE_EDGE (0<<15) |
50 | #define TRGRMODE_EDGE (0<<15) |
51 | #define SHORTHAND_DEST (0<<18) |
51 | #define SHORTHAND_DEST (0<<18) |
52 | #define SHORTHAND_INCL (2<<18) |
52 | #define SHORTHAND_INCL (2<<18) |
53 | #define SHORTHAND_EXCL (3<<18) |
53 | #define SHORTHAND_EXCL (3<<18) |
54 | 54 | ||
55 | #define SEND_PENDING (1<<12) |
55 | #define SEND_PENDING (1<<12) |
56 | 56 | ||
57 | /* Interrupt Command Register */ |
57 | /* Interrupt Command Register */ |
58 | #define ICRlo (0x300/sizeof(__u32)) |
58 | #define ICRlo (0x300/sizeof(__u32)) |
59 | #define ICRhi (0x310/sizeof(__u32)) |
59 | #define ICRhi (0x310/sizeof(__u32)) |
60 | #define ICRloClear ((1<<13)|(3<<16)|(0xfff<<20)) |
60 | #define ICRloClear ((1<<13)|(3<<16)|(0xfff<<20)) |
61 | #define ICRhiClear (0xffffff<<0) |
61 | #define ICRhiClear (0xffffff<<0) |
62 | 62 | ||
63 | /* End Of Interrupt */ |
63 | /* End Of Interrupt */ |
64 | #define EOI (0x0b0/sizeof(__u32)) |
64 | #define EOI (0x0b0/sizeof(__u32)) |
65 | 65 | ||
66 | /* Error Status Register */ |
66 | /* Error Status Register */ |
67 | #define ESR (0x280/sizeof(__u32)) |
67 | #define ESR (0x280/sizeof(__u32)) |
68 | #define ESRClear ((0xffffff<<8)|(1<<4)) |
68 | #define ESRClear ((0xffffff<<8)|(1<<4)) |
69 | 69 | ||
70 | /* Task Priority Register */ |
70 | /* Task Priority Register */ |
71 | #define TPR (0x080/sizeof(__u32)) |
71 | #define TPR (0x080/sizeof(__u32)) |
72 | #define TPRClear 0xffffff00 |
72 | #define TPRClear 0xffffff00 |
73 | 73 | ||
74 | /* Spurious Vector Register */ |
74 | /* Spurious Vector Register */ |
75 | #define SVR (0x0f0/sizeof(__u32)) |
75 | #define SVR (0x0f0/sizeof(__u32)) |
76 | #define SVRClear (~0x3f0) |
76 | #define SVRClear (~0x3f0) |
77 | 77 | ||
78 | /* Time Divide Configuratio Register */ |
78 | /* Time Divide Configuratio Register */ |
79 | #define TDCR (0x3e0/sizeof(__u32)) |
79 | #define TDCR (0x3e0/sizeof(__u32)) |
80 | #define TDCRClear (~0xb) |
80 | #define TDCRClear (~0xb) |
81 | 81 | ||
82 | /* Initial Count Register for Timer */ |
82 | /* Initial Count Register for Timer */ |
83 | #define ICRT (0x380/sizeof(__u32)) |
83 | #define ICRT (0x380/sizeof(__u32)) |
84 | 84 | ||
85 | /* Current Count Register for Timer */ |
85 | /* Current Count Register for Timer */ |
86 | #define CCRT (0x390/sizeof(__u32)) |
86 | #define CCRT (0x390/sizeof(__u32)) |
87 | 87 | ||
88 | /* LVT */ |
88 | /* LVT */ |
89 | #define LVT_Tm (0x320/sizeof(__u32)) |
89 | #define LVT_Tm (0x320/sizeof(__u32)) |
90 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
90 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
91 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
91 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
92 | #define LVT_Err (0x370/sizeof(__u32)) |
92 | #define LVT_Err (0x370/sizeof(__u32)) |
93 | #define LVT_PCINT (0x340/sizeof(__u32)) |
93 | #define LVT_PCINT (0x340/sizeof(__u32)) |
94 | 94 | ||
95 | /* Local APIC ID Register */ |
95 | /* Local APIC ID Register */ |
96 | #define L_APIC_ID (0x020/sizeof(__u32)) |
96 | #define L_APIC_ID (0x020/sizeof(__u32)) |
97 | #define L_APIC_IDClear (~(0xf<<24)) |
97 | #define L_APIC_IDClear (~(0xf<<24)) |
98 | #define L_APIC_IDShift 24 |
98 | #define L_APIC_IDShift 24 |
99 | #define L_APIC_IDMask 0xf |
99 | #define L_APIC_IDMask 0xf |
100 | 100 | ||
101 | /* Local APIC Version Register */ |
101 | /* Local APIC Version Register */ |
102 | #define LAVR (0x030/sizeof(__u32)) |
102 | #define LAVR (0x030/sizeof(__u32)) |
103 | #define LAVR_Mask 0xff |
103 | #define LAVR_Mask 0xff |
104 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
104 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
105 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
105 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
106 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
106 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
107 | 107 | ||
108 | /* IO APIC */ |
108 | /* IO APIC */ |
109 | #define IOREGSEL (0x00/sizeof(__u32)) |
109 | #define IOREGSEL (0x00/sizeof(__u32)) |
110 | #define IOWIN (0x10/sizeof(__u32)) |
110 | #define IOWIN (0x10/sizeof(__u32)) |
111 | 111 | ||
112 | #define IOAPICID 0x00 |
112 | #define IOAPICID 0x00 |
113 | #define IOAPICVER 0x01 |
113 | #define IOAPICVER 0x01 |
114 | #define IOAPICARB 0x02 |
114 | #define IOAPICARB 0x02 |
115 | #define IOREDTBL 0x10 |
115 | #define IOREDTBL 0x10 |
116 | 116 | ||
- | 117 | /** Delivery modes. */ |
|
- | 118 | #define DELMOD_FIXED 0x0 |
|
- | 119 | #define DELMOD_LOWPRI 0x1 |
|
- | 120 | #define DELMOD_SMI 0x2 |
|
- | 121 | /* 0x3 reserved */ |
|
- | 122 | #define DELMOD_NMI 0x4 |
|
- | 123 | #define DELMOD_INIT 0x5 |
|
- | 124 | /* 0x6 reserved */ |
|
- | 125 | #define DELMOD_EXTINT 0x7 |
|
- | 126 | ||
- | 127 | /** Destination modes. */ |
|
- | 128 | #define DESTMOD_PHYS 0x0 |
|
- | 129 | #define DESTMOD_LOGIC 0x1 |
|
- | 130 | ||
- | 131 | /** Trigger Modes. */ |
|
- | 132 | #define TRIGMOD_EDGE 0x0 |
|
- | 133 | #define TRIGMOD_LEVEL 0x1 |
|
- | 134 | ||
- | 135 | /** Interrupt Input Pin Polarities. */ |
|
- | 136 | #define POLARITY_HIGH 0x0 |
|
- | 137 | #define POLARITY_LOW 0x1 |
|
- | 138 | ||
- | 139 | /** I/O Redirection Register. */ |
|
- | 140 | struct io_redirection_reg { |
|
- | 141 | union { |
|
- | 142 | __u32 lo; |
|
- | 143 | struct { |
|
- | 144 | unsigned intvec : 8; /**< Interrupt Vector. */ |
|
- | 145 | unsigned delmod : 3; /**< Delivery Mode. */ |
|
- | 146 | unsigned destmod : 1; /**< Destination mode. */ |
|
- | 147 | unsigned delivs : 1; /**< Delivery status (RO). */ |
|
- | 148 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
|
- | 149 | unsigned irr : 1; /**< Remote IRR (RO). */ |
|
- | 150 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
|
- | 151 | unsigned masked : 1; /**< Interrupt Mask. */ |
|
- | 152 | unsigned : 15; /**< Reserved. */ |
|
- | 153 | }; |
|
- | 154 | }; |
|
- | 155 | union { |
|
- | 156 | __u32 hi; |
|
- | 157 | struct { |
|
- | 158 | unsigned : 24; /**< Reserved. */ |
|
- | 159 | unsigned dest : 8; /**< Destination Field. */ |
|
- | 160 | }; |
|
- | 161 | }; |
|
- | 162 | ||
- | 163 | } __attribute__ ((packed)); |
|
- | 164 | ||
- | 165 | typedef struct io_redirection_reg io_redirection_reg_t; |
|
117 | 166 | ||
118 | extern volatile __u32 *l_apic; |
167 | extern volatile __u32 *l_apic; |
119 | extern volatile __u32 *io_apic; |
168 | extern volatile __u32 *io_apic; |
120 | 169 | ||
121 | extern __u32 apic_id_mask; |
170 | extern __u32 apic_id_mask; |
122 | 171 | ||
123 | extern void apic_init(void); |
172 | extern void apic_init(void); |
124 | extern void apic_spurious(__u8 n, __native stack[]); |
173 | extern void apic_spurious(__u8 n, __native stack[]); |
125 | 174 | ||
126 | extern void l_apic_init(void); |
175 | extern void l_apic_init(void); |
127 | extern void l_apic_eoi(void); |
176 | extern void l_apic_eoi(void); |
128 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
177 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
129 | extern int l_apic_send_init_ipi(__u8 apicid); |
178 | extern int l_apic_send_init_ipi(__u8 apicid); |
130 | extern void l_apic_debug(void); |
179 | extern void l_apic_debug(void); |
131 | extern void l_apic_timer_interrupt(__u8 n, __native stack[]); |
180 | extern void l_apic_timer_interrupt(__u8 n, __native stack[]); |
132 | extern __u8 l_apic_id(void); |
181 | extern __u8 l_apic_id(void); |
133 | 182 | ||
134 | extern __u32 io_apic_read(__u8 address); |
183 | extern __u32 io_apic_read(__u8 address); |
135 | extern void io_apic_write(__u8 address , __u32 x); |
184 | extern void io_apic_write(__u8 address , __u32 x); |
136 | extern void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags); |
185 | extern void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags); |
137 | extern void io_apic_disable_irqs(__u16 irqmask); |
186 | extern void io_apic_disable_irqs(__u16 irqmask); |
138 | extern void io_apic_enable_irqs(__u16 irqmask); |
187 | extern void io_apic_enable_irqs(__u16 irqmask); |
139 | 188 | ||
140 | #endif |
189 | #endif |
141 | 190 |