WebSVN – HelenOS – Diff – /kernel/trunk/arch/ia32/include/barrier.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia32_BARRIER_H__
#define __ia32_BARRIER_H__
 
 
 
/*
 * NOTE:
 * No barriers for critical section (i.e. spinlock) on IA-32 are needed:
 * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction
 * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers
 */
 
/*
 * Provisions are made to prevent compiler from reordering instructions itself.
 */
 
#define CS_ENTER_BARRIER()  __asm__ volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER()  __asm__ volatile ("" ::: "memory")
 
static inline void cpuid_serialization(void)
{
    __asm__ volatile (
        "xorl %%eax, %%eax\n"
        "cpuid\n"
        ::: "eax", "ebx", "ecx", "edx", "memory"
    );
}
 
#ifdef CONFIG_FENCES_P4
#   define memory_barrier()     __asm__ volatile ("mfence\n" ::: "memory")
#   define read_barrier()       __asm__ volatile ("lfence\n" ::: "memory")
#   ifdef CONFIG_WEAK_MEMORY
#       define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
#   else
#       define write_barrier()  __asm__ volatile( "" ::: "memory");
#   endif
#elif CONFIG_FENCES_P3
#   define memory_barrier()     cpuid_serialization()
#   define read_barrier()       cpuid_serialization()
#   ifdef CONFIG_WEAK_MEMORY
#       define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
#   else
#       define write_barrier()  __asm__ volatile( "" ::: "memory");
#   endif
#else
#   define memory_barrier()     cpuid_serialization()
#   define read_barrier()       cpuid_serialization()
#   ifdef CONFIG_WEAK_MEMORY
#       define write_barrier()  cpuid_serialization()
#   else
#       define write_barrier()  __asm__ volatile( "" ::: "memory");
#   endif
#endif
 
#endif
 

Rev 534	Rev 1434
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __ia32_BARRIER_H__	29	#ifndef __ia32_BARRIER_H__
30	#define __ia32_BARRIER_H__	30	#define __ia32_BARRIER_H__
31		31
32	#include <arch/types.h>	-
33		-
34	/*	32	/*
35	* NOTE:	33	* NOTE:
36	* No barriers for critical section (i.e. spinlock) on IA-32 are needed:	34	* No barriers for critical section (i.e. spinlock) on IA-32 are needed:
37	* - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction	35	* - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction
38	* - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers	36	* - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers
39	*/	37	*/
40		38
41	/*	39	/*
42	* Provisions are made to prevent compiler from reordering instructions itself.	40	* Provisions are made to prevent compiler from reordering instructions itself.
43	*/	41	*/
44		42
45	#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")	43	#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")
46	#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")	44	#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")
47		45
48	static inline void cpuid_serialization(void)	46	static inline void cpuid_serialization(void)
49	{	47	{
50	__asm__ volatile (	48	__asm__ volatile (
51	"xorl %%eax, %%eax\n"	49	"xorl %%eax, %%eax\n"
52	"cpuid\n"	50	"cpuid\n"
53	::: "eax", "ebx", "ecx", "edx", "memory"	51	::: "eax", "ebx", "ecx", "edx", "memory"
54	);	52	);
55	}	53	}
56		54
57	#ifdef CONFIG_FENCES_P4	55	#ifdef CONFIG_FENCES_P4
58	# define memory_barrier() __asm__ volatile ("mfence\n" ::: "memory")	56	# define memory_barrier() __asm__ volatile ("mfence\n" ::: "memory")
59	# define read_barrier() __asm__ volatile ("lfence\n" ::: "memory")	57	# define read_barrier() __asm__ volatile ("lfence\n" ::: "memory")
60	# ifdef CONFIG_WEAK_MEMORY	58	# ifdef CONFIG_WEAK_MEMORY
61	# define write_barrier() __asm__ volatile ("sfence\n" ::: "memory")	59	# define write_barrier() __asm__ volatile ("sfence\n" ::: "memory")
62	# else	60	# else
63	# define write_barrier()	61	# define write_barrier() __asm__ volatile( "" ::: "memory");
64	# endif	62	# endif
65	#elif CONFIG_FENCES_P3	63	#elif CONFIG_FENCES_P3
66	# define memory_barrier() cpuid_serialization()	64	# define memory_barrier() cpuid_serialization()
67	# define read_barrier() cpuid_serialization()	65	# define read_barrier() cpuid_serialization()
68	# ifdef CONFIG_WEAK_MEMORY	66	# ifdef CONFIG_WEAK_MEMORY
69	# define write_barrier() __asm__ volatile ("sfence\n" ::: "memory")	67	# define write_barrier() __asm__ volatile ("sfence\n" ::: "memory")
70	# else	68	# else
71	# define write_barrier()	69	# define write_barrier() __asm__ volatile( "" ::: "memory");
72	# endif	70	# endif
73	#else	71	#else
74	# define memory_barrier() cpuid_serialization()	72	# define memory_barrier() cpuid_serialization()
75	# define read_barrier() cpuid_serialization()	73	# define read_barrier() cpuid_serialization()
76	# ifdef CONFIG_WEAK_MEMORY	74	# ifdef CONFIG_WEAK_MEMORY
77	# define write_barrier() cpuid_serialization()	75	# define write_barrier() cpuid_serialization()
78	# else	76	# else
79	# define write_barrier()	77	# define write_barrier() __asm__ volatile( "" ::: "memory");
80	# endif	78	# endif
81	#endif	79	#endif
82		80
83	#endif	81	#endif
84		82

Subversion Repositories HelenOS

(root)/kernel/trunk/arch/ia32/include/barrier.h – Rev 534 → 1434