WebSVN – HelenOS – Diff – /kernel/trunk/arch/ia32/include/asm.h


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia32_ASM_H__
#define __ia32_ASM_H__
 
#include <arch/types.h>
 
 
 
 
#include <config.h>
 
extern __u32 interrupt_handler_size;
 
extern void paging_on(void);
 
extern void interrupt_handlers(void);
 
extern __u8 inb(int port);
extern __u16 inw(int port);
extern __u32 inl(int port);
 
extern void outb(int port, __u8 b);
extern void outw(int port, __u16 w);
extern void outl(int port, __u32 l);
 
extern void enable_l_apic_in_msr(void);
 
 
void asm_delay_loop(__u32 t);
void asm_fake_loop(__u32 t);
 
 
/** Halt CPU
 *
 * Halt the current CPU until interrupt event.
 */
static inline void cpu_halt(void) { __asm__("hlt\n"); };
static inline void cpu_sleep(void) { __asm__("hlt\n"); };
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
 
/** Set priority level low
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_low(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n"
        "popl %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Set priority level high
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_high(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n"
        "popl %0\n"
        "cli\n"
        : "=r" (v)
    );
    return v;
}
 
/** Restore priority level
 *
 * Restore EFLAGS.
 */
static inline void cpu_priority_restore(pri_t pri) {
    __asm__ volatile (
        "pushl %0\n"
        "popf\n"
        : : "r" (pri)
    );
}
 
/** Return raw priority level
 *
 * Return EFLAFS.
 */
static inline pri_t cpu_priority_read(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n"
        "popl %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
   
    return v;
}
 
static inline __u64 rdtsc(void)
{
    __u64 v;
   
    __asm__ volatile("rdtsc\n" : "=A" (v));
   
    return v;
}
 
#endif
 

Rev 195	Rev 348
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __ia32_ASM_H__	29	#ifndef __ia32_ASM_H__
30	#define __ia32_ASM_H__	30	#define __ia32_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <typedefs.h>	-
34	#include <config.h>	-
35	#include <synch/spinlock.h>	-
36	#include <arch/boot/memmap.h>	-
37	#include <config.h>	33	#include <config.h>
38		34
39	extern __u32 interrupt_handler_size;	35	extern __u32 interrupt_handler_size;
40		36
41	extern void paging_on(void);	37	extern void paging_on(void);
42		38
43	extern void interrupt_handlers(void);	39	extern void interrupt_handlers(void);
44		40
45	extern __u8 inb(int port);	41	extern __u8 inb(int port);
46	extern __u16 inw(int port);	42	extern __u16 inw(int port);
47	extern __u32 inl(int port);	43	extern __u32 inl(int port);
48		44
49	extern void outb(int port, __u8 b);	45	extern void outb(int port, __u8 b);
50	extern void outw(int port, __u16 w);	46	extern void outw(int port, __u16 w);
51	extern void outl(int port, __u32 l);	47	extern void outl(int port, __u32 l);
52		48
53	extern void enable_l_apic_in_msr(void);	49	extern void enable_l_apic_in_msr(void);
54		50
55		51
56	void asm_delay_loop(__u32 t);	52	void asm_delay_loop(__u32 t);
57	void asm_fake_loop(__u32 t);	53	void asm_fake_loop(__u32 t);
58		54
59		55
60	/** Halt CPU	56	/** Halt CPU
61	*	57	*
62	* Halt the current CPU until interrupt event.	58	* Halt the current CPU until interrupt event.
63	*/	59	*/
64	static inline void cpu_halt(void) { __asm__("hlt"); };	60	static inline void cpu_halt(void) { __asm__("hlt\n"); };
65	static inline void cpu_sleep(void) { __asm__("hlt"); };	61	static inline void cpu_sleep(void) { __asm__("hlt\n"); };
66		62
67	/** Read CR2	63	/** Read CR2
68	*	64	*
69	* Return value in CR2	65	* Return value in CR2
70	*	66	*
71	* @return Value read.	67	* @return Value read.
72	*/	68	*/
73	static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0" : "=r" (v)); return v; }	69	static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
74		70
75	/** Write CR3	71	/** Write CR3
76	*	72	*
77	* Write value to CR3.	73	* Write value to CR3.
78	*	74	*
79	* @param v Value to be written.	75	* @param v Value to be written.
80	*/	76	*/
81	static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }	77	static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
82		78
83	/** Read CR3	79	/** Read CR3
84	*	80	*
85	* Return value in CR3	81	* Return value in CR3
86	*	82	*
87	* @return Value read.	83	* @return Value read.
88	*/	84	*/
89	static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; }	85	static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
90		86
91	/** Set priority level low	87	/** Set priority level low
92	*	88	*
93	* Enable interrupts and return previous	89	* Enable interrupts and return previous
94	* value of EFLAGS.	90	* value of EFLAGS.
95	*/	91	*/
96	static inline pri_t cpu_priority_low(void) {	92	static inline pri_t cpu_priority_low(void) {
97	pri_t v;	93	pri_t v;
98	__asm__ volatile (	94	__asm__ volatile (
99	"pushf\n"	95	"pushf\n"
100	"popl %0\n"	96	"popl %0\n"
101	"sti\n"	97	"sti\n"
102	: "=r" (v)	98	: "=r" (v)
103	);	99	);
104	return v;	100	return v;
105	}	101	}
106		102
107	/** Set priority level high	103	/** Set priority level high
108	*	104	*
109	* Disable interrupts and return previous	105	* Disable interrupts and return previous
110	* value of EFLAGS.	106	* value of EFLAGS.
111	*/	107	*/
112	static inline pri_t cpu_priority_high(void) {	108	static inline pri_t cpu_priority_high(void) {
113	pri_t v;	109	pri_t v;
114	__asm__ volatile (	110	__asm__ volatile (
115	"pushf\n"	111	"pushf\n"
116	"popl %0\n"	112	"popl %0\n"
117	"cli\n"	113	"cli\n"
118	: "=r" (v)	114	: "=r" (v)
119	);	115	);
120	return v;	116	return v;
121	}	117	}
122		118
123	/** Restore priority level	119	/** Restore priority level
124	*	120	*
125	* Restore EFLAGS.	121	* Restore EFLAGS.
126	*/	122	*/
127	static inline void cpu_priority_restore(pri_t pri) {	123	static inline void cpu_priority_restore(pri_t pri) {
128	__asm__ volatile (	124	__asm__ volatile (
129	"pushl %0\n"	125	"pushl %0\n"
130	"popf\n"	126	"popf\n"
131	: : "r" (pri)	127	: : "r" (pri)
132	);	128	);
133	}	129	}
134		130
135	/** Return raw priority level	131	/** Return raw priority level
136	*	132	*
137	* Return EFLAFS.	133	* Return EFLAFS.
138	*/	134	*/
139	static inline pri_t cpu_priority_read(void) {	135	static inline pri_t cpu_priority_read(void) {
140	pri_t v;	136	pri_t v;
141	__asm__ volatile (	137	__asm__ volatile (
142	"pushf\n"	138	"pushf\n"
143	"popl %0\n"	139	"popl %0\n"
144	: "=r" (v)	140	: "=r" (v)
145	);	141	);
146	return v;	142	return v;
147	}	143	}
148		144
149	/** Return base address of current stack	145	/** Return base address of current stack
150	*	146	*
151	* Return the base address of the current stack.	147	* Return the base address of the current stack.
152	* The stack is assumed to be STACK_SIZE bytes long.	148	* The stack is assumed to be STACK_SIZE bytes long.
153	* The stack must start on page boundary.	149	* The stack must start on page boundary.
154	*/	150	*/
155	static inline __address get_stack_base(void)	151	static inline __address get_stack_base(void)
156	{	152	{
157	__address v;	153	__address v;
158		154
159	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));	155	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
160		156
-		157	return v;
-		158	}
-		159
-		160	static inline __u64 rdtsc(void)
-		161	{
-		162	__u64 v;
-		163
-		164	__asm__ volatile("rdtsc\n" : "=A" (v));
-		165
161	return v;	166	return v;
162	}	167	}
163		168
164	#endif	169	#endif
165		170

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(root)/kernel/trunk/arch/ia32/include/asm.h @ 594 – Rev 195 → 348