WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/include/asm.h


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * Copyright (C) 2005 Sergey Bondari
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia32_ASM_H__
#define __ia32_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
extern __u32 interrupt_handler_size;
 
extern void paging_on(void);
 
extern void interrupt_handlers(void);
 
extern void enable_l_apic_in_msr(void);
 
 
void asm_delay_loop(__u32 t);
void asm_fake_loop(__u32 t);
 
 
/** Halt CPU
 *
 * Halt the current CPU until interrupt event.
 */
static inline void cpu_halt(void) { __asm__("hlt\n"); };
static inline void cpu_sleep(void) { __asm__("hlt\n"); };
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Word to port
 *
 * Output word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Double word to port
 *
 * Output double word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Word from port
 *
 * Get word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Double word from port
 *
 * Get double word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushf\n\t"
        "popl %0\n\t"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushf\n\t"
        "popl %0\n\t"
        "cli\n"
        : "=r" (v)
    );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    __asm__ volatile (
        "pushl %0\n\t"
        "popf\n"
        : : "r" (ipl)
    );
}
 
/** Return interrupt priority level.
 *
 * @return EFLAFS.
 */
static inline ipl_t interrupts_read(void) {
    ipl_t v;
    __asm__ volatile (
        "pushf\n\t"
        "popl %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
   
    return v;
}
 
static inline __u64 rdtsc(void)
{
    __u64 v;
   
    __asm__ volatile("rdtsc\n" : "=A" (v));
   
    return v;
}
 
#endif
 

Rev 393	Rev 413
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* Copyright (C) 2005 Sergey Bondari	3	* Copyright (C) 2005 Sergey Bondari
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	#ifndef __ia32_ASM_H__	30	#ifndef __ia32_ASM_H__
31	#define __ia32_ASM_H__	31	#define __ia32_ASM_H__
32		32
33	#include <arch/types.h>	33	#include <arch/types.h>
34	#include <config.h>	34	#include <config.h>
35		35
36	extern __u32 interrupt_handler_size;	36	extern __u32 interrupt_handler_size;
37		37
38	extern void paging_on(void);	38	extern void paging_on(void);
39		39
40	extern void interrupt_handlers(void);	40	extern void interrupt_handlers(void);
41		41
42	extern void enable_l_apic_in_msr(void);	42	extern void enable_l_apic_in_msr(void);
43		43
44		44
45	void asm_delay_loop(__u32 t);	45	void asm_delay_loop(__u32 t);
46	void asm_fake_loop(__u32 t);	46	void asm_fake_loop(__u32 t);
47		47
48		48
49	/** Halt CPU	49	/** Halt CPU
50	*	50	*
51	* Halt the current CPU until interrupt event.	51	* Halt the current CPU until interrupt event.
52	*/	52	*/
53	static inline void cpu_halt(void) { __asm__("hlt\n"); };	53	static inline void cpu_halt(void) { __asm__("hlt\n"); };
54	static inline void cpu_sleep(void) { __asm__("hlt\n"); };	54	static inline void cpu_sleep(void) { __asm__("hlt\n"); };
55		55
56	/** Read CR2	56	/** Read CR2
57	*	57	*
58	* Return value in CR2	58	* Return value in CR2
59	*	59	*
60	* @return Value read.	60	* @return Value read.
61	*/	61	*/
62	static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }	62	static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
63		63
64	/** Write CR3	64	/** Write CR3
65	*	65	*
66	* Write value to CR3.	66	* Write value to CR3.
67	*	67	*
68	* @param v Value to be written.	68	* @param v Value to be written.
69	*/	69	*/
70	static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }	70	static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
71		71
72	/** Read CR3	72	/** Read CR3
73	*	73	*
74	* Return value in CR3	74	* Return value in CR3
75	*	75	*
76	* @return Value read.	76	* @return Value read.
77	*/	77	*/
78	static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }	78	static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
79		79
80	/** Byte to port	80	/** Byte to port
81	*	81	*
82	* Output byte to port	82	* Output byte to port
83	*	83	*
84	* @param port Port to write to	84	* @param port Port to write to
85	* @param val Value to write	85	* @param val Value to write
86	*/	86	*/
87	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	87	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
88		88
89	/** Word to port	89	/** Word to port
90	*	90	*
91	* Output word to port	91	* Output word to port
92	*	92	*
93	* @param port Port to write to	93	* @param port Port to write to
94	* @param val Value to write	94	* @param val Value to write
95	*/	95	*/
96	static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }	96	static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
97		97
98	/** Double word to port	98	/** Double word to port
99	*	99	*
100	* Output double word to port	100	* Output double word to port
101	*	101	*
102	* @param port Port to write to	102	* @param port Port to write to
103	* @param val Value to write	103	* @param val Value to write
104	*/	104	*/
105	static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }	105	static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
106		106
107	/** Byte from port	107	/** Byte from port
108	*	108	*
109	* Get byte from port	109	* Get byte from port
110	*	110	*
111	* @param port Port to read from	111	* @param port Port to read from
112	* @return Value read	112	* @return Value read
113	*/	113	*/
114	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	114	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
115		115
116	/** Word from port	116	/** Word from port
117	*	117	*
118	* Get word from port	118	* Get word from port
119	*	119	*
120	* @param port Port to read from	120	* @param port Port to read from
121	* @return Value read	121	* @return Value read
122	*/	122	*/
123	static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }	123	static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
124		124
125	/** Double word from port	125	/** Double word from port
126	*	126	*
127	* Get double word from port	127	* Get double word from port
128	*	128	*
129	* @param port Port to read from	129	* @param port Port to read from
130	* @return Value read	130	* @return Value read
131	*/	131	*/
132	static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }	132	static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
133		133
134	/** Set priority level low	134	/** Enable interrupts.
135	*	135	*
136	* Enable interrupts and return previous	136	* Enable interrupts and return previous
137	* value of EFLAGS.	137	* value of EFLAGS.
-		138	*
-		139	* @return Old interrupt priority level.
138	*/	140	*/
139	static inline pri_t cpu_priority_low(void) {	141	static inline ipl_t interrupts_enable(void) {
140	pri_t v;	142	ipl_t v;
141	__asm__ volatile (	143	__asm__ volatile (
142	"pushf\n\t"	144	"pushf\n\t"
143	"popl %0\n\t"	145	"popl %0\n\t"
144	"sti\n"	146	"sti\n"
145	: "=r" (v)	147	: "=r" (v)
146	);	148	);
147	return v;	149	return v;
148	}	150	}
149		151
150	/** Set priority level high	152	/** Disable interrupts.
151	*	153	*
152	* Disable interrupts and return previous	154	* Disable interrupts and return previous
153	* value of EFLAGS.	155	* value of EFLAGS.
-		156	*
-		157	* @return Old interrupt priority level.
154	*/	158	*/
155	static inline pri_t cpu_priority_high(void) {	159	static inline ipl_t interrupts_disable(void) {
156	pri_t v;	160	ipl_t v;
157	__asm__ volatile (	161	__asm__ volatile (
158	"pushf\n\t"	162	"pushf\n\t"
159	"popl %0\n\t"	163	"popl %0\n\t"
160	"cli\n"	164	"cli\n"
161	: "=r" (v)	165	: "=r" (v)
162	);	166	);
163	return v;	167	return v;
164	}	168	}
165		169
166	/** Restore priority level	170	/** Restore interrupt priority level.
167	*	171	*
168	* Restore EFLAGS.	172	* Restore EFLAGS.
-		173	*
-		174	* @param ipl Saved interrupt priority level.
169	*/	175	*/
170	static inline void cpu_priority_restore(pri_t pri) {	176	static inline void interrupts_restore(ipl_t ipl) {
171	__asm__ volatile (	177	__asm__ volatile (
172	"pushl %0\n\t"	178	"pushl %0\n\t"
173	"popf\n"	179	"popf\n"
174	: : "r" (pri)	180	: : "r" (ipl)
175	);	181	);
176	}	182	}
177		183
178	/** Return raw priority level	184	/** Return interrupt priority level.
179	*	185	*
180	* Return EFLAFS.	186	* @return EFLAFS.
181	*/	187	*/
182	static inline pri_t cpu_priority_read(void) {	188	static inline ipl_t interrupts_read(void) {
183	pri_t v;	189	ipl_t v;
184	__asm__ volatile (	190	__asm__ volatile (
185	"pushf\n\t"	191	"pushf\n\t"
186	"popl %0\n"	192	"popl %0\n"
187	: "=r" (v)	193	: "=r" (v)
188	);	194	);
189	return v;	195	return v;
190	}	196	}
191		197
192	/** Return base address of current stack	198	/** Return base address of current stack
193	*	199	*
194	* Return the base address of the current stack.	200	* Return the base address of the current stack.
195	* The stack is assumed to be STACK_SIZE bytes long.	201	* The stack is assumed to be STACK_SIZE bytes long.
196	* The stack must start on page boundary.	202	* The stack must start on page boundary.
197	*/	203	*/
198	static inline __address get_stack_base(void)	204	static inline __address get_stack_base(void)
199	{	205	{
200	__address v;	206	__address v;
201		207
202	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));	208	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
203		209
204	return v;	210	return v;
205	}	211	}
206		212
207	static inline __u64 rdtsc(void)	213	static inline __u64 rdtsc(void)
208	{	214	{
209	__u64 v;	215	__u64 v;
210		216
211	__asm__ volatile("rdtsc\n" : "=A" (v));	217	__asm__ volatile("rdtsc\n" : "=A" (v));
212		218
213	return v;	219	return v;
214	}	220	}
215		221
216	#endif	222	#endif
217		223

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(root)/kernel/trunk/arch/ia32/include/asm.h @ 1780 – Rev 393 → 413