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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * Copyright (C) 2005 Sergey Bondari |
3 | * Copyright (C) 2005 Sergey Bondari |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | #ifndef __ia32_ASM_H__ |
30 | #ifndef __ia32_ASM_H__ |
31 | #define __ia32_ASM_H__ |
31 | #define __ia32_ASM_H__ |
32 | 32 | ||
33 | #include <arch/types.h> |
33 | #include <arch/types.h> |
34 | #include <config.h> |
34 | #include <config.h> |
35 | 35 | ||
36 | extern __u32 interrupt_handler_size; |
36 | extern __u32 interrupt_handler_size; |
37 | 37 | ||
38 | extern void paging_on(void); |
38 | extern void paging_on(void); |
39 | 39 | ||
40 | extern void interrupt_handlers(void); |
40 | extern void interrupt_handlers(void); |
41 | 41 | ||
42 | extern void enable_l_apic_in_msr(void); |
42 | extern void enable_l_apic_in_msr(void); |
43 | 43 | ||
44 | 44 | ||
45 | extern void asm_delay_loop(__u32 t); |
45 | extern void asm_delay_loop(__u32 t); |
46 | extern void asm_fake_loop(__u32 t); |
46 | extern void asm_fake_loop(__u32 t); |
47 | 47 | ||
48 | 48 | ||
49 | /** Halt CPU |
49 | /** Halt CPU |
50 | * |
50 | * |
51 | * Halt the current CPU until interrupt event. |
51 | * Halt the current CPU until interrupt event. |
52 | */ |
52 | */ |
53 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
53 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
54 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
54 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
55 | 55 | ||
56 | /** Read CR2 |
56 | #define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \ |
57 | * |
57 | { \ |
58 | * Return value in CR2 |
58 | __native res; \ |
59 | * |
- | |
- | 59 | __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
|
60 | * @return Value read. |
60 | return res; \ |
61 | */ |
61 | } |
62 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; } |
- | |
63 | 62 | ||
64 | /** Write CR3 |
- | |
65 | * |
- | |
66 | * Write value to CR3. |
63 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \ |
67 | * |
64 | { \ |
68 | * @param v Value to be written. |
65 | __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
69 | */ |
66 | } |
70 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
- | |
71 | 67 | ||
- | 68 | GEN_READ_REG(cr0); |
|
- | 69 | GEN_READ_REG(cr2); |
|
72 | /** Read CR3 |
70 | GEN_READ_REG(cr3); |
- | 71 | GEN_WRITE_REG(cr3); |
|
73 | * |
72 | |
- | 73 | GEN_READ_REG(dr0); |
|
- | 74 | GEN_READ_REG(dr1); |
|
- | 75 | GEN_READ_REG(dr2); |
|
- | 76 | GEN_READ_REG(dr3); |
|
- | 77 | GEN_READ_REG(dr6); |
|
74 | * Return value in CR3 |
78 | GEN_READ_REG(dr7); |
75 | * |
79 | |
- | 80 | GEN_WRITE_REG(dr0); |
|
76 | * @return Value read. |
81 | GEN_WRITE_REG(dr1); |
77 | */ |
82 | GEN_WRITE_REG(dr2); |
78 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; } |
83 | GEN_WRITE_REG(dr3); |
- | 84 | GEN_WRITE_REG(dr6); |
|
- | 85 | GEN_WRITE_REG(dr7); |
|
79 | 86 | ||
80 | /** Byte to port |
87 | /** Byte to port |
81 | * |
88 | * |
82 | * Output byte to port |
89 | * Output byte to port |
83 | * |
90 | * |
84 | * @param port Port to write to |
91 | * @param port Port to write to |
85 | * @param val Value to write |
92 | * @param val Value to write |
86 | */ |
93 | */ |
87 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
94 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
88 | 95 | ||
89 | /** Word to port |
96 | /** Word to port |
90 | * |
97 | * |
91 | * Output word to port |
98 | * Output word to port |
92 | * |
99 | * |
93 | * @param port Port to write to |
100 | * @param port Port to write to |
94 | * @param val Value to write |
101 | * @param val Value to write |
95 | */ |
102 | */ |
96 | static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
103 | static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
97 | 104 | ||
98 | /** Double word to port |
105 | /** Double word to port |
99 | * |
106 | * |
100 | * Output double word to port |
107 | * Output double word to port |
101 | * |
108 | * |
102 | * @param port Port to write to |
109 | * @param port Port to write to |
103 | * @param val Value to write |
110 | * @param val Value to write |
104 | */ |
111 | */ |
105 | static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
112 | static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
106 | 113 | ||
107 | /** Byte from port |
114 | /** Byte from port |
108 | * |
115 | * |
109 | * Get byte from port |
116 | * Get byte from port |
110 | * |
117 | * |
111 | * @param port Port to read from |
118 | * @param port Port to read from |
112 | * @return Value read |
119 | * @return Value read |
113 | */ |
120 | */ |
114 | static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
121 | static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
115 | 122 | ||
116 | /** Word from port |
123 | /** Word from port |
117 | * |
124 | * |
118 | * Get word from port |
125 | * Get word from port |
119 | * |
126 | * |
120 | * @param port Port to read from |
127 | * @param port Port to read from |
121 | * @return Value read |
128 | * @return Value read |
122 | */ |
129 | */ |
123 | static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
130 | static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
124 | 131 | ||
125 | /** Double word from port |
132 | /** Double word from port |
126 | * |
133 | * |
127 | * Get double word from port |
134 | * Get double word from port |
128 | * |
135 | * |
129 | * @param port Port to read from |
136 | * @param port Port to read from |
130 | * @return Value read |
137 | * @return Value read |
131 | */ |
138 | */ |
132 | static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
139 | static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
133 | 140 | ||
134 | /** Enable interrupts. |
141 | /** Enable interrupts. |
135 | * |
142 | * |
136 | * Enable interrupts and return previous |
143 | * Enable interrupts and return previous |
137 | * value of EFLAGS. |
144 | * value of EFLAGS. |
138 | * |
145 | * |
139 | * @return Old interrupt priority level. |
146 | * @return Old interrupt priority level. |
140 | */ |
147 | */ |
141 | static inline ipl_t interrupts_enable(void) |
148 | static inline ipl_t interrupts_enable(void) |
142 | { |
149 | { |
143 | ipl_t v; |
150 | ipl_t v; |
144 | __asm__ volatile ( |
151 | __asm__ volatile ( |
145 | "pushf\n\t" |
152 | "pushf\n\t" |
146 | "popl %0\n\t" |
153 | "popl %0\n\t" |
147 | "sti\n" |
154 | "sti\n" |
148 | : "=r" (v) |
155 | : "=r" (v) |
149 | ); |
156 | ); |
150 | return v; |
157 | return v; |
151 | } |
158 | } |
152 | 159 | ||
153 | /** Disable interrupts. |
160 | /** Disable interrupts. |
154 | * |
161 | * |
155 | * Disable interrupts and return previous |
162 | * Disable interrupts and return previous |
156 | * value of EFLAGS. |
163 | * value of EFLAGS. |
157 | * |
164 | * |
158 | * @return Old interrupt priority level. |
165 | * @return Old interrupt priority level. |
159 | */ |
166 | */ |
160 | static inline ipl_t interrupts_disable(void) |
167 | static inline ipl_t interrupts_disable(void) |
161 | { |
168 | { |
162 | ipl_t v; |
169 | ipl_t v; |
163 | __asm__ volatile ( |
170 | __asm__ volatile ( |
164 | "pushf\n\t" |
171 | "pushf\n\t" |
165 | "popl %0\n\t" |
172 | "popl %0\n\t" |
166 | "cli\n" |
173 | "cli\n" |
167 | : "=r" (v) |
174 | : "=r" (v) |
168 | ); |
175 | ); |
169 | return v; |
176 | return v; |
170 | } |
177 | } |
171 | 178 | ||
172 | /** Restore interrupt priority level. |
179 | /** Restore interrupt priority level. |
173 | * |
180 | * |
174 | * Restore EFLAGS. |
181 | * Restore EFLAGS. |
175 | * |
182 | * |
176 | * @param ipl Saved interrupt priority level. |
183 | * @param ipl Saved interrupt priority level. |
177 | */ |
184 | */ |
178 | static inline void interrupts_restore(ipl_t ipl) |
185 | static inline void interrupts_restore(ipl_t ipl) |
179 | { |
186 | { |
180 | __asm__ volatile ( |
187 | __asm__ volatile ( |
181 | "pushl %0\n\t" |
188 | "pushl %0\n\t" |
182 | "popf\n" |
189 | "popf\n" |
183 | : : "r" (ipl) |
190 | : : "r" (ipl) |
184 | ); |
191 | ); |
185 | } |
192 | } |
186 | 193 | ||
187 | /** Return interrupt priority level. |
194 | /** Return interrupt priority level. |
188 | * |
195 | * |
189 | * @return EFLAFS. |
196 | * @return EFLAFS. |
190 | */ |
197 | */ |
191 | static inline ipl_t interrupts_read(void) |
198 | static inline ipl_t interrupts_read(void) |
192 | { |
199 | { |
193 | ipl_t v; |
200 | ipl_t v; |
194 | __asm__ volatile ( |
201 | __asm__ volatile ( |
195 | "pushf\n\t" |
202 | "pushf\n\t" |
196 | "popl %0\n" |
203 | "popl %0\n" |
197 | : "=r" (v) |
204 | : "=r" (v) |
198 | ); |
205 | ); |
199 | return v; |
206 | return v; |
200 | } |
207 | } |
201 | 208 | ||
202 | /** Return base address of current stack |
209 | /** Return base address of current stack |
203 | * |
210 | * |
204 | * Return the base address of the current stack. |
211 | * Return the base address of the current stack. |
205 | * The stack is assumed to be STACK_SIZE bytes long. |
212 | * The stack is assumed to be STACK_SIZE bytes long. |
206 | * The stack must start on page boundary. |
213 | * The stack must start on page boundary. |
207 | */ |
214 | */ |
208 | static inline __address get_stack_base(void) |
215 | static inline __address get_stack_base(void) |
209 | { |
216 | { |
210 | __address v; |
217 | __address v; |
211 | 218 | ||
212 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
219 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
213 | 220 | ||
214 | return v; |
221 | return v; |
215 | } |
222 | } |
216 | 223 | ||
217 | static inline __u64 rdtsc(void) |
224 | static inline __u64 rdtsc(void) |
218 | { |
225 | { |
219 | __u64 v; |
226 | __u64 v; |
220 | 227 | ||
221 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
228 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
222 | 229 | ||
223 | return v; |
230 | return v; |
224 | } |
231 | } |
225 | 232 | ||
226 | /** Return current IP address */ |
233 | /** Return current IP address */ |
227 | static inline __address * get_ip() |
234 | static inline __address * get_ip() |
228 | { |
235 | { |
229 | __address *ip; |
236 | __address *ip; |
230 | 237 | ||
231 | __asm__ volatile ( |
238 | __asm__ volatile ( |
232 | "mov %%eip, %0" |
239 | "mov %%eip, %0" |
233 | : "=r" (ip) |
240 | : "=r" (ip) |
234 | ); |
241 | ); |
235 | return ip; |
242 | return ip; |
236 | } |
243 | } |
237 | 244 | ||
238 | /** Invalidate TLB Entry. |
245 | /** Invalidate TLB Entry. |
239 | * |
246 | * |
240 | * @param addr Address on a page whose TLB entry is to be invalidated. |
247 | * @param addr Address on a page whose TLB entry is to be invalidated. |
241 | */ |
248 | */ |
242 | static inline void invlpg(__address addr) |
249 | static inline void invlpg(__address addr) |
243 | { |
250 | { |
244 | __asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr)); |
251 | __asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr)); |
245 | } |
252 | } |
246 | 253 | ||
247 | #endif |
254 | #endif |
248 | 255 |