WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/pm.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/pm.h>
#include <arch/mm/page.h>
#include <arch/types.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <interrupt.h>
 
#include <config.h>
 
#include <memstr.h>
#include <mm/heap.h>
#include <debug.h>
 
/*
 * There is no segmentation in long mode so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 */
 
struct descriptor gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KTEXT 32-bit protected, for protected mode before long mode */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* TSS descriptor - set up will be completed later,
     * on AMD64 it is 64-bit - 2 items in table */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
 
struct idescriptor idt[IDT_ITEMS];
 
struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };
 
static struct tss tss;
struct tss *tss_p = NULL;
 
void gdt_tss_setbase(struct descriptor *d, __address base)
{
    struct tss_descriptor *td = (struct tss_descriptor *) d;
 
    td->base_0_15 = base & 0xffff;
    td->base_16_23 = ((base) >> 16) & 0xff;
    td->base_24_31 = ((base) >> 24) & 0xff;
    td->base_32_63 = ((base) >> 32);
}
 
void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
{
    struct tss_descriptor *td = (struct tss_descriptor *) d;
 
    td->limit_0_15 = limit & 0xffff;
    td->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(struct idescriptor *d, __address offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16 & 0xffff;
    d->offset_32_63 = offset >> 32;
}
 
void tss_initialize(struct tss *t)
{
    memsetb((__address) t, sizeof(struct tss), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    struct idescriptor *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 
        d->unused = 0;
        d->selector = gdtselector(KTEXT_DES);
 
        d->present = 1;
        d->type = AR_INTERRUPT; /* masking interrupt */
 
        if (i == VECTOR_SYSCALL) {
            /*
             * The syscall interrupt gate must be calleable from userland.
             */
            d->dpl |= PL_USER;
        }
       
        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
        exc_register(i, "undef", null_interrupt);
    }
    exc_register(13, "gp_fault", gp_fault);
    exc_register( 7, "nm_fault", nm_fault);
    exc_register(12, "ss_fault", ss_fault);
}
 
 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
static void clean_IOPL_NT_flags(void)
{
    asm
    (
        "pushfq;"
        "pop %%rax;"
        "and $~(0x7000),%%rax;"
        "pushq %%rax;"
        "popfq;"
        :
        :
        :"%rax"
    );
}
 
/* Clean AM(18) flag in CR0 register */
static void clean_AM_flag(void)
{
    asm
    (
        "mov %%cr0,%%rax;"
        "and $~(0x40000),%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
    );
}
 
void pm_init(void)
{
    struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
    struct tss_descriptor *tss_desc;
 
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */
 
    if (config.cpu_active == 1) {
        idt_init();
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    }
    else {
        tss_p = (struct tss *) malloc(sizeof(struct tss));
        if (!tss_p)
            panic("could not allocate TSS\n");
    }
 
    tss_initialize(tss_p);
 
    tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);
    tss_desc->present = 1;
    tss_desc->type = AR_TSS;
    tss_desc->dpl = PL_KERNEL;
   
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
    gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
 
    __asm__("lgdt %0" : : "m"(gdtr));
    __asm__("lidt %0" : : "m"(idtr));
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
    __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
   
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
    clean_AM_flag();          /* Disable alignment check */
}
 

Rev 534	Rev 576
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/pm.h>	29	#include <arch/pm.h>
30	#include <arch/mm/page.h>	30	#include <arch/mm/page.h>
31	#include <arch/types.h>	31	#include <arch/types.h>
32	#include <arch/interrupt.h>	32	#include <arch/interrupt.h>
33	#include <arch/asm.h>	33	#include <arch/asm.h>
-		34	#include <interrupt.h>
34		35
35	#include <config.h>	36	#include <config.h>
36		37
37	#include <memstr.h>	38	#include <memstr.h>
38	#include <mm/heap.h>	39	#include <mm/heap.h>
39	#include <debug.h>	40	#include <debug.h>
40		41
41	/*	42	/*
42	* There is no segmentation in long mode so we set up flat mode. In this	43	* There is no segmentation in long mode so we set up flat mode. In this
43	* mode, we use, for each privilege level, two segments spanning the	44	* mode, we use, for each privilege level, two segments spanning the
44	* whole memory. One is for code and one is for data.	45	* whole memory. One is for code and one is for data.
45	*/	46	*/
46		47
47	struct descriptor gdt[GDT_ITEMS] = {	48	struct descriptor gdt[GDT_ITEMS] = {
48	/* NULL descriptor */	49	/* NULL descriptor */
49	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	50	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
50	/* KTEXT descriptor */	51	/* KTEXT descriptor */
51	{ .limit_0_15 = 0xffff,	52	{ .limit_0_15 = 0xffff,
52	.base_0_15 = 0,	53	.base_0_15 = 0,
53	.base_16_23 = 0,	54	.base_16_23 = 0,
54	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,	55	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,
55	.limit_16_19 = 0xf,	56	.limit_16_19 = 0xf,
56	.available = 0,	57	.available = 0,
57	.longmode = 1,	58	.longmode = 1,
58	.special = 0,	59	.special = 0,
59	.granularity = 1,	60	.granularity = 1,
60	.base_24_31 = 0 },	61	.base_24_31 = 0 },
61	/* KDATA descriptor */	62	/* KDATA descriptor */
62	{ .limit_0_15 = 0xffff,	63	{ .limit_0_15 = 0xffff,
63	.base_0_15 = 0,	64	.base_0_15 = 0,
64	.base_16_23 = 0,	65	.base_16_23 = 0,
65	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,	66	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,
66	.limit_16_19 = 0xf,	67	.limit_16_19 = 0xf,
67	.available = 0,	68	.available = 0,
68	.longmode = 0,	69	.longmode = 0,
69	.special = 0,	70	.special = 0,
70	.granularity = 1,	71	.granularity = 1,
71	.base_24_31 = 0 },	72	.base_24_31 = 0 },
72	/* UTEXT descriptor */	73	/* UTEXT descriptor */
73	{ .limit_0_15 = 0xffff,	74	{ .limit_0_15 = 0xffff,
74	.base_0_15 = 0,	75	.base_0_15 = 0,
75	.base_16_23 = 0,	76	.base_16_23 = 0,
76	.access = AR_PRESENT \| AR_CODE \| DPL_USER,	77	.access = AR_PRESENT \| AR_CODE \| DPL_USER,
77	.limit_16_19 = 0xf,	78	.limit_16_19 = 0xf,
78	.available = 0,	79	.available = 0,
79	.longmode = 1,	80	.longmode = 1,
80	.special = 0,	81	.special = 0,
81	.granularity = 1,	82	.granularity = 1,
82	.base_24_31 = 0 },	83	.base_24_31 = 0 },
83	/* UDATA descriptor */	84	/* UDATA descriptor */
84	{ .limit_0_15 = 0xffff,	85	{ .limit_0_15 = 0xffff,
85	.base_0_15 = 0,	86	.base_0_15 = 0,
86	.base_16_23 = 0,	87	.base_16_23 = 0,
87	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,	88	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,
88	.limit_16_19 = 0xf,	89	.limit_16_19 = 0xf,
89	.available = 0,	90	.available = 0,
90	.longmode = 0,	91	.longmode = 0,
91	.special = 1,	92	.special = 1,
92	.granularity = 1,	93	.granularity = 1,
93	.base_24_31 = 0 },	94	.base_24_31 = 0 },
94	/* KTEXT 32-bit protected, for protected mode before long mode */	95	/* KTEXT 32-bit protected, for protected mode before long mode */
95	{ .limit_0_15 = 0xffff,	96	{ .limit_0_15 = 0xffff,
96	.base_0_15 = 0,	97	.base_0_15 = 0,
97	.base_16_23 = 0,	98	.base_16_23 = 0,
98	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,	99	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,
99	.limit_16_19 = 0xf,	100	.limit_16_19 = 0xf,
100	.available = 0,	101	.available = 0,
101	.longmode = 0,	102	.longmode = 0,
102	.special = 1,	103	.special = 1,
103	.granularity = 1,	104	.granularity = 1,
104	.base_24_31 = 0 },	105	.base_24_31 = 0 },
105	/* TSS descriptor - set up will be completed later,	106	/* TSS descriptor - set up will be completed later,
106	* on AMD64 it is 64-bit - 2 items in table */	107	* on AMD64 it is 64-bit - 2 items in table */
107	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	108	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
108	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }	109	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
109	};	110	};
110		111
111	struct idescriptor idt[IDT_ITEMS];	112	struct idescriptor idt[IDT_ITEMS];
112		113
113	struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };	114	struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
114	struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };	115	struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };
115		116
116	static struct tss tss;	117	static struct tss tss;
117	struct tss *tss_p = NULL;	118	struct tss *tss_p = NULL;
118		119
119	void gdt_tss_setbase(struct descriptor *d, __address base)	120	void gdt_tss_setbase(struct descriptor *d, __address base)
120	{	121	{
121	struct tss_descriptor td = (struct tss_descriptor ) d;	122	struct tss_descriptor td = (struct tss_descriptor ) d;
122		123
123	td->base_0_15 = base & 0xffff;	124	td->base_0_15 = base & 0xffff;
124	td->base_16_23 = ((base) >> 16) & 0xff;	125	td->base_16_23 = ((base) >> 16) & 0xff;
125	td->base_24_31 = ((base) >> 24) & 0xff;	126	td->base_24_31 = ((base) >> 24) & 0xff;
126	td->base_32_63 = ((base) >> 32);	127	td->base_32_63 = ((base) >> 32);
127	}	128	}
128		129
129	void gdt_tss_setlimit(struct descriptor *d, __u32 limit)	130	void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
130	{	131	{
131	struct tss_descriptor td = (struct tss_descriptor ) d;	132	struct tss_descriptor td = (struct tss_descriptor ) d;
132		133
133	td->limit_0_15 = limit & 0xffff;	134	td->limit_0_15 = limit & 0xffff;
134	td->limit_16_19 = (limit >> 16) & 0xf;	135	td->limit_16_19 = (limit >> 16) & 0xf;
135	}	136	}
136		137
137	void idt_setoffset(struct idescriptor *d, __address offset)	138	void idt_setoffset(struct idescriptor *d, __address offset)
138	{	139	{
139	/*	140	/*
140	* Offset is a linear address.	141	* Offset is a linear address.
141	*/	142	*/
142	d->offset_0_15 = offset & 0xffff;	143	d->offset_0_15 = offset & 0xffff;
143	d->offset_16_31 = offset >> 16 & 0xffff;	144	d->offset_16_31 = offset >> 16 & 0xffff;
144	d->offset_32_63 = offset >> 32;	145	d->offset_32_63 = offset >> 32;
145	}	146	}
146		147
147	void tss_initialize(struct tss *t)	148	void tss_initialize(struct tss *t)
148	{	149	{
149	memsetb((__address) t, sizeof(struct tss), 0);	150	memsetb((__address) t, sizeof(struct tss), 0);
150	}	151	}
151		152
152	/*	153	/*
153	* This function takes care of proper setup of IDT and IDTR.	154	* This function takes care of proper setup of IDT and IDTR.
154	*/	155	*/
155	void idt_init(void)	156	void idt_init(void)
156	{	157	{
157	struct idescriptor *d;	158	struct idescriptor *d;
158	int i;	159	int i;
159		160
160	for (i = 0; i < IDT_ITEMS; i++) {	161	for (i = 0; i < IDT_ITEMS; i++) {
161	d = &idt[i];	162	d = &idt[i];
162		163
163	d->unused = 0;	164	d->unused = 0;
164	d->selector = gdtselector(KTEXT_DES);	165	d->selector = gdtselector(KTEXT_DES);
165		166
166	d->present = 1;	167	d->present = 1;
167	d->type = AR_INTERRUPT; /* masking interrupt */	168	d->type = AR_INTERRUPT; /* masking interrupt */
168		169
169	if (i == VECTOR_SYSCALL) {	170	if (i == VECTOR_SYSCALL) {
170	/*	171	/*
171	* The syscall interrupt gate must be calleable from userland.	172	* The syscall interrupt gate must be calleable from userland.
172	*/	173	*/
173	d->dpl \|= PL_USER;	174	d->dpl \|= PL_USER;
174	}	175	}
175		176
176	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);	177	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
177	trap_register(i, null_interrupt);	178	exc_register(i, "undef", null_interrupt);
178	}	179	}
179	trap_register(13, gp_fault);	180	exc_register(13, "gp_fault", gp_fault);
180	trap_register( 7, nm_fault);	181	exc_register( 7, "nm_fault", nm_fault);
181	trap_register(12, ss_fault);	182	exc_register(12, "ss_fault", ss_fault);
182	}	183	}
183		184
184		185
185	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */	186	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
186	static void clean_IOPL_NT_flags(void)	187	static void clean_IOPL_NT_flags(void)
187	{	188	{
188	asm	189	asm
189	(	190	(
190	"pushfq;"	191	"pushfq;"
191	"pop %%rax;"	192	"pop %%rax;"
192	"and $~(0x7000),%%rax;"	193	"and $~(0x7000),%%rax;"
193	"pushq %%rax;"	194	"pushq %%rax;"
194	"popfq;"	195	"popfq;"
195	:	196	:
196	:	197	:
197	:"%rax"	198	:"%rax"
198	);	199	);
199	}	200	}
200		201
201	/* Clean AM(18) flag in CR0 register */	202	/* Clean AM(18) flag in CR0 register */
202	static void clean_AM_flag(void)	203	static void clean_AM_flag(void)
203	{	204	{
204	asm	205	asm
205	(	206	(
206	"mov %%cr0,%%rax;"	207	"mov %%cr0,%%rax;"
207	"and $~(0x40000),%%rax;"	208	"and $~(0x40000),%%rax;"
208	"mov %%rax,%%cr0;"	209	"mov %%rax,%%cr0;"
209	:	210	:
210	:	211	:
211	:"%rax"	212	:"%rax"
212	);	213	);
213	}	214	}
214		215
215	void pm_init(void)	216	void pm_init(void)
216	{	217	{
217	struct descriptor gdt_p = (struct descriptor ) gdtr.base;	218	struct descriptor gdt_p = (struct descriptor ) gdtr.base;
218	struct tss_descriptor *tss_desc;	219	struct tss_descriptor *tss_desc;
219		220
220	/*	221	/*
221	* Each CPU has its private GDT and TSS.	222	* Each CPU has its private GDT and TSS.
222	* All CPUs share one IDT.	223	* All CPUs share one IDT.
223	*/	224	*/
224		225
225	if (config.cpu_active == 1) {	226	if (config.cpu_active == 1) {
226	idt_init();	227	idt_init();
227	/*	228	/*
228	* NOTE: bootstrap CPU has statically allocated TSS, because	229	* NOTE: bootstrap CPU has statically allocated TSS, because
229	* the heap hasn't been initialized so far.	230	* the heap hasn't been initialized so far.
230	*/	231	*/
231	tss_p = &tss;	232	tss_p = &tss;
232	}	233	}
233	else {	234	else {
234	tss_p = (struct tss *) malloc(sizeof(struct tss));	235	tss_p = (struct tss *) malloc(sizeof(struct tss));
235	if (!tss_p)	236	if (!tss_p)
236	panic("could not allocate TSS\n");	237	panic("could not allocate TSS\n");
237	}	238	}
238		239
239	tss_initialize(tss_p);	240	tss_initialize(tss_p);
240		241
241	tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);	242	tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);
242	tss_desc->present = 1;	243	tss_desc->present = 1;
243	tss_desc->type = AR_TSS;	244	tss_desc->type = AR_TSS;
244	tss_desc->dpl = PL_KERNEL;	245	tss_desc->dpl = PL_KERNEL;
245		246
246	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);	247	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
247	gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);	248	gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
248		249
249	__asm__("lgdt %0" : : "m"(gdtr));	250	__asm__("lgdt %0" : : "m"(gdtr));
250	__asm__("lidt %0" : : "m"(idtr));	251	__asm__("lidt %0" : : "m"(idtr));
251	/*	252	/*
252	* As of this moment, the current CPU has its own GDT pointing	253	* As of this moment, the current CPU has its own GDT pointing
253	* to its own TSS. We just need to load the TR register.	254	* to its own TSS. We just need to load the TR register.
254	*/	255	*/
255	__asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));	256	__asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
256		257
257	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */	258	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */
258	clean_AM_flag(); /* Disable alignment check */	259	clean_AM_flag(); /* Disable alignment check */
259	}	260	}
260		261

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(root)/kernel/trunk/arch/amd64/src/pm.c – Rev 534 → 576