WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/pm.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * Copyright (C) 2005-2006 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/pm.h>
#include <arch/mm/page.h>
#include <arch/types.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <interrupt.h>
#include <mm/as.h>
 
#include <config.h>
 
#include <memstr.h>
#include <mm/slab.h>
#include <debug.h>
 
/*
 * There is no segmentation in long mode so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 */
 
descriptor_t gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KTEXT 32-bit protected, for protected mode before long mode */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* TSS descriptor - set up will be completed later,
     * on AMD64 it is 64-bit - 2 items in table */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
 
idescriptor_t idt[IDT_ITEMS];
 
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
 
static tss_t tss;
tss_t *tss_p = NULL;
 
void gdt_tss_setbase(descriptor_t *d, __address base)
{
    tss_descriptor_t *td = (tss_descriptor_t *) d;
 
    td->base_0_15 = base & 0xffff;
    td->base_16_23 = ((base) >> 16) & 0xff;
    td->base_24_31 = ((base) >> 24) & 0xff;
    td->base_32_63 = ((base) >> 32);
}
 
void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
{
    struct tss_descriptor *td = (tss_descriptor_t *) d;
 
    td->limit_0_15 = limit & 0xffff;
    td->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(idescriptor_t *d, __address offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16 & 0xffff;
    d->offset_32_63 = offset >> 32;
}
 
void tss_initialize(tss_t *t)
{
    memsetb((__address) t, sizeof(tss_t), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    idescriptor_t *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 
        d->unused = 0;
        d->selector = gdtselector(KTEXT_DES);
 
        d->present = 1;
        d->type = AR_INTERRUPT; /* masking interrupt */
 
        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
        exc_register(i, "undef", (iroutine)null_interrupt);
    }
 
    exc_register( 7, "nm_fault", nm_fault);
    exc_register(12, "ss_fault", ss_fault);
    exc_register(13, "gp_fault", gp_fault);
    exc_register(14, "ident_mapper", ident_page_fault);
}
 
/** Initialize segmentation - code/data/idt tables
 *
 */
void pm_init(void)
{
    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
    tss_descriptor_t *tss_desc;
 
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */
 
    if (config.cpu_active == 1) {
        idt_init();
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    }
    else {
        /* We are going to use malloc, which may return
         * non boot-mapped pointer, initialize the CR3 register
         * ahead of page_init */
        write_cr3((__address) AS_KERNEL->page_table);
 
        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
        if (!tss_p)
            panic("could not allocate TSS\n");
    }
 
    tss_initialize(tss_p);
 
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
    tss_desc->present = 1;
    tss_desc->type = AR_TSS;
    tss_desc->dpl = PL_KERNEL;
   
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
 
    gdtr_load(&gdtr);
    idtr_load(&idtr);
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
    tr_load(gdtselector(TSS_DES));
}
 

Rev 1251	Rev 1252
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* Copyright (C) 2005-2006 Ondrej Palkovsky	3	* Copyright (C) 2005-2006 Ondrej Palkovsky
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	#include <arch/pm.h>	30	#include <arch/pm.h>
31	#include <arch/mm/page.h>	31	#include <arch/mm/page.h>
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <arch/interrupt.h>	33	#include <arch/interrupt.h>
34	#include <arch/asm.h>	34	#include <arch/asm.h>
35	#include <interrupt.h>	35	#include <interrupt.h>
-		36	#include <mm/as.h>
36		37
37	#include <config.h>	38	#include <config.h>
38		39
39	#include <memstr.h>	40	#include <memstr.h>
40	#include <mm/slab.h>	41	#include <mm/slab.h>
41	#include <debug.h>	42	#include <debug.h>
42		43
43	/*	44	/*
44	* There is no segmentation in long mode so we set up flat mode. In this	45	* There is no segmentation in long mode so we set up flat mode. In this
45	* mode, we use, for each privilege level, two segments spanning the	46	* mode, we use, for each privilege level, two segments spanning the
46	* whole memory. One is for code and one is for data.	47	* whole memory. One is for code and one is for data.
47	*/	48	*/
48		49
49	descriptor_t gdt[GDT_ITEMS] = {	50	descriptor_t gdt[GDT_ITEMS] = {
50	/* NULL descriptor */	51	/* NULL descriptor */
51	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	52	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
52	/* KTEXT descriptor */	53	/* KTEXT descriptor */
53	{ .limit_0_15 = 0xffff,	54	{ .limit_0_15 = 0xffff,
54	.base_0_15 = 0,	55	.base_0_15 = 0,
55	.base_16_23 = 0,	56	.base_16_23 = 0,
56	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,	57	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,
57	.limit_16_19 = 0xf,	58	.limit_16_19 = 0xf,
58	.available = 0,	59	.available = 0,
59	.longmode = 1,	60	.longmode = 1,
60	.special = 0,	61	.special = 0,
61	.granularity = 1,	62	.granularity = 1,
62	.base_24_31 = 0 },	63	.base_24_31 = 0 },
63	/* KDATA descriptor */	64	/* KDATA descriptor */
64	{ .limit_0_15 = 0xffff,	65	{ .limit_0_15 = 0xffff,
65	.base_0_15 = 0,	66	.base_0_15 = 0,
66	.base_16_23 = 0,	67	.base_16_23 = 0,
67	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,	68	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,
68	.limit_16_19 = 0xf,	69	.limit_16_19 = 0xf,
69	.available = 0,	70	.available = 0,
70	.longmode = 0,	71	.longmode = 0,
71	.special = 0,	72	.special = 0,
72	.granularity = 1,	73	.granularity = 1,
73	.base_24_31 = 0 },	74	.base_24_31 = 0 },
74	/* UDATA descriptor */	75	/* UDATA descriptor */
75	{ .limit_0_15 = 0xffff,	76	{ .limit_0_15 = 0xffff,
76	.base_0_15 = 0,	77	.base_0_15 = 0,
77	.base_16_23 = 0,	78	.base_16_23 = 0,
78	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,	79	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,
79	.limit_16_19 = 0xf,	80	.limit_16_19 = 0xf,
80	.available = 0,	81	.available = 0,
81	.longmode = 0,	82	.longmode = 0,
82	.special = 1,	83	.special = 1,
83	.granularity = 1,	84	.granularity = 1,
84	.base_24_31 = 0 },	85	.base_24_31 = 0 },
85	/* UTEXT descriptor */	86	/* UTEXT descriptor */
86	{ .limit_0_15 = 0xffff,	87	{ .limit_0_15 = 0xffff,
87	.base_0_15 = 0,	88	.base_0_15 = 0,
88	.base_16_23 = 0,	89	.base_16_23 = 0,
89	.access = AR_PRESENT \| AR_CODE \| DPL_USER,	90	.access = AR_PRESENT \| AR_CODE \| DPL_USER,
90	.limit_16_19 = 0xf,	91	.limit_16_19 = 0xf,
91	.available = 0,	92	.available = 0,
92	.longmode = 1,	93	.longmode = 1,
93	.special = 0,	94	.special = 0,
94	.granularity = 1,	95	.granularity = 1,
95	.base_24_31 = 0 },	96	.base_24_31 = 0 },
96	/* KTEXT 32-bit protected, for protected mode before long mode */	97	/* KTEXT 32-bit protected, for protected mode before long mode */
97	{ .limit_0_15 = 0xffff,	98	{ .limit_0_15 = 0xffff,
98	.base_0_15 = 0,	99	.base_0_15 = 0,
99	.base_16_23 = 0,	100	.base_16_23 = 0,
100	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,	101	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,
101	.limit_16_19 = 0xf,	102	.limit_16_19 = 0xf,
102	.available = 0,	103	.available = 0,
103	.longmode = 0,	104	.longmode = 0,
104	.special = 1,	105	.special = 1,
105	.granularity = 1,	106	.granularity = 1,
106	.base_24_31 = 0 },	107	.base_24_31 = 0 },
107	/* TSS descriptor - set up will be completed later,	108	/* TSS descriptor - set up will be completed later,
108	* on AMD64 it is 64-bit - 2 items in table */	109	* on AMD64 it is 64-bit - 2 items in table */
109	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }	111	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
111	};	112	};
112		113
113	idescriptor_t idt[IDT_ITEMS];	114	idescriptor_t idt[IDT_ITEMS];
114		115
115	ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };	116	ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
116	ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };	117	ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
117		118
118	static tss_t tss;	119	static tss_t tss;
119	tss_t *tss_p = NULL;	120	tss_t *tss_p = NULL;
120		121
121	void gdt_tss_setbase(descriptor_t *d, __address base)	122	void gdt_tss_setbase(descriptor_t *d, __address base)
122	{	123	{
123	tss_descriptor_t td = (tss_descriptor_t ) d;	124	tss_descriptor_t td = (tss_descriptor_t ) d;
124		125
125	td->base_0_15 = base & 0xffff;	126	td->base_0_15 = base & 0xffff;
126	td->base_16_23 = ((base) >> 16) & 0xff;	127	td->base_16_23 = ((base) >> 16) & 0xff;
127	td->base_24_31 = ((base) >> 24) & 0xff;	128	td->base_24_31 = ((base) >> 24) & 0xff;
128	td->base_32_63 = ((base) >> 32);	129	td->base_32_63 = ((base) >> 32);
129	}	130	}
130		131
131	void gdt_tss_setlimit(descriptor_t *d, __u32 limit)	132	void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
132	{	133	{
133	struct tss_descriptor td = (tss_descriptor_t ) d;	134	struct tss_descriptor td = (tss_descriptor_t ) d;
134		135
135	td->limit_0_15 = limit & 0xffff;	136	td->limit_0_15 = limit & 0xffff;
136	td->limit_16_19 = (limit >> 16) & 0xf;	137	td->limit_16_19 = (limit >> 16) & 0xf;
137	}	138	}
138		139
139	void idt_setoffset(idescriptor_t *d, __address offset)	140	void idt_setoffset(idescriptor_t *d, __address offset)
140	{	141	{
141	/*	142	/*
142	* Offset is a linear address.	143	* Offset is a linear address.
143	*/	144	*/
144	d->offset_0_15 = offset & 0xffff;	145	d->offset_0_15 = offset & 0xffff;
145	d->offset_16_31 = offset >> 16 & 0xffff;	146	d->offset_16_31 = offset >> 16 & 0xffff;
146	d->offset_32_63 = offset >> 32;	147	d->offset_32_63 = offset >> 32;
147	}	148	}
148		149
149	void tss_initialize(tss_t *t)	150	void tss_initialize(tss_t *t)
150	{	151	{
151	memsetb((__address) t, sizeof(tss_t), 0);	152	memsetb((__address) t, sizeof(tss_t), 0);
152	}	153	}
153		154
154	/*	155	/*
155	* This function takes care of proper setup of IDT and IDTR.	156	* This function takes care of proper setup of IDT and IDTR.
156	*/	157	*/
157	void idt_init(void)	158	void idt_init(void)
158	{	159	{
159	idescriptor_t *d;	160	idescriptor_t *d;
160	int i;	161	int i;
161		162
162	for (i = 0; i < IDT_ITEMS; i++) {	163	for (i = 0; i < IDT_ITEMS; i++) {
163	d = &idt[i];	164	d = &idt[i];
164		165
165	d->unused = 0;	166	d->unused = 0;
166	d->selector = gdtselector(KTEXT_DES);	167	d->selector = gdtselector(KTEXT_DES);
167		168
168	d->present = 1;	169	d->present = 1;
169	d->type = AR_INTERRUPT; /* masking interrupt */	170	d->type = AR_INTERRUPT; /* masking interrupt */
170		171
171	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);	172	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
172	exc_register(i, "undef", (iroutine)null_interrupt);	173	exc_register(i, "undef", (iroutine)null_interrupt);
173	}	174	}
174		175
175	exc_register( 7, "nm_fault", nm_fault);	176	exc_register( 7, "nm_fault", nm_fault);
176	exc_register(12, "ss_fault", ss_fault);	177	exc_register(12, "ss_fault", ss_fault);
177	exc_register(13, "gp_fault", gp_fault);	178	exc_register(13, "gp_fault", gp_fault);
178	exc_register(14, "ident_mapper", ident_page_fault);	179	exc_register(14, "ident_mapper", ident_page_fault);
179	}	180	}
180		181
181	/** Initialize segmentation - code/data/idt tables	182	/** Initialize segmentation - code/data/idt tables
182	*	183	*
183	*/	184	*/
184	void pm_init(void)	185	void pm_init(void)
185	{	186	{
186	descriptor_t gdt_p = (struct descriptor ) gdtr.base;	187	descriptor_t gdt_p = (struct descriptor ) gdtr.base;
187	tss_descriptor_t *tss_desc;	188	tss_descriptor_t *tss_desc;
188		189
189	/*	190	/*
190	* Each CPU has its private GDT and TSS.	191	* Each CPU has its private GDT and TSS.
191	* All CPUs share one IDT.	192	* All CPUs share one IDT.
192	*/	193	*/
193		194
194	if (config.cpu_active == 1) {	195	if (config.cpu_active == 1) {
195	idt_init();	196	idt_init();
196	/*	197	/*
197	* NOTE: bootstrap CPU has statically allocated TSS, because	198	* NOTE: bootstrap CPU has statically allocated TSS, because
198	* the heap hasn't been initialized so far.	199	* the heap hasn't been initialized so far.
199	*/	200	*/
200	tss_p = &tss;	201	tss_p = &tss;
201	}	202	}
202	else {	203	else {
-		204	/* We are going to use malloc, which may return
-		205	* non boot-mapped pointer, initialize the CR3 register
-		206	* ahead of page_init */
-		207	write_cr3((__address) AS_KERNEL->page_table);
-		208
203	tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);	209	tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
204	if (!tss_p)	210	if (!tss_p)
205	panic("could not allocate TSS\n");	211	panic("could not allocate TSS\n");
206	}	212	}
207		213
208	tss_initialize(tss_p);	214	tss_initialize(tss_p);
209		215
210	tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);	216	tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
211	tss_desc->present = 1;	217	tss_desc->present = 1;
212	tss_desc->type = AR_TSS;	218	tss_desc->type = AR_TSS;
213	tss_desc->dpl = PL_KERNEL;	219	tss_desc->dpl = PL_KERNEL;
214		220
215	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);	221	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
216	gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);	222	gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
217		223
218	gdtr_load(&gdtr);	224	gdtr_load(&gdtr);
219	idtr_load(&idtr);	225	idtr_load(&idtr);
220	/*	226	/*
221	* As of this moment, the current CPU has its own GDT pointing	227	* As of this moment, the current CPU has its own GDT pointing
222	* to its own TSS. We just need to load the TR register.	228	* to its own TSS. We just need to load the TR register.
223	*/	229	*/
224	tr_load(gdtselector(TSS_DES));	230	tr_load(gdtselector(TSS_DES));
225	}	231	}
226		232

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/src/pm.c @ 1780 – Rev 1251 → 1252