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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/pm.h> |
29 | #include <arch/pm.h> |
30 | #include <arch/mm/page.h> |
30 | #include <arch/mm/page.h> |
31 | #include <arch/types.h> |
31 | #include <arch/types.h> |
- | 32 | #include <arch/interrupt.h> |
|
- | 33 | #include <arch/asm.h> |
|
32 | 34 | ||
- | 35 | #include <config.h> |
|
- | 36 | ||
- | 37 | #include <memstr.h> |
|
- | 38 | #include <mm/heap.h> |
|
- | 39 | #include <debug.h> |
|
33 | 40 | ||
34 | /* |
41 | /* |
35 | * There is no segmentation in long mode so we set up flat mode. In this |
42 | * There is no segmentation in long mode so we set up flat mode. In this |
36 | * mode, we use, for each privilege level, two segments spanning the |
43 | * mode, we use, for each privilege level, two segments spanning the |
37 | * whole memory. One is for code and one is for data. |
44 | * whole memory. One is for code and one is for data. |
38 | */ |
45 | */ |
39 | 46 | ||
40 | struct descriptor gdt[GDT_ITEMS] = { |
47 | struct descriptor gdt[GDT_ITEMS] = { |
41 | /* NULL descriptor */ |
48 | /* NULL descriptor */ |
42 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
49 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
43 | /* KTEXT descriptor */ |
50 | /* KTEXT descriptor */ |
44 | { .limit_0_15 = 0xffff, |
51 | { .limit_0_15 = 0xffff, |
45 | .base_0_15 = 0, |
52 | .base_0_15 = 0, |
46 | .base_16_23 = 0, |
53 | .base_16_23 = 0, |
47 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE , |
54 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE , |
48 | .limit_16_19 = 0xf, |
55 | .limit_16_19 = 0xf, |
49 | .available = 0, |
56 | .available = 0, |
50 | .longmode = 1, |
57 | .longmode = 1, |
51 | .special = 0, |
58 | .special = 0, |
52 | .granularity = 1, |
59 | .granularity = 1, |
53 | .base_24_31 = 0 }, |
60 | .base_24_31 = 0 }, |
54 | /* KDATA descriptor */ |
61 | /* KDATA descriptor */ |
55 | { .limit_0_15 = 0xffff, |
62 | { .limit_0_15 = 0xffff, |
56 | .base_0_15 = 0, |
63 | .base_0_15 = 0, |
57 | .base_16_23 = 0, |
64 | .base_16_23 = 0, |
58 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, |
65 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, |
59 | .limit_16_19 = 0xf, |
66 | .limit_16_19 = 0xf, |
60 | .available = 0, |
67 | .available = 0, |
61 | .longmode = 0, |
68 | .longmode = 0, |
62 | .special = 0, |
69 | .special = 0, |
63 | .granularity = 1, |
70 | .granularity = 1, |
64 | .base_24_31 = 0 }, |
71 | .base_24_31 = 0 }, |
65 | /* UTEXT descriptor */ |
72 | /* UTEXT descriptor */ |
66 | { .limit_0_15 = 0xffff, |
73 | { .limit_0_15 = 0xffff, |
67 | .base_0_15 = 0, |
74 | .base_0_15 = 0, |
68 | .base_16_23 = 0, |
75 | .base_16_23 = 0, |
69 | .access = AR_PRESENT | AR_CODE | DPL_USER, |
76 | .access = AR_PRESENT | AR_CODE | DPL_USER, |
70 | .limit_16_19 = 0xf, |
77 | .limit_16_19 = 0xf, |
71 | .available = 0, |
78 | .available = 0, |
72 | .longmode = 1, |
79 | .longmode = 1, |
73 | .special = 0, |
80 | .special = 0, |
74 | .granularity = 0, |
81 | .granularity = 1, |
75 | .base_24_31 = 0 }, |
82 | .base_24_31 = 0 }, |
76 | /* UDATA descriptor */ |
83 | /* UDATA descriptor */ |
77 | { .limit_0_15 = 0xffff, |
84 | { .limit_0_15 = 0xffff, |
78 | .base_0_15 = 0, |
85 | .base_0_15 = 0, |
79 | .base_16_23 = 0, |
86 | .base_16_23 = 0, |
80 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, |
87 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, |
81 | .limit_16_19 = 0xf, |
88 | .limit_16_19 = 0xf, |
82 | .available = 0, |
89 | .available = 0, |
83 | .longmode = 0, |
90 | .longmode = 0, |
84 | .special = 1, |
91 | .special = 1, |
85 | .granularity = 1, |
92 | .granularity = 1, |
86 | .base_24_31 = 0 }, |
93 | .base_24_31 = 0 }, |
87 | /* KTEXT 16-bit protected */ |
94 | /* KTEXT 16-bit protected */ |
88 | { .limit_0_15 = 0xffff, |
95 | { .limit_0_15 = 0xffff, |
89 | .base_0_15 = 0, |
96 | .base_0_15 = 0, |
90 | .base_16_23 = 0, |
97 | .base_16_23 = 0, |
91 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, |
98 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, |
92 | .limit_16_19 = 0xf, |
99 | .limit_16_19 = 0xf, |
93 | .available = 0, |
100 | .available = 0, |
94 | .longmode = 0, |
101 | .longmode = 0, |
95 | .special = 0, |
102 | .special = 0, |
96 | .granularity = 1, |
103 | .granularity = 1, |
97 | .base_24_31 = 0 }, |
104 | .base_24_31 = 0 }, |
98 | /* TSS descriptor - set up will be completed later */ |
105 | /* TSS descriptor - set up will be completed later, |
- | 106 | * on AMD64 it is 64-bit - 2 items in table */ |
|
- | 107 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
|
99 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } |
108 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } |
100 | }; |
109 | }; |
101 | 110 | ||
- | 111 | struct ptr_16_64 gdtr = {.limit = sizeof(gdtr), .base= (__u64) &gdtr }; |
|
- | 112 | ||
102 | struct idescriptor idt[IDT_ITEMS]; |
113 | struct idescriptor idt[IDT_ITEMS]; |
103 | 114 | ||
104 | static struct tss tss; |
115 | static struct tss tss; |
105 | 116 | ||
106 | /* Does not compile correctly if it does not exist */ |
117 | /* TODO: Does not compile correctly if it does not exist ???? */ |
107 | int __attribute__ ((section ("K_DATA_START"))) __fake; |
118 | int __attribute__ ((section ("K_DATA_START"))) __fake; |
- | 119 | ||
- | 120 | void gdt_tss_setbase(struct descriptor *d, __address base) |
|
- | 121 | { |
|
- | 122 | struct tss_descriptor *td = (struct tss_descriptor *) d; |
|
- | 123 | ||
- | 124 | td->base_0_15 = base & 0xffff; |
|
- | 125 | td->base_16_23 = ((base) >> 16) & 0xff; |
|
- | 126 | td->base_24_31 = ((base) >> 24) & 0xff; |
|
- | 127 | td->base_32_63 = ((base) >> 32); |
|
- | 128 | } |
|
- | 129 | ||
- | 130 | void gdt_tss_setlimit(struct descriptor *d, __u32 limit) |
|
- | 131 | { |
|
- | 132 | struct tss_descriptor *td = (struct tss_descriptor *) d; |
|
- | 133 | ||
- | 134 | td->limit_0_15 = limit & 0xffff; |
|
- | 135 | td->limit_16_19 = (limit >> 16) & 0xf; |
|
- | 136 | } |
|
- | 137 | ||
- | 138 | void idt_setoffset(struct idescriptor *d, __address offset) |
|
- | 139 | { |
|
- | 140 | /* |
|
- | 141 | * Offset is a linear address. |
|
- | 142 | */ |
|
- | 143 | d->offset_0_15 = offset & 0xffff; |
|
- | 144 | d->offset_16_31 = offset >> 16 & 0xffff; |
|
- | 145 | d->offset_32_63 = offset >> 32; |
|
- | 146 | } |
|
- | 147 | ||
- | 148 | void tss_initialize(struct tss *t) |
|
- | 149 | { |
|
- | 150 | memsetb((__address) t, sizeof(struct tss), 0); |
|
- | 151 | } |
|
- | 152 | ||
- | 153 | /* |
|
- | 154 | * This function takes care of proper setup of IDT and IDTR. |
|
- | 155 | */ |
|
- | 156 | void idt_init(void) |
|
- | 157 | { |
|
- | 158 | struct idescriptor *d; |
|
- | 159 | int i; |
|
- | 160 | ||
- | 161 | for (i = 0; i < IDT_ITEMS; i++) { |
|
- | 162 | d = &idt[i]; |
|
- | 163 | ||
- | 164 | d->unused = 0; |
|
- | 165 | d->selector = idtselector(KTEXT_DES); |
|
- | 166 | ||
- | 167 | d->present = 1; |
|
- | 168 | d->type = AR_INTERRUPT; /* masking interrupt */ |
|
- | 169 | ||
- | 170 | if (i == VECTOR_SYSCALL) { |
|
- | 171 | /* |
|
- | 172 | * The syscall interrupt gate must be calleable from userland. |
|
- | 173 | */ |
|
- | 174 | d->dpl |= PL_USER; |
|
- | 175 | } |
|
- | 176 | ||
- | 177 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
|
- | 178 | trap_register(i, null_interrupt); |
|
- | 179 | } |
|
- | 180 | trap_register(13, gp_fault); |
|
- | 181 | trap_register( 7, nm_fault); |
|
- | 182 | trap_register(12, ss_fault); |
|
- | 183 | } |
|
- | 184 | ||
- | 185 | ||
- | 186 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
|
- | 187 | static void clean_IOPL_NT_flags(void) |
|
- | 188 | { |
|
- | 189 | asm |
|
- | 190 | ( |
|
- | 191 | "pushfq;" |
|
- | 192 | "pop %%rax;" |
|
- | 193 | "and $~(0x7000),%%rax;" |
|
- | 194 | "pushq %%rax;" |
|
- | 195 | "popfq;" |
|
- | 196 | : |
|
- | 197 | : |
|
- | 198 | :"%rax" |
|
- | 199 | ); |
|
- | 200 | } |
|
- | 201 | ||
- | 202 | /* Clean AM(18) flag in CR0 register */ |
|
- | 203 | static void clean_AM_flag(void) |
|
- | 204 | { |
|
- | 205 | asm |
|
- | 206 | ( |
|
- | 207 | "mov %%cr0,%%rax;" |
|
- | 208 | "and $~(0x40000),%%rax;" |
|
- | 209 | "mov %%rax,%%cr0;" |
|
- | 210 | : |
|
- | 211 | : |
|
- | 212 | :"%rax" |
|
- | 213 | ); |
|
- | 214 | } |
|
- | 215 | ||
- | 216 | void pm_init(void) |
|
- | 217 | { |
|
- | 218 | struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base); |
|
- | 219 | struct tss_descriptor *tss_d; |
|
- | 220 | ||
- | 221 | /* |
|
- | 222 | * Each CPU has its private GDT and TSS. |
|
- | 223 | * All CPUs share one IDT. |
|
- | 224 | */ |
|
- | 225 | ||
- | 226 | if (config.cpu_active == 1) { |
|
- | 227 | idt_init(); |
|
- | 228 | /* |
|
- | 229 | * NOTE: bootstrap CPU has statically allocated TSS, because |
|
- | 230 | * the heap hasn't been initialized so far. |
|
- | 231 | */ |
|
- | 232 | tss_p = &tss; |
|
- | 233 | } |
|
- | 234 | else { |
|
- | 235 | tss_p = (struct tss *) malloc(sizeof(struct tss)); |
|
- | 236 | if (!tss_p) |
|
- | 237 | panic("could not allocate TSS\n"); |
|
- | 238 | } |
|
- | 239 | ||
- | 240 | tss_initialize(tss_p); |
|
- | 241 | ||
- | 242 | tss_d = (struct tss_descriptor *) &gdt_p[TSS_DES]; |
|
- | 243 | tss_d[TSS_DES].present = 1; |
|
- | 244 | tss_d[TSS_DES].type = AR_TSS; |
|
- | 245 | tss_d[TSS_DES].dpl = PL_KERNEL; |
|
- | 246 | ||
- | 247 | gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
|
- | 248 | gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1); |
|
- | 249 | ||
- | 250 | /* |
|
- | 251 | * As of this moment, the current CPU has its own GDT pointing |
|
- | 252 | * to its own TSS. We just need to load the TR register. |
|
- | 253 | */ |
|
- | 254 | __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES))); |
|
- | 255 | ||
- | 256 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ |
|
- | 257 | clean_AM_flag(); /* Disable alignment check */ |
|
- | 258 | } |
|
108 | 259 |