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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Vana |
2 | * Copyright (C) 2005 Jakub Vana |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
- | 27 | */ |
|
- | 28 | ||
- | 29 | /** @addtogroup amd64 |
|
- | 30 | * @{ |
|
- | 31 | */ |
|
- | 32 | /** @file |
|
27 | * |
33 | * |
28 | */ |
34 | */ |
29 | 35 | ||
30 | #include <fpu_context.h> |
36 | #include <fpu_context.h> |
31 | #include <arch.h> |
37 | #include <arch.h> |
32 | #include <cpu.h> |
38 | #include <cpu.h> |
33 | 39 | ||
34 | /** Save FPU (mmx, sse) context using fxsave instruction */ |
40 | /** Save FPU (mmx, sse) context using fxsave instruction */ |
35 | void fpu_context_save(fpu_context_t *fctx) |
41 | void fpu_context_save(fpu_context_t *fctx) |
36 | { |
42 | { |
37 | __asm__ volatile ( |
43 | __asm__ volatile ( |
38 | "fxsave %0" |
44 | "fxsave %0" |
39 | : "=m"(*fctx) |
45 | : "=m"(*fctx) |
40 | ); |
46 | ); |
41 | } |
47 | } |
42 | 48 | ||
43 | /** Restore FPU (mmx,sse) context using fxrstor instruction */ |
49 | /** Restore FPU (mmx,sse) context using fxrstor instruction */ |
44 | void fpu_context_restore(fpu_context_t *fctx) |
50 | void fpu_context_restore(fpu_context_t *fctx) |
45 | { |
51 | { |
46 | __asm__ volatile ( |
52 | __asm__ volatile ( |
47 | "fxrstor %0" |
53 | "fxrstor %0" |
48 | : "=m"(*fctx) |
54 | : "=m"(*fctx) |
49 | ); |
55 | ); |
50 | } |
56 | } |
51 | 57 | ||
52 | void fpu_init() |
58 | void fpu_init() |
53 | { |
59 | { |
54 | /* TODO: Zero all SSE, MMX etc. registers */ |
60 | /* TODO: Zero all SSE, MMX etc. registers */ |
55 | __asm__ volatile ( |
61 | __asm__ volatile ( |
56 | "fninit;" |
62 | "fninit;" |
57 | ); |
63 | ); |
58 | } |
64 | } |
- | 65 | ||
- | 66 | /** @} |
|
- | 67 | */ |
|
- | 68 | ||
59 | 69 |