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/*
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/*
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <arch/cpuid.h>
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#include <arch/cpuid.h>
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#include <arch/pm.h>
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#include <arch/pm.h>
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#include <arch.h>
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#include <arch.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <print.h>
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#include <print.h>
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#include <typedefs.h>
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#include <typedefs.h>
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 37 
 
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/*
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/*
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 * Identification of CPUs.
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 * Identification of CPUs.
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 * Contains only non-MP-Specification specific SMP code.
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 * Contains only non-MP-Specification specific SMP code.
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 */
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 */
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#define AMD_CPUID_EBX   0x68747541
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#define AMD_CPUID_EBX   0x68747541
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#define AMD_CPUID_ECX   0x444d4163
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#define AMD_CPUID_ECX   0x444d4163
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#define AMD_CPUID_EDX   0x69746e65
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#define AMD_CPUID_EDX   0x69746e65
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#define INTEL_CPUID_EBX 0x756e6547
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#define INTEL_CPUID_EBX 0x756e6547
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#define INTEL_CPUID_ECX 0x6c65746e
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#define INTEL_CPUID_ECX 0x6c65746e
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#define INTEL_CPUID_EDX 0x49656e69
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#define INTEL_CPUID_EDX 0x49656e69
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 50 
 
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enum vendor {
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enum vendor {
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    VendorUnknown=0,
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    VendorUnknown=0,
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    VendorAMD,
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    VendorAMD,
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    VendorIntel
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    VendorIntel
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};
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};
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 56 
 
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static char *vendor_str[] = {
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static char *vendor_str[] = {
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    "Unknown Vendor",
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    "Unknown Vendor",
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    "AuthenticAMD",
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    "AuthenticAMD",
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    "GenuineIntel"
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    "GenuineIntel"
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};
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};
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 62 
 
- 
 
 63 
 
- 
 
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/** Setup flags on processor so that we can use the FPU
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 *
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 * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
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 67 
 * cr0.em = 0 -> we do not emulate coprocessor
- 
 
 68 
 * cr0.mp = 1 -> we do want lazy context switch
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 69 
 */
- 
 
 70 
void cpu_setup_fpu(void)
- 
 
 71 
{
- 
 
 72 
    __asm__ volatile (
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        "movq %%cr0, %%rax;"
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        "btsq $1, %%rax;" /* cr0.mp */
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        "btrq $2, %%rax;"  /* cr0.em */
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        "movq %%rax, %%cr0;"
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        "movq %%cr4, %%rax;"
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        "bts $9, %%rax;" /* cr4.osfxsr */
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        "movq %%rax, %%cr4;"
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        :
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        :
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        :"%rax"
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        );
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 85 
}
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 86 
 
- 
 
 87 
/** Set the TS flag to 1.
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 88 
 *
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 89 
 * If a thread accesses coprocessor, exception is run, which
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 90 
 * does a lazy fpu context switch.
- 
 
 91 
 *
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 92 
 */
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void set_TS_flag(void)
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void set_TS_flag(void)
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{
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{
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    __asm__ volatile (
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    __asm__ volatile (
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        "mov %%cr0,%%rax;"
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        "mov %%cr0,%%rax;"
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        "or $8,%%rax;"
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        "bts $3,%%rax;"
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        "mov %%rax,%%cr0;"
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        "mov %%rax,%%cr0;"
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        :
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        :
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        :
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        :
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        :"%rax"
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        :"%rax"
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        );
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        );
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}
 103 
}
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 104 
 
75 
void reset_TS_flag(void)
 105 
void reset_TS_flag(void)
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{
 106 
{
77 
    __asm__ volatile (
 107 
    __asm__ volatile (
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        "mov %%cr0,%%rax;"
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        "mov %%cr0,%%rax;"
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        "btc $4,%%rax;"
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        "btr $3,%%rax;"
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        "mov %%rax,%%cr0;"
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        "mov %%rax,%%cr0;"
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        :
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        :
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        :
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        :
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        :"%rax"
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        :"%rax"
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        ); 
 114 
        ); 
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}
 115 
}
86 
 
 116 
 
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void cpu_arch_init(void)
 117 
void cpu_arch_init(void)
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{
 118 
{
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    CPU->arch.tss = tss_p;
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    CPU->arch.tss = tss_p;
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    CPU->fpu_owner=NULL;
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    CPU->fpu_owner=NULL;
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}
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}
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 122 
 
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 123 
 
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void cpu_identify(void)
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void cpu_identify(void)
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{
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{
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    cpu_info_t info;
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    cpu_info_t info;
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    int i;
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    int i;
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    CPU->arch.vendor = VendorUnknown;
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    CPU->arch.vendor = VendorUnknown;
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    if (has_cpuid()) {
 130 
    if (has_cpuid()) {
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        cpuid(0, &info);
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        cpuid(0, &info);
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        /*
 133 
        /*
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         * Check for AMD processor.
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         * Check for AMD processor.
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         */
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         */
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        if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
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        if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
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            CPU->arch.vendor = VendorAMD;
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            CPU->arch.vendor = VendorAMD;
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        }
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        }
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 139 
 
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        /*
 140 
        /*
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         * Check for Intel processor.
 141 
         * Check for Intel processor.
112 
         */    
 142 
         */    
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        if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
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        if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
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            CPU->arch.vendor = VendorIntel;
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            CPU->arch.vendor = VendorIntel;
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        }
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        }
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        cpuid(1, &info);
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        cpuid(1, &info);
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        CPU->arch.family = (info.cpuid_eax>>8)&0xf;
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        CPU->arch.family = (info.cpuid_eax>>8)&0xf;
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        CPU->arch.model = (info.cpuid_eax>>4)&0xf;
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        CPU->arch.model = (info.cpuid_eax>>4)&0xf;
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        CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;                      
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        CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;                      
121 
    }
 151 
    }
122 
}
 152 
}
123 
 
 153 
 
124 
void cpu_print_report(cpu_t* m)
 154 
void cpu_print_report(cpu_t* m)
125 
{
 155 
{
126 
    printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
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    printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
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        m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
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        m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
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        m->frequency_mhz);
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        m->frequency_mhz);
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}
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}
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