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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup amd64cpu amd64 |
29 | /** @addtogroup amd64cpu |
30 | * @ingroup cpu |
- | |
31 | * @{ |
30 | * @{ |
32 | */ |
31 | */ |
33 | /** @file |
32 | /** @file |
34 | */ |
33 | */ |
35 | 34 | ||
36 | #include <arch/cpu.h> |
35 | #include <arch/cpu.h> |
37 | #include <arch/cpuid.h> |
36 | #include <arch/cpuid.h> |
38 | #include <arch/pm.h> |
37 | #include <arch/pm.h> |
39 | 38 | ||
40 | #include <arch.h> |
39 | #include <arch.h> |
41 | #include <arch/types.h> |
40 | #include <arch/types.h> |
42 | #include <print.h> |
41 | #include <print.h> |
43 | #include <typedefs.h> |
42 | #include <typedefs.h> |
44 | #include <fpu_context.h> |
43 | #include <fpu_context.h> |
45 | 44 | ||
46 | /* |
45 | /* |
47 | * Identification of CPUs. |
46 | * Identification of CPUs. |
48 | * Contains only non-MP-Specification specific SMP code. |
47 | * Contains only non-MP-Specification specific SMP code. |
49 | */ |
48 | */ |
50 | #define AMD_CPUID_EBX 0x68747541 |
49 | #define AMD_CPUID_EBX 0x68747541 |
51 | #define AMD_CPUID_ECX 0x444d4163 |
50 | #define AMD_CPUID_ECX 0x444d4163 |
52 | #define AMD_CPUID_EDX 0x69746e65 |
51 | #define AMD_CPUID_EDX 0x69746e65 |
53 | 52 | ||
54 | #define INTEL_CPUID_EBX 0x756e6547 |
53 | #define INTEL_CPUID_EBX 0x756e6547 |
55 | #define INTEL_CPUID_ECX 0x6c65746e |
54 | #define INTEL_CPUID_ECX 0x6c65746e |
56 | #define INTEL_CPUID_EDX 0x49656e69 |
55 | #define INTEL_CPUID_EDX 0x49656e69 |
57 | 56 | ||
58 | 57 | ||
59 | enum vendor { |
58 | enum vendor { |
60 | VendorUnknown=0, |
59 | VendorUnknown=0, |
61 | VendorAMD, |
60 | VendorAMD, |
62 | VendorIntel |
61 | VendorIntel |
63 | }; |
62 | }; |
64 | 63 | ||
65 | static char *vendor_str[] = { |
64 | static char *vendor_str[] = { |
66 | "Unknown Vendor", |
65 | "Unknown Vendor", |
67 | "AuthenticAMD", |
66 | "AuthenticAMD", |
68 | "GenuineIntel" |
67 | "GenuineIntel" |
69 | }; |
68 | }; |
70 | 69 | ||
71 | 70 | ||
72 | /** Setup flags on processor so that we can use the FPU |
71 | /** Setup flags on processor so that we can use the FPU |
73 | * |
72 | * |
74 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
73 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
75 | * cr0.em = 0 -> we do not emulate coprocessor |
74 | * cr0.em = 0 -> we do not emulate coprocessor |
76 | * cr0.mp = 1 -> we do want lazy context switch |
75 | * cr0.mp = 1 -> we do want lazy context switch |
77 | */ |
76 | */ |
78 | void cpu_setup_fpu(void) |
77 | void cpu_setup_fpu(void) |
79 | { |
78 | { |
80 | __asm__ volatile ( |
79 | __asm__ volatile ( |
81 | "movq %%cr0, %%rax;" |
80 | "movq %%cr0, %%rax;" |
82 | "btsq $1, %%rax;" /* cr0.mp */ |
81 | "btsq $1, %%rax;" /* cr0.mp */ |
83 | "btrq $2, %%rax;" /* cr0.em */ |
82 | "btrq $2, %%rax;" /* cr0.em */ |
84 | "movq %%rax, %%cr0;" |
83 | "movq %%rax, %%cr0;" |
85 | 84 | ||
86 | "movq %%cr4, %%rax;" |
85 | "movq %%cr4, %%rax;" |
87 | "bts $9, %%rax;" /* cr4.osfxsr */ |
86 | "bts $9, %%rax;" /* cr4.osfxsr */ |
88 | "movq %%rax, %%cr4;" |
87 | "movq %%rax, %%cr4;" |
89 | : |
88 | : |
90 | : |
89 | : |
91 | :"%rax" |
90 | :"%rax" |
92 | ); |
91 | ); |
93 | } |
92 | } |
94 | 93 | ||
95 | /** Set the TS flag to 1. |
94 | /** Set the TS flag to 1. |
96 | * |
95 | * |
97 | * If a thread accesses coprocessor, exception is run, which |
96 | * If a thread accesses coprocessor, exception is run, which |
98 | * does a lazy fpu context switch. |
97 | * does a lazy fpu context switch. |
99 | * |
98 | * |
100 | */ |
99 | */ |
101 | void fpu_disable(void) |
100 | void fpu_disable(void) |
102 | { |
101 | { |
103 | __asm__ volatile ( |
102 | __asm__ volatile ( |
104 | "mov %%cr0,%%rax;" |
103 | "mov %%cr0,%%rax;" |
105 | "bts $3,%%rax;" |
104 | "bts $3,%%rax;" |
106 | "mov %%rax,%%cr0;" |
105 | "mov %%rax,%%cr0;" |
107 | : |
106 | : |
108 | : |
107 | : |
109 | :"%rax" |
108 | :"%rax" |
110 | ); |
109 | ); |
111 | } |
110 | } |
112 | 111 | ||
113 | void fpu_enable(void) |
112 | void fpu_enable(void) |
114 | { |
113 | { |
115 | __asm__ volatile ( |
114 | __asm__ volatile ( |
116 | "mov %%cr0,%%rax;" |
115 | "mov %%cr0,%%rax;" |
117 | "btr $3,%%rax;" |
116 | "btr $3,%%rax;" |
118 | "mov %%rax,%%cr0;" |
117 | "mov %%rax,%%cr0;" |
119 | : |
118 | : |
120 | : |
119 | : |
121 | :"%rax" |
120 | :"%rax" |
122 | ); |
121 | ); |
123 | } |
122 | } |
124 | 123 | ||
125 | void cpu_arch_init(void) |
124 | void cpu_arch_init(void) |
126 | { |
125 | { |
127 | CPU->arch.tss = tss_p; |
126 | CPU->arch.tss = tss_p; |
128 | CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss); |
127 | CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss); |
129 | CPU->fpu_owner = NULL; |
128 | CPU->fpu_owner = NULL; |
130 | } |
129 | } |
131 | 130 | ||
132 | void cpu_identify(void) |
131 | void cpu_identify(void) |
133 | { |
132 | { |
134 | cpu_info_t info; |
133 | cpu_info_t info; |
135 | 134 | ||
136 | CPU->arch.vendor = VendorUnknown; |
135 | CPU->arch.vendor = VendorUnknown; |
137 | if (has_cpuid()) { |
136 | if (has_cpuid()) { |
138 | cpuid(0, &info); |
137 | cpuid(0, &info); |
139 | 138 | ||
140 | /* |
139 | /* |
141 | * Check for AMD processor. |
140 | * Check for AMD processor. |
142 | */ |
141 | */ |
143 | if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
142 | if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
144 | CPU->arch.vendor = VendorAMD; |
143 | CPU->arch.vendor = VendorAMD; |
145 | } |
144 | } |
146 | 145 | ||
147 | /* |
146 | /* |
148 | * Check for Intel processor. |
147 | * Check for Intel processor. |
149 | */ |
148 | */ |
150 | if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
149 | if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
151 | CPU->arch.vendor = VendorIntel; |
150 | CPU->arch.vendor = VendorIntel; |
152 | } |
151 | } |
153 | 152 | ||
154 | cpuid(1, &info); |
153 | cpuid(1, &info); |
155 | CPU->arch.family = (info.cpuid_eax>>8)&0xf; |
154 | CPU->arch.family = (info.cpuid_eax>>8)&0xf; |
156 | CPU->arch.model = (info.cpuid_eax>>4)&0xf; |
155 | CPU->arch.model = (info.cpuid_eax>>4)&0xf; |
157 | CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; |
156 | CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; |
158 | } |
157 | } |
159 | } |
158 | } |
160 | 159 | ||
161 | void cpu_print_report(cpu_t* m) |
160 | void cpu_print_report(cpu_t* m) |
162 | { |
161 | { |
163 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
162 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
164 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping, |
163 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping, |
165 | m->frequency_mhz); |
164 | m->frequency_mhz); |
166 | } |
165 | } |
167 | 166 | ||
168 | /** @} |
167 | /** @} |
169 | */ |
168 | */ |
170 | 169 | ||
171 | 170 |