Rev 532 | Go to most recent revision | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 532 | Rev 534 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/cpu.h> |
29 | #include <arch/cpu.h> |
30 | #include <arch/cpuid.h> |
30 | #include <arch/cpuid.h> |
31 | #include <arch/pm.h> |
31 | #include <arch/pm.h> |
32 | 32 | ||
33 | #include <arch.h> |
33 | #include <arch.h> |
34 | #include <arch/types.h> |
34 | #include <arch/types.h> |
35 | #include <print.h> |
35 | #include <print.h> |
36 | #include <typedefs.h> |
36 | #include <typedefs.h> |
37 | #include <fpu_context.h> |
37 | #include <fpu_context.h> |
38 | 38 | ||
39 | /* |
39 | /* |
40 | * Identification of CPUs. |
40 | * Identification of CPUs. |
41 | * Contains only non-MP-Specification specific SMP code. |
41 | * Contains only non-MP-Specification specific SMP code. |
42 | */ |
42 | */ |
43 | #define AMD_CPUID_EBX 0x68747541 |
43 | #define AMD_CPUID_EBX 0x68747541 |
44 | #define AMD_CPUID_ECX 0x444d4163 |
44 | #define AMD_CPUID_ECX 0x444d4163 |
45 | #define AMD_CPUID_EDX 0x69746e65 |
45 | #define AMD_CPUID_EDX 0x69746e65 |
46 | 46 | ||
47 | #define INTEL_CPUID_EBX 0x756e6547 |
47 | #define INTEL_CPUID_EBX 0x756e6547 |
48 | #define INTEL_CPUID_ECX 0x6c65746e |
48 | #define INTEL_CPUID_ECX 0x6c65746e |
49 | #define INTEL_CPUID_EDX 0x49656e69 |
49 | #define INTEL_CPUID_EDX 0x49656e69 |
50 | 50 | ||
51 | 51 | ||
52 | enum vendor { |
52 | enum vendor { |
53 | VendorUnknown=0, |
53 | VendorUnknown=0, |
54 | VendorAMD, |
54 | VendorAMD, |
55 | VendorIntel |
55 | VendorIntel |
56 | }; |
56 | }; |
57 | 57 | ||
58 | static char *vendor_str[] = { |
58 | static char *vendor_str[] = { |
59 | "Unknown Vendor", |
59 | "Unknown Vendor", |
60 | "AuthenticAMD", |
60 | "AuthenticAMD", |
61 | "GenuineIntel" |
61 | "GenuineIntel" |
62 | }; |
62 | }; |
63 | 63 | ||
64 | 64 | ||
65 | /** Setup flags on processor so that we can use the FPU |
65 | /** Setup flags on processor so that we can use the FPU |
66 | * |
66 | * |
67 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
67 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
68 | * cr0.em = 0 -> we do not emulate coprocessor |
68 | * cr0.em = 0 -> we do not emulate coprocessor |
69 | * cr0.mp = 1 -> we do want lazy context switch |
69 | * cr0.mp = 1 -> we do want lazy context switch |
70 | */ |
70 | */ |
71 | void cpu_setup_fpu(void) |
71 | void cpu_setup_fpu(void) |
72 | { |
72 | { |
73 | __asm__ volatile ( |
73 | __asm__ volatile ( |
74 | "movq %%cr0, %%rax;" |
74 | "movq %%cr0, %%rax;" |
75 | "btsq $1, %%rax;" /* cr0.mp */ |
75 | "btsq $1, %%rax;" /* cr0.mp */ |
76 | "btrq $2, %%rax;" /* cr0.em */ |
76 | "btrq $2, %%rax;" /* cr0.em */ |
77 | "movq %%rax, %%cr0;" |
77 | "movq %%rax, %%cr0;" |
78 | 78 | ||
79 | "movq %%cr4, %%rax;" |
79 | "movq %%cr4, %%rax;" |
80 | "bts $9, %%rax;" /* cr4.osfxsr */ |
80 | "bts $9, %%rax;" /* cr4.osfxsr */ |
81 | "movq %%rax, %%cr4;" |
81 | "movq %%rax, %%cr4;" |
82 | : |
82 | : |
83 | : |
83 | : |
84 | :"%rax" |
84 | :"%rax" |
85 | ); |
85 | ); |
86 | } |
86 | } |
87 | 87 | ||
88 | /** Set the TS flag to 1. |
88 | /** Set the TS flag to 1. |
89 | * |
89 | * |
90 | * If a thread accesses coprocessor, exception is run, which |
90 | * If a thread accesses coprocessor, exception is run, which |
91 | * does a lazy fpu context switch. |
91 | * does a lazy fpu context switch. |
92 | * |
92 | * |
93 | */ |
93 | */ |
94 | void fpu_disable(void) |
94 | void fpu_disable(void) |
95 | { |
95 | { |
96 | __asm__ volatile ( |
96 | __asm__ volatile ( |
97 | "mov %%cr0,%%rax;" |
97 | "mov %%cr0,%%rax;" |
98 | "bts $3,%%rax;" |
98 | "bts $3,%%rax;" |
99 | "mov %%rax,%%cr0;" |
99 | "mov %%rax,%%cr0;" |
100 | : |
100 | : |
101 | : |
101 | : |
102 | :"%rax" |
102 | :"%rax" |
103 | ); |
103 | ); |
104 | } |
104 | } |
105 | 105 | ||
106 | void fpu_enable(void) |
106 | void fpu_enable(void) |
107 | { |
107 | { |
108 | __asm__ volatile ( |
108 | __asm__ volatile ( |
109 | "mov %%cr0,%%rax;" |
109 | "mov %%cr0,%%rax;" |
110 | "btr $3,%%rax;" |
110 | "btr $3,%%rax;" |
111 | "mov %%rax,%%cr0;" |
111 | "mov %%rax,%%cr0;" |
112 | : |
112 | : |
113 | : |
113 | : |
114 | :"%rax" |
114 | :"%rax" |
115 | ); |
115 | ); |
116 | } |
116 | } |
117 | 117 | ||
118 | void cpu_arch_init(void) |
118 | void cpu_arch_init(void) |
119 | { |
119 | { |
120 | CPU->arch.tss = tss_p; |
120 | CPU->arch.tss = tss_p; |
121 | CPU->fpu_owner=NULL; |
121 | CPU->fpu_owner=NULL; |
122 | } |
122 | } |
123 | 123 | ||
124 | 124 | ||
125 | void cpu_identify(void) |
125 | void cpu_identify(void) |
126 | { |
126 | { |
127 | cpu_info_t info; |
127 | cpu_info_t info; |
128 | int i; |
128 | int i; |
129 | 129 | ||
130 | CPU->arch.vendor = VendorUnknown; |
130 | CPU->arch.vendor = VendorUnknown; |
131 | if (has_cpuid()) { |
131 | if (has_cpuid()) { |
132 | cpuid(0, &info); |
132 | cpuid(0, &info); |
133 | 133 | ||
134 | /* |
134 | /* |
135 | * Check for AMD processor. |
135 | * Check for AMD processor. |
136 | */ |
136 | */ |
137 | if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
137 | if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
138 | CPU->arch.vendor = VendorAMD; |
138 | CPU->arch.vendor = VendorAMD; |
139 | } |
139 | } |
140 | 140 | ||
141 | /* |
141 | /* |
142 | * Check for Intel processor. |
142 | * Check for Intel processor. |
143 | */ |
143 | */ |
144 | if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
144 | if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
145 | CPU->arch.vendor = VendorIntel; |
145 | CPU->arch.vendor = VendorIntel; |
146 | } |
146 | } |
147 | 147 | ||
148 | cpuid(1, &info); |
148 | cpuid(1, &info); |
149 | CPU->arch.family = (info.cpuid_eax>>8)&0xf; |
149 | CPU->arch.family = (info.cpuid_eax>>8)&0xf; |
150 | CPU->arch.model = (info.cpuid_eax>>4)&0xf; |
150 | CPU->arch.model = (info.cpuid_eax>>4)&0xf; |
151 | CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; |
151 | CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; |
152 | } |
152 | } |
153 | } |
153 | } |
154 | 154 | ||
155 | void cpu_print_report(cpu_t* m) |
155 | void cpu_print_report(cpu_t* m) |
156 | { |
156 | { |
157 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
157 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
158 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping, |
158 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping, |
159 | m->frequency_mhz); |
159 | m->frequency_mhz); |
160 | } |
160 | } |
161 | 161 |