WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/asm_utils.S


#
# Copyright (C) 2005 Ondrej Palkovsky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
 
#  Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
# and 1 means interrupt with error word
 
	
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
 
#include <arch/pm.h>
	
.text
.global interrupt_handlers
.global panic_printf
 
panic_printf:
	movq $halt, (%rsp)
	jmp printf
 
.global memcpy
memcpy:
	jmp _memcpy
	
.global cpuid
.global has_cpuid
.global rdtsc
.global read_efer_flag
.global set_efer_flag
	
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
## Determine CPUID support
#
# Return 0 in EAX if CPUID is not support, 1 if supported.
#
has_cpuid:
	pushfq			# store flags
	popq %rax		# read flags
	movq %rax,%rdx		# copy flags
	btcl $21,%edx		# swap the ID bit
	pushq %rdx
	popfq			# propagate the change into flags
	pushfq
	popq %rdx		# read flags	
	andl $(1<<21),%eax	# interested only in ID bit
	andl $(1<<21),%edx
	xorl %edx,%eax		# 0 if not supported, 1 if supported
	ret
 
cpuid:
	movq %rbx, %r10  # we have to preserve rbx across function calls
 
	movl %edi,%eax	# load the command into %eax
 
	cpuid	
	movl %eax,0(%rsi)
	movl %ebx,4(%rsi)
	movl %ecx,8(%rsi)
	movl %edx,12(%rsi)
 
	movq %r10, %rbx
	ret
 
rdtsc:
	xorq %rax,%rax
	rdtsc
	ret
 
set_efer_flag:
	movq $0xc0000080, %rcx
	rdmsr
	btsl %edi, %eax
	wrmsr
	ret
	
read_efer_flag:	
	movq $0xc0000080, %rcx
	rdmsr
	ret 		
 
# Push all general purpose registers on stack except %rbp, %rsp
.macro push_all_gpr
	pushq %rax 
	pushq %rbx
	pushq %rcx
	pushq %rdx
	pushq %rsi
	pushq %rdi
	pushq %r8
	pushq %r9
	pushq %r10
	pushq %r11
	pushq %r12
	pushq %r13
	pushq %r14
	pushq %r15
.endm
 
.macro pop_all_gpr
	popq %r15
	popq %r14
	popq %r13
	popq %r12
	popq %r11
	popq %r10
	popq %r9
	popq %r8
	popq %rdi
	popq %rsi
	popq %rdx
	popq %rcx
	popq %rbx
	popq %rax
.endm
	
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers setup data segment registers
# and call exc_dispatch().
#
.macro handler i n
	pushq %rbp
	movq %rsp,%rbp
	
	push_all_gpr
 
	movq $(\i),%rdi   # %rdi - first parameter
	movq %rbp, %rsi
	addq $8, %rsi     # %rsi - second parameter - original stack
	call exc_dispatch 	# exc_dispatch(i, stack)
 
# Test if this is interrupt with error word or not
	mov $\i,%cl;
	movl $1,%eax;
	test $0xe0,%cl;
	jnz 0f;
	and $0x1f,%cl;
	shl %cl,%eax;
	and $ERROR_WORD_INTERRUPT_LIST,%eax;
	jz 0f;
 
 
# Return with error word
	pop_all_gpr
	
	popq %rbp;
	addq $8,%rsp;    # Skip error word
	iretq
 
0:
# Return with no error word
	pop_all_gpr
	
	popq %rbp
	iretq
 
	.if (\n-\i)-1
	handler "(\i+1)",\n
	.endif
.endm
	
interrupt_handlers:
h_start:
	handler 0 IDT_ITEMS
h_end:
	
 
.data
.global interrupt_handler_size
 
interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
 

Rev 702	Rev 717
1	#	1	#
2	# Copyright (C) 2005 Ondrej Palkovsky	2	# Copyright (C) 2005 Ondrej Palkovsky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29		29
30	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word	30	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
31	# and 1 means interrupt with error word	31	# and 1 means interrupt with error word
32		32
33		33
34	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00	34	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
35		35
36	#include <arch/pm.h>	36	#include <arch/pm.h>
37		37
38	.text	38	.text
39	.global interrupt_handlers	39	.global interrupt_handlers
40	.global panic_printf	40	.global panic_printf
41		41
42	panic_printf:	42	panic_printf:
43	movq $halt, (%rsp)	43	movq $halt, (%rsp)
44	jmp printf	44	jmp printf
45		45
46	.global memcpy	46	.global memcpy
47	memcpy:	47	memcpy:
48	jmp _memcpy	48	jmp _memcpy
49		49
50	.global cpuid	50	.global cpuid
51	.global has_cpuid	51	.global has_cpuid
52	.global rdtsc	52	.global rdtsc
53	.global read_efer_flag	53	.global read_efer_flag
54	.global set_efer_flag	54	.global set_efer_flag
55		55
56		-
57	# THIS IS USERSPACE CODE	-
58	.global utext	-
59	utext:	-
60	0:	-
61	int $48	-
62	jmp 0b	-
63	# not reached	-
64	utext_end:	-
65		-
66	.data	-
67	.global utext_size	-
68	utext_size:	-
69	.long utext_end - utext	-
70		-
71		-
72	## Determine CPUID support	56	## Determine CPUID support
73	#	57	#
74	# Return 0 in EAX if CPUID is not support, 1 if supported.	58	# Return 0 in EAX if CPUID is not support, 1 if supported.
75	#	59	#
76	has_cpuid:	60	has_cpuid:
77	pushfq # store flags	61	pushfq # store flags
78	popq %rax # read flags	62	popq %rax # read flags
79	movq %rax,%rdx # copy flags	63	movq %rax,%rdx # copy flags
80	btcl $21,%edx # swap the ID bit	64	btcl $21,%edx # swap the ID bit
81	pushq %rdx	65	pushq %rdx
82	popfq # propagate the change into flags	66	popfq # propagate the change into flags
83	pushfq	67	pushfq
84	popq %rdx # read flags	68	popq %rdx # read flags
85	andl $(1<<21),%eax # interested only in ID bit	69	andl $(1<<21),%eax # interested only in ID bit
86	andl $(1<<21),%edx	70	andl $(1<<21),%edx
87	xorl %edx,%eax # 0 if not supported, 1 if supported	71	xorl %edx,%eax # 0 if not supported, 1 if supported
88	ret	72	ret
89		73
90	cpuid:	74	cpuid:
91	movq %rbx, %r10 # we have to preserve rbx across function calls	75	movq %rbx, %r10 # we have to preserve rbx across function calls
92		76
93	movl %edi,%eax # load the command into %eax	77	movl %edi,%eax # load the command into %eax
94		78
95	cpuid	79	cpuid
96	movl %eax,0(%rsi)	80	movl %eax,0(%rsi)
97	movl %ebx,4(%rsi)	81	movl %ebx,4(%rsi)
98	movl %ecx,8(%rsi)	82	movl %ecx,8(%rsi)
99	movl %edx,12(%rsi)	83	movl %edx,12(%rsi)
100		84
101	movq %r10, %rbx	85	movq %r10, %rbx
102	ret	86	ret
103		87
104	rdtsc:	88	rdtsc:
105	xorq %rax,%rax	89	xorq %rax,%rax
106	rdtsc	90	rdtsc
107	ret	91	ret
108		92
109	set_efer_flag:	93	set_efer_flag:
110	movq $0xc0000080, %rcx	94	movq $0xc0000080, %rcx
111	rdmsr	95	rdmsr
112	btsl %edi, %eax	96	btsl %edi, %eax
113	wrmsr	97	wrmsr
114	ret	98	ret
115		99
116	read_efer_flag:	100	read_efer_flag:
117	movq $0xc0000080, %rcx	101	movq $0xc0000080, %rcx
118	rdmsr	102	rdmsr
119	ret	103	ret
120		104
121	# Push all general purpose registers on stack except %rbp, %rsp	105	# Push all general purpose registers on stack except %rbp, %rsp
122	.macro push_all_gpr	106	.macro push_all_gpr
123	pushq %rax	107	pushq %rax
124	pushq %rbx	108	pushq %rbx
125	pushq %rcx	109	pushq %rcx
126	pushq %rdx	110	pushq %rdx
127	pushq %rsi	111	pushq %rsi
128	pushq %rdi	112	pushq %rdi
129	pushq %r8	113	pushq %r8
130	pushq %r9	114	pushq %r9
131	pushq %r10	115	pushq %r10
132	pushq %r11	116	pushq %r11
133	pushq %r12	117	pushq %r12
134	pushq %r13	118	pushq %r13
135	pushq %r14	119	pushq %r14
136	pushq %r15	120	pushq %r15
137	.endm	121	.endm
138		122
139	.macro pop_all_gpr	123	.macro pop_all_gpr
140	popq %r15	124	popq %r15
141	popq %r14	125	popq %r14
142	popq %r13	126	popq %r13
143	popq %r12	127	popq %r12
144	popq %r11	128	popq %r11
145	popq %r10	129	popq %r10
146	popq %r9	130	popq %r9
147	popq %r8	131	popq %r8
148	popq %rdi	132	popq %rdi
149	popq %rsi	133	popq %rsi
150	popq %rdx	134	popq %rdx
151	popq %rcx	135	popq %rcx
152	popq %rbx	136	popq %rbx
153	popq %rax	137	popq %rax
154	.endm	138	.endm
155		139
156	## Declare interrupt handlers	140	## Declare interrupt handlers
157	#	141	#
158	# Declare interrupt handlers for n interrupt	142	# Declare interrupt handlers for n interrupt
159	# vectors starting at vector i.	143	# vectors starting at vector i.
160	#	144	#
161	# The handlers setup data segment registers	145	# The handlers setup data segment registers
162	# and call exc_dispatch().	146	# and call exc_dispatch().
163	#	147	#
164	.macro handler i n	148	.macro handler i n
165	pushq %rbp	149	pushq %rbp
166	movq %rsp,%rbp	150	movq %rsp,%rbp
167		151
168	push_all_gpr	152	push_all_gpr
169		153
170	movq $(\i),%rdi # %rdi - first parameter	154	movq $(\i),%rdi # %rdi - first parameter
171	movq %rbp, %rsi	155	movq %rbp, %rsi
172	addq $8, %rsi # %rsi - second parameter - original stack	156	addq $8, %rsi # %rsi - second parameter - original stack
173	call exc_dispatch # exc_dispatch(i, stack)	157	call exc_dispatch # exc_dispatch(i, stack)
174		158
175	# Test if this is interrupt with error word or not	159	# Test if this is interrupt with error word or not
176	mov $\i,%cl;	160	mov $\i,%cl;
177	movl $1,%eax;	161	movl $1,%eax;
178	test $0xe0,%cl;	162	test $0xe0,%cl;
179	jnz 0f;	163	jnz 0f;
180	and $0x1f,%cl;	164	and $0x1f,%cl;
181	shl %cl,%eax;	165	shl %cl,%eax;
182	and $ERROR_WORD_INTERRUPT_LIST,%eax;	166	and $ERROR_WORD_INTERRUPT_LIST,%eax;
183	jz 0f;	167	jz 0f;
184		168
185		169
186	# Return with error word	170	# Return with error word
187	pop_all_gpr	171	pop_all_gpr
188		172
189	popq %rbp;	173	popq %rbp;
190	addq $8,%rsp; # Skip error word	174	addq $8,%rsp; # Skip error word
191	iretq	175	iretq
192		176
193	0:	177	0:
194	# Return with no error word	178	# Return with no error word
195	pop_all_gpr	179	pop_all_gpr
196		180
197	popq %rbp	181	popq %rbp
198	iretq	182	iretq
199		183
200	.if (\n-\i)-1	184	.if (\n-\i)-1
201	handler "(\i+1)",\n	185	handler "(\i+1)",\n
202	.endif	186	.endif
203	.endm	187	.endm
204		188
205	interrupt_handlers:	189	interrupt_handlers:
206	h_start:	190	h_start:
207	handler 0 IDT_ITEMS	191	handler 0 IDT_ITEMS
208	h_end:	192	h_end:
209		193
210		-
211	.data	194	.data
212	.global interrupt_handler_size	195	.global interrupt_handler_size
213		196
214	interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS	197	interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
215		198

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(root)/kernel/trunk/arch/amd64/src/asm_utils.S @ 983 – Rev 702 → 717