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1 | # |
1 | # |
2 | # Copyright (C) 2005 Ondrej Palkovsky |
2 | # Copyright (C) 2005 Ondrej Palkovsky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | 29 | ||
30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
31 | # and 1 means interrupt with error word |
31 | # and 1 means interrupt with error word |
32 | 32 | ||
33 | 33 | ||
34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
35 | 35 | ||
36 | #define __ASM__ |
36 | #define __ASM__ |
37 | #include <arch/pm.h> |
37 | #include <arch/pm.h> |
38 | 38 | ||
39 | .text |
39 | .text |
40 | .global interrupt_handlers |
40 | .global interrupt_handlers |
41 | .global panic_printf |
41 | .global panic_printf |
- | 42 | .global cpuid |
|
42 | 43 | ||
43 | panic_printf: |
44 | panic_printf: |
44 | movq $halt, (%rsp) |
45 | movq $halt, (%rsp) |
45 | jmp printf |
46 | jmp printf |
46 | 47 | ||
47 | .global has_cpuid |
48 | .global has_cpuid |
48 | .global rdtsc |
49 | .global rdtsc |
49 | - | ||
- | 50 | .global read_efer_flag |
|
- | 51 | .global set_efer_flag |
|
50 | 52 | ||
51 | ## Determine CPUID support |
53 | ## Determine CPUID support |
52 | # |
54 | # |
53 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
55 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
54 | # |
56 | # |
55 | has_cpuid: |
57 | has_cpuid: |
56 | pushq %rbx |
58 | pushq %rbx |
57 | 59 | ||
58 | pushfq # store flags |
60 | pushfq # store flags |
59 | popq %rax # read flags |
61 | popq %rax # read flags |
60 | movq %rax,%rbx # copy flags |
62 | movq %rax,%rbx # copy flags |
61 | btcl $21,%ebx # swap the ID bit |
63 | btcl $21,%ebx # swap the ID bit |
62 | pushq %rbx |
64 | pushq %rbx |
63 | popfq # propagate the change into flags |
65 | popfq # propagate the change into flags |
64 | pushfq |
66 | pushfq |
65 | popq %rbx # read flags |
67 | popq %rbx # read flags |
66 | andl $(1<<21),%eax # interested only in ID bit |
68 | andl $(1<<21),%eax # interested only in ID bit |
67 | andl $(1<<21),%ebx |
69 | andl $(1<<21),%ebx |
68 | xorl %ebx,%eax # 0 if not supported, 1 if supported |
70 | xorl %ebx,%eax # 0 if not supported, 1 if supported |
69 | 71 | ||
70 | popq %rbx |
72 | popq %rbx |
71 | ret |
73 | ret |
72 | 74 | ||
- | 75 | cpuid: |
|
- | 76 | movq %rbx, %r10 # we have to preserve rbx across function calls |
|
- | 77 | ||
- | 78 | movl %edi,%eax # load the command into %eax |
|
- | 79 | ||
- | 80 | cpuid |
|
- | 81 | movl %eax,0(%rsi) |
|
- | 82 | movl %ebx,4(%rsi) |
|
- | 83 | movl %ecx,8(%rsi) |
|
- | 84 | movl %edx,12(%rsi) |
|
- | 85 | ||
- | 86 | movq %r10, %rbx |
|
- | 87 | ret |
|
73 | 88 | ||
74 | rdtsc: |
89 | rdtsc: |
75 | xorq %rax,%rax |
90 | xorq %rax,%rax |
76 | rdtsc |
91 | rdtsc |
77 | ret |
92 | ret |
- | 93 | ||
- | 94 | set_efer_flag: |
|
- | 95 | movq $0xc0000080, %rcx |
|
- | 96 | rdmsr |
|
- | 97 | btsl %edi, %eax |
|
- | 98 | wrmsr |
|
- | 99 | ret |
|
78 | 100 | ||
- | 101 | read_efer_flag: |
|
- | 102 | movq $0xc0000080, %rcx |
|
- | 103 | rdmsr |
|
- | 104 | ret |
|
79 | 105 | ||
80 | # Push all general purpose registers on stack except %rbp, %rsp |
106 | # Push all general purpose registers on stack except %rbp, %rsp |
81 | .macro push_all_gpr |
107 | .macro push_all_gpr |
82 | pushq %rax |
108 | pushq %rax |
83 | pushq %rbx |
109 | pushq %rbx |
84 | pushq %rcx |
110 | pushq %rcx |
85 | pushq %rdx |
111 | pushq %rdx |
86 | pushq %rsi |
112 | pushq %rsi |
87 | pushq %rdi |
113 | pushq %rdi |
88 | pushq %r8 |
114 | pushq %r8 |
89 | pushq %r9 |
115 | pushq %r9 |
90 | pushq %r10 |
116 | pushq %r10 |
91 | pushq %r11 |
117 | pushq %r11 |
92 | pushq %r12 |
118 | pushq %r12 |
93 | pushq %r13 |
119 | pushq %r13 |
94 | pushq %r14 |
120 | pushq %r14 |
95 | pushq %r15 |
121 | pushq %r15 |
96 | .endm |
122 | .endm |
97 | 123 | ||
98 | .macro pop_all_gpr |
124 | .macro pop_all_gpr |
99 | popq %r15 |
125 | popq %r15 |
100 | popq %r14 |
126 | popq %r14 |
101 | popq %r13 |
127 | popq %r13 |
102 | popq %r12 |
128 | popq %r12 |
103 | popq %r11 |
129 | popq %r11 |
104 | popq %r10 |
130 | popq %r10 |
105 | popq %r9 |
131 | popq %r9 |
106 | popq %r8 |
132 | popq %r8 |
107 | popq %rdi |
133 | popq %rdi |
108 | popq %rsi |
134 | popq %rsi |
109 | popq %rdx |
135 | popq %rdx |
110 | popq %rcx |
136 | popq %rcx |
111 | popq %rbx |
137 | popq %rbx |
112 | popq %rax |
138 | popq %rax |
113 | .endm |
139 | .endm |
114 | 140 | ||
115 | ## Declare interrupt handlers |
141 | ## Declare interrupt handlers |
116 | # |
142 | # |
117 | # Declare interrupt handlers for n interrupt |
143 | # Declare interrupt handlers for n interrupt |
118 | # vectors starting at vector i. |
144 | # vectors starting at vector i. |
119 | # |
145 | # |
120 | # The handlers setup data segment registers |
146 | # The handlers setup data segment registers |
121 | # and call trap_dispatcher(). |
147 | # and call trap_dispatcher(). |
122 | # |
148 | # |
123 | .macro handler i n |
149 | .macro handler i n |
124 | pushq %rbp |
150 | pushq %rbp |
125 | movq %rsp,%rbp |
151 | movq %rsp,%rbp |
126 | 152 | ||
127 | push_all_gpr |
153 | push_all_gpr |
128 | 154 | ||
129 | # trap_dispatcher(i, stack) |
155 | # trap_dispatcher(i, stack) |
130 | movq $(\i),%rdi # %rdi - first parameter |
156 | movq $(\i),%rdi # %rdi - first parameter |
131 | movq %rbp, %rsi |
157 | movq %rbp, %rsi |
132 | addq $8, %rsi # %rsi - second parameter - original stack |
158 | addq $8, %rsi # %rsi - second parameter - original stack |
133 | call trap_dispatcher |
159 | call trap_dispatcher |
134 | 160 | ||
135 | # Test if this is interrupt with error word or not |
161 | # Test if this is interrupt with error word or not |
136 | mov $\i,%cl; |
162 | mov $\i,%cl; |
137 | movl $1,%eax; |
163 | movl $1,%eax; |
138 | test $0xe0,%cl; |
164 | test $0xe0,%cl; |
139 | jnz 0f; |
165 | jnz 0f; |
140 | and $0x1f,%cl; |
166 | and $0x1f,%cl; |
141 | shl %cl,%eax; |
167 | shl %cl,%eax; |
142 | and $ERROR_WORD_INTERRUPT_LIST,%eax; |
168 | and $ERROR_WORD_INTERRUPT_LIST,%eax; |
143 | jz 0f; |
169 | jz 0f; |
144 | 170 | ||
145 | 171 | ||
146 | # Return with error word |
172 | # Return with error word |
147 | pop_all_gpr |
173 | pop_all_gpr |
148 | 174 | ||
149 | popq %rbp; |
175 | popq %rbp; |
150 | add $8,%esp; # Skip error word |
176 | add $8,%esp; # Skip error word |
151 | iretq |
177 | iretq |
152 | 178 | ||
153 | 0: |
179 | 0: |
154 | # Return with no error word |
180 | # Return with no error word |
155 | pop_all_gpr |
181 | pop_all_gpr |
156 | 182 | ||
157 | popq %rbp |
183 | popq %rbp |
158 | iretq |
184 | iretq |
159 | 185 | ||
160 | .if (\n-\i)-1 |
186 | .if (\n-\i)-1 |
161 | handler "(\i+1)",\n |
187 | handler "(\i+1)",\n |
162 | .endif |
188 | .endif |
163 | .endm |
189 | .endm |
164 | 190 | ||
165 | interrupt_handlers: |
191 | interrupt_handlers: |
166 | h_start: |
192 | h_start: |
167 | handler 0 IDT_ITEMS |
193 | handler 0 IDT_ITEMS |
168 | # handler 64 128 |
194 | # handler 64 128 |
169 | # handler 128 192 |
195 | # handler 128 192 |
170 | # handler 192 256 |
196 | # handler 192 256 |
171 | h_end: |
197 | h_end: |
172 | 198 | ||
173 | 199 | ||
174 | .data |
200 | .data |
175 | .global interrupt_handler_size |
201 | .global interrupt_handler_size |
176 | 202 | ||
177 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
203 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
178 | 204 |