WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/asm_utils.S


#
# Copyright (C) 2005 Ondrej Palkovsky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#define IREGISTER_SPACE 120
 
#define IOFFSET_RAX 0x0
#define IOFFSET_RBX 0x8
#define IOFFSET_RCX 0x10
#define IOFFSET_RDX 0x18
#define IOFFSET_RSI 0x20
#define IOFFSET_RDI 0x28
#define IOFFSET_R8 0x30
#define IOFFSET_R9 0x38
#define IOFFSET_R10 0x40
#define IOFFSET_R11 0x48
#define IOFFSET_R12 0x50
#define IOFFSET_R13 0x58
#define IOFFSET_R14 0x60
#define IOFFSET_R15 0x68
#define IOFFSET_RBP 0x70
 
#  Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
# and 1 means interrupt with error word
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
 
#include <arch/pm.h>
#include <arch/mm/page.h>
	
.text
.global interrupt_handlers
.global syscall_entry
.global panic_printf
 
panic_printf:
	movq $halt, (%rsp)
	jmp printf
 
.global memcpy
memcpy:
	jmp _memcpy
	
.global cpuid
.global has_cpuid
.global rdtsc
.global read_efer_flag
.global set_efer_flag
	
## Determine CPUID support
#
# Return 0 in EAX if CPUID is not support, 1 if supported.
#
has_cpuid:
	pushfq			# store flags
	popq %rax		# read flags
	movq %rax,%rdx		# copy flags
	btcl $21,%edx		# swap the ID bit
	pushq %rdx
	popfq			# propagate the change into flags
	pushfq
	popq %rdx		# read flags	
	andl $(1<<21),%eax	# interested only in ID bit
	andl $(1<<21),%edx
	xorl %edx,%eax		# 0 if not supported, 1 if supported
	ret
 
cpuid:
	movq %rbx, %r10  # we have to preserve rbx across function calls
 
	movl %edi,%eax	# load the command into %eax
 
	cpuid	
	movl %eax,0(%rsi)
	movl %ebx,4(%rsi)
	movl %ecx,8(%rsi)
	movl %edx,12(%rsi)
 
	movq %r10, %rbx
	ret
 
rdtsc:
	xorq %rax,%rax
	rdtsc
	ret
 
set_efer_flag:
	movq $0xc0000080, %rcx
	rdmsr
	btsl %edi, %eax
	wrmsr
	ret
	
read_efer_flag:	
	movq $0xc0000080, %rcx
	rdmsr
	ret 		
 
# Push all general purpose registers on stack except %rbp, %rsp
.macro save_all_gpr
	movq %rax, IOFFSET_RAX(%rsp)
	movq %rcx, IOFFSET_RCX(%rsp)
	movq %rdx, IOFFSET_RDX(%rsp)
	movq %rsi, IOFFSET_RSI(%rsp)
	movq %rdi, IOFFSET_RDI(%rsp)
	movq %r8, IOFFSET_R8(%rsp)
	movq %r9, IOFFSET_R9(%rsp)
	movq %r10, IOFFSET_R10(%rsp)
	movq %r11, IOFFSET_R11(%rsp)
#ifdef CONFIG_DEBUG_ALLREGS	
	movq %rbx, IOFFSET_RBX(%rsp)
	movq %rbp, IOFFSET_RBP(%rsp)
	movq %r12, IOFFSET_R12(%rsp)
	movq %r13, IOFFSET_R13(%rsp)
	movq %r14, IOFFSET_R14(%rsp)
	movq %r15, IOFFSET_R15(%rsp)
#endif
.endm
 
.macro restore_all_gpr
	movq IOFFSET_RAX(%rsp), %rax
	movq IOFFSET_RCX(%rsp), %rcx
	movq IOFFSET_RDX(%rsp), %rdx
	movq IOFFSET_RSI(%rsp), %rsi
	movq IOFFSET_RDI(%rsp), %rdi
	movq IOFFSET_R8(%rsp), %r8
	movq IOFFSET_R9(%rsp), %r9
	movq IOFFSET_R10(%rsp), %r10
	movq IOFFSET_R11(%rsp), %r11
#ifdef CONFIG_DEBUG_ALLREGS	
	movq IOFFSET_RBX(%rsp), %rbx
	movq IOFFSET_RBP(%rsp), %rbp
	movq IOFFSET_R12(%rsp), %r12
	movq IOFFSET_R13(%rsp), %r13
	movq IOFFSET_R14(%rsp), %r14
	movq IOFFSET_R15(%rsp), %r15
#endif
.endm
 
#ifdef CONFIG_DEBUG_ALLREGS
# define INTERRUPT_ALIGN 256
#else
# define INTERRUPT_ALIGN 128
#endif
	
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers call exc_dispatch().
#
.macro handler i n
 
	/*
	 * Choose between version with error code and version without error code.
	 * Both versions have to be of the same size. amd64 assembly is, however,
	 * a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp
	 * can result in two instructions with different op-code lengths.
	 * Therefore we align the interrupt handlers.
	 */
 
	.iflt \i-32
		.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
			/*
			 * Version with error word.
			 */
			subq $IREGISTER_SPACE, %rsp
		.else
			/*
			 * Version without error word,
			 */
			subq $(IREGISTER_SPACE+8), %rsp
		.endif
	.else
		/*
		 * Version without error word,
		 */
		subq $(IREGISTER_SPACE+8), %rsp
	.endif	
 
	save_all_gpr
 
	movq $(\i), %rdi   	# %rdi - first parameter
	movq %rsp, %rsi   	# %rsi - pointer to istate
	call exc_dispatch 	# exc_dispatch(i, istate)
	
	restore_all_gpr
	# $8 = Skip error word
	addq $(IREGISTER_SPACE+8), %rsp
	iretq
 
	.align INTERRUPT_ALIGN
	.if (\n-\i)-1
	handler "(\i+1)",\n
	.endif
.endm
 
.align INTERRUPT_ALIGN
interrupt_handlers:
h_start:
	handler 0 IDT_ITEMS
h_end:
 
	
syscall_entry:
	# Switch to hidden gs	
	swapgs
	# %gs:0 now points to pointer to stack page
	mov %gs:0, %r10     # We have a ptr to stack page in r10
	addq $PAGE_SIZE-16, %r10 # We need some space to store old %sp
	
	movq %rsp, 0(%r10)  # Save old stack pointer to stack
	movq %r10, %rsp     # Change to new stack
	pushq %rcx          # Return address
	pushq %r11          # Save flags
 
	# Switch back to remain consistent
	swapgs 
 
	sti
	movq %r9, %rcx      # Exchange last parameter as a third
	
	cmp $2, %r8          # Is this SYS_INT_CONTROL
	je sys_int_ctrl
	
	call syscall_handler
sys_end:	
	cli                 # We will be touching stack pointer
		
	popq %r11
	popq %rcx
	movq 0(%rsp), %rsp
	sysretq
	
sys_int_ctrl:
	mov %rsp, %rsi      # Pointer to flags
	call ddi_int_control
	jmp sys_end
	
		
.data
.global interrupt_handler_size
 
interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS
 

Rev 1121	Rev 1212
1	#	1	#
2	# Copyright (C) 2005 Ondrej Palkovsky	2	# Copyright (C) 2005 Ondrej Palkovsky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#define IREGISTER_SPACE 120	29	#define IREGISTER_SPACE 120
30		30
31	#define IOFFSET_RAX 0x0	31	#define IOFFSET_RAX 0x0
32	#define IOFFSET_RBX 0x8	32	#define IOFFSET_RBX 0x8
33	#define IOFFSET_RCX 0x10	33	#define IOFFSET_RCX 0x10
34	#define IOFFSET_RDX 0x18	34	#define IOFFSET_RDX 0x18
35	#define IOFFSET_RSI 0x20	35	#define IOFFSET_RSI 0x20
36	#define IOFFSET_RDI 0x28	36	#define IOFFSET_RDI 0x28
37	#define IOFFSET_R8 0x30	37	#define IOFFSET_R8 0x30
38	#define IOFFSET_R9 0x38	38	#define IOFFSET_R9 0x38
39	#define IOFFSET_R10 0x40	39	#define IOFFSET_R10 0x40
40	#define IOFFSET_R11 0x48	40	#define IOFFSET_R11 0x48
41	#define IOFFSET_R12 0x50	41	#define IOFFSET_R12 0x50
42	#define IOFFSET_R13 0x58	42	#define IOFFSET_R13 0x58
43	#define IOFFSET_R14 0x60	43	#define IOFFSET_R14 0x60
44	#define IOFFSET_R15 0x68	44	#define IOFFSET_R15 0x68
45	#define IOFFSET_RBP 0x70	45	#define IOFFSET_RBP 0x70
46		46
47	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word	47	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
48	# and 1 means interrupt with error word	48	# and 1 means interrupt with error word
49	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00	49	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
50		50
51	#include <arch/pm.h>	51	#include <arch/pm.h>
52	#include <arch/mm/page.h>	52	#include <arch/mm/page.h>
53		53
54	.text	54	.text
55	.global interrupt_handlers	55	.global interrupt_handlers
56	.global syscall_entry	56	.global syscall_entry
57	.global panic_printf	57	.global panic_printf
58		58
59	panic_printf:	59	panic_printf:
60	movq $halt, (%rsp)	60	movq $halt, (%rsp)
61	jmp printf	61	jmp printf
62		62
63	.global memcpy	63	.global memcpy
64	memcpy:	64	memcpy:
65	jmp _memcpy	65	jmp _memcpy
66		66
67	.global cpuid	67	.global cpuid
68	.global has_cpuid	68	.global has_cpuid
69	.global rdtsc	69	.global rdtsc
70	.global read_efer_flag	70	.global read_efer_flag
71	.global set_efer_flag	71	.global set_efer_flag
72		72
73	## Determine CPUID support	73	## Determine CPUID support
74	#	74	#
75	# Return 0 in EAX if CPUID is not support, 1 if supported.	75	# Return 0 in EAX if CPUID is not support, 1 if supported.
76	#	76	#
77	has_cpuid:	77	has_cpuid:
78	pushfq # store flags	78	pushfq # store flags
79	popq %rax # read flags	79	popq %rax # read flags
80	movq %rax,%rdx # copy flags	80	movq %rax,%rdx # copy flags
81	btcl $21,%edx # swap the ID bit	81	btcl $21,%edx # swap the ID bit
82	pushq %rdx	82	pushq %rdx
83	popfq # propagate the change into flags	83	popfq # propagate the change into flags
84	pushfq	84	pushfq
85	popq %rdx # read flags	85	popq %rdx # read flags
86	andl $(1<<21),%eax # interested only in ID bit	86	andl $(1<<21),%eax # interested only in ID bit
87	andl $(1<<21),%edx	87	andl $(1<<21),%edx
88	xorl %edx,%eax # 0 if not supported, 1 if supported	88	xorl %edx,%eax # 0 if not supported, 1 if supported
89	ret	89	ret
90		90
91	cpuid:	91	cpuid:
92	movq %rbx, %r10 # we have to preserve rbx across function calls	92	movq %rbx, %r10 # we have to preserve rbx across function calls
93		93
94	movl %edi,%eax # load the command into %eax	94	movl %edi,%eax # load the command into %eax
95		95
96	cpuid	96	cpuid
97	movl %eax,0(%rsi)	97	movl %eax,0(%rsi)
98	movl %ebx,4(%rsi)	98	movl %ebx,4(%rsi)
99	movl %ecx,8(%rsi)	99	movl %ecx,8(%rsi)
100	movl %edx,12(%rsi)	100	movl %edx,12(%rsi)
101		101
102	movq %r10, %rbx	102	movq %r10, %rbx
103	ret	103	ret
104		104
105	rdtsc:	105	rdtsc:
106	xorq %rax,%rax	106	xorq %rax,%rax
107	rdtsc	107	rdtsc
108	ret	108	ret
109		109
110	set_efer_flag:	110	set_efer_flag:
111	movq $0xc0000080, %rcx	111	movq $0xc0000080, %rcx
112	rdmsr	112	rdmsr
113	btsl %edi, %eax	113	btsl %edi, %eax
114	wrmsr	114	wrmsr
115	ret	115	ret
116		116
117	read_efer_flag:	117	read_efer_flag:
118	movq $0xc0000080, %rcx	118	movq $0xc0000080, %rcx
119	rdmsr	119	rdmsr
120	ret	120	ret
121		121
122	# Push all general purpose registers on stack except %rbp, %rsp	122	# Push all general purpose registers on stack except %rbp, %rsp
123	.macro save_all_gpr	123	.macro save_all_gpr
124	movq %rax, IOFFSET_RAX(%rsp)	124	movq %rax, IOFFSET_RAX(%rsp)
125	movq %rcx, IOFFSET_RCX(%rsp)	125	movq %rcx, IOFFSET_RCX(%rsp)
126	movq %rdx, IOFFSET_RDX(%rsp)	126	movq %rdx, IOFFSET_RDX(%rsp)
127	movq %rsi, IOFFSET_RSI(%rsp)	127	movq %rsi, IOFFSET_RSI(%rsp)
128	movq %rdi, IOFFSET_RDI(%rsp)	128	movq %rdi, IOFFSET_RDI(%rsp)
129	movq %r8, IOFFSET_R8(%rsp)	129	movq %r8, IOFFSET_R8(%rsp)
130	movq %r9, IOFFSET_R9(%rsp)	130	movq %r9, IOFFSET_R9(%rsp)
131	movq %r10, IOFFSET_R10(%rsp)	131	movq %r10, IOFFSET_R10(%rsp)
132	movq %r11, IOFFSET_R11(%rsp)	132	movq %r11, IOFFSET_R11(%rsp)
133	#ifdef CONFIG_DEBUG_ALLREGS	133	#ifdef CONFIG_DEBUG_ALLREGS
134	movq %rbx, IOFFSET_RBX(%rsp)	134	movq %rbx, IOFFSET_RBX(%rsp)
135	movq %rbp, IOFFSET_RBP(%rsp)	135	movq %rbp, IOFFSET_RBP(%rsp)
136	movq %r12, IOFFSET_R12(%rsp)	136	movq %r12, IOFFSET_R12(%rsp)
137	movq %r13, IOFFSET_R13(%rsp)	137	movq %r13, IOFFSET_R13(%rsp)
138	movq %r14, IOFFSET_R14(%rsp)	138	movq %r14, IOFFSET_R14(%rsp)
139	movq %r15, IOFFSET_R15(%rsp)	139	movq %r15, IOFFSET_R15(%rsp)
140	#endif	140	#endif
141	.endm	141	.endm
142		142
143	.macro restore_all_gpr	143	.macro restore_all_gpr
144	movq IOFFSET_RAX(%rsp), %rax	144	movq IOFFSET_RAX(%rsp), %rax
145	movq IOFFSET_RCX(%rsp), %rcx	145	movq IOFFSET_RCX(%rsp), %rcx
146	movq IOFFSET_RDX(%rsp), %rdx	146	movq IOFFSET_RDX(%rsp), %rdx
147	movq IOFFSET_RSI(%rsp), %rsi	147	movq IOFFSET_RSI(%rsp), %rsi
148	movq IOFFSET_RDI(%rsp), %rdi	148	movq IOFFSET_RDI(%rsp), %rdi
149	movq IOFFSET_R8(%rsp), %r8	149	movq IOFFSET_R8(%rsp), %r8
150	movq IOFFSET_R9(%rsp), %r9	150	movq IOFFSET_R9(%rsp), %r9
151	movq IOFFSET_R10(%rsp), %r10	151	movq IOFFSET_R10(%rsp), %r10
152	movq IOFFSET_R11(%rsp), %r11	152	movq IOFFSET_R11(%rsp), %r11
153	#ifdef CONFIG_DEBUG_ALLREGS	153	#ifdef CONFIG_DEBUG_ALLREGS
154	movq IOFFSET_RBX(%rsp), %rbx	154	movq IOFFSET_RBX(%rsp), %rbx
155	movq IOFFSET_RBP(%rsp), %rbp	155	movq IOFFSET_RBP(%rsp), %rbp
156	movq IOFFSET_R12(%rsp), %r12	156	movq IOFFSET_R12(%rsp), %r12
157	movq IOFFSET_R13(%rsp), %r13	157	movq IOFFSET_R13(%rsp), %r13
158	movq IOFFSET_R14(%rsp), %r14	158	movq IOFFSET_R14(%rsp), %r14
159	movq IOFFSET_R15(%rsp), %r15	159	movq IOFFSET_R15(%rsp), %r15
160	#endif	160	#endif
161	.endm	161	.endm
162		162
163	#ifdef CONFIG_DEBUG_ALLREGS	163	#ifdef CONFIG_DEBUG_ALLREGS
164	# define INTERRUPT_ALIGN 256	164	# define INTERRUPT_ALIGN 256
165	#else	165	#else
166	# define INTERRUPT_ALIGN 128	166	# define INTERRUPT_ALIGN 128
167	#endif	167	#endif
168		168
169	## Declare interrupt handlers	169	## Declare interrupt handlers
170	#	170	#
171	# Declare interrupt handlers for n interrupt	171	# Declare interrupt handlers for n interrupt
172	# vectors starting at vector i.	172	# vectors starting at vector i.
173	#	173	#
174	# The handlers call exc_dispatch().	174	# The handlers call exc_dispatch().
175	#	175	#
176	.macro handler i n	176	.macro handler i n
177		177
178	/*	178	/*
179	* Choose between version with error code and version without error code.	179	* Choose between version with error code and version without error code.
180	* Both versions have to be of the same size. amd64 assembly is, however,	180	* Both versions have to be of the same size. amd64 assembly is, however,
181	* a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp	181	* a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp
182	* can result in two instructions with different op-code lengths.	182	* can result in two instructions with different op-code lengths.
183	* Therefore we align the interrupt handlers.	183	* Therefore we align the interrupt handlers.
184	*/	184	*/
185		185
186	.iflt \i-32	186	.iflt \i-32
187	.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST	187	.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
188	/*	188	/*
189	* Version with error word.	189	* Version with error word.
190	*/	190	*/
191	subq $IREGISTER_SPACE, %rsp	191	subq $IREGISTER_SPACE, %rsp
192	.else	192	.else
193	/*	193	/*
194	* Version without error word,	194	* Version without error word,
195	*/	195	*/
196	subq $(IREGISTER_SPACE+8), %rsp	196	subq $(IREGISTER_SPACE+8), %rsp
197	.endif	197	.endif
198	.else	198	.else
199	/*	199	/*
200	* Version without error word,	200	* Version without error word,
201	*/	201	*/
202	subq $(IREGISTER_SPACE+8), %rsp	202	subq $(IREGISTER_SPACE+8), %rsp
203	.endif	203	.endif
204		204
205	save_all_gpr	205	save_all_gpr
206		206
207	movq $(\i), %rdi # %rdi - first parameter	207	movq $(\i), %rdi # %rdi - first parameter
208	movq %rsp, %rsi # %rsi - pointer to istate	208	movq %rsp, %rsi # %rsi - pointer to istate
209	call exc_dispatch # exc_dispatch(i, istate)	209	call exc_dispatch # exc_dispatch(i, istate)
210		210
211	restore_all_gpr	211	restore_all_gpr
212	# $8 = Skip error word	212	# $8 = Skip error word
213	addq $(IREGISTER_SPACE+8), %rsp	213	addq $(IREGISTER_SPACE+8), %rsp
214	iretq	214	iretq
215		215
216	.align INTERRUPT_ALIGN	216	.align INTERRUPT_ALIGN
217	.if (\n-\i)-1	217	.if (\n-\i)-1
218	handler "(\i+1)",\n	218	handler "(\i+1)",\n
219	.endif	219	.endif
220	.endm	220	.endm
221		221
222	.align INTERRUPT_ALIGN	222	.align INTERRUPT_ALIGN
223	interrupt_handlers:	223	interrupt_handlers:
224	h_start:	224	h_start:
225	handler 0 IDT_ITEMS	225	handler 0 IDT_ITEMS
226	h_end:	226	h_end:
227		227
228		228
229	syscall_entry:	229	syscall_entry:
230	# Switch to hidden gs	230	# Switch to hidden gs
231	swapgs	231	swapgs
232	# %gs:0 now points to pointer to stack page	232	# %gs:0 now points to pointer to stack page
233	mov %gs:0, %r10 # We have a ptr to stack page in r10	233	mov %gs:0, %r10 # We have a ptr to stack page in r10
234	addq $PAGE_SIZE-16, %r10 # We need some space to store old %sp	234	addq $PAGE_SIZE-16, %r10 # We need some space to store old %sp
235		235
236	movq %rsp, 0(%r10) # Save old stack pointer to stack	236	movq %rsp, 0(%r10) # Save old stack pointer to stack
237	movq %r10, %rsp # Change to new stack	237	movq %r10, %rsp # Change to new stack
238	pushq %rcx # Return address	238	pushq %rcx # Return address
239	pushq %r11 # Save flags	239	pushq %r11 # Save flags
240		240
241	# Switch back to remain consistent	241	# Switch back to remain consistent
242	swapgs	242	swapgs
243		243
244	sti	244	sti
245	movq %r9, %rcx # Exchange last parameter as a third	245	movq %r9, %rcx # Exchange last parameter as a third
-		246
-		247	cmp $2, %r8 # Is this SYS_INT_CONTROL
-		248	je sys_int_ctrl
-		249
246	call syscall_handler	250	call syscall_handler
-		251	sys_end:
247	cli # We will be touching stack pointer	252	cli # We will be touching stack pointer
248		253
249	popq %r11	254	popq %r11
250	popq %rcx	255	popq %rcx
251	movq 0(%rsp), %rsp	256	movq 0(%rsp), %rsp
252	sysretq	257	sysretq
-		258
-		259	sys_int_ctrl:
-		260	mov %rsp, %rsi # Pointer to flags
-		261	call ddi_int_control
-		262	jmp sys_end
-		263
253		264
254	.data	265	.data
255	.global interrupt_handler_size	266	.global interrupt_handler_size
256		267
257	interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS	268	interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS
258		269

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/src/asm_utils.S – Rev 1121 → 1212