WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/amd64.c


/*
 * Copyright (C) 2005 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch.h>
 
#include <arch/types.h>
 
#include <config.h>
 
#include <proc/thread.h>
#include <arch/ega.h>
#include <arch/vesa.h>
#include <genarch/i8042/i8042.h>
#include <arch/i8254.h>
#include <arch/i8259.h>
 
#include <arch/bios/bios.h>
#include <arch/mm/memory_init.h>
#include <arch/cpu.h>
#include <print.h>
#include <arch/cpuid.h>
#include <genarch/acpi/acpi.h>
#include <panic.h>
#include <interrupt.h>
#include <arch/syscall.h>
#include <arch/debugger.h>
#include <syscall/syscall.h>
 
 
/** Disable I/O on non-privileged levels
 *
 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
 */
static void clean_IOPL_NT_flags(void)
{
    asm
    (
        "pushfq;"
        "pop %%rax;"
        "and $~(0x7000),%%rax;"
        "pushq %%rax;"
        "popfq;"
        :
        :
        :"%rax"
    );
}
 
/** Disable alignment check
 *
 * Clean AM(18) flag in CR0 register
 */
static void clean_AM_flag(void)
{
    asm
    (
        "mov %%cr0,%%rax;"
        "and $~(0x40000),%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
    );
}
 
void arch_pre_mm_init(void)
{
    struct cpu_info cpuid_s;
 
    cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
    if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
        panic("Processor does not support No-execute pages.\n");
 
    cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
    if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
        panic("Processor does not support FXSAVE/FXRESTORE.\n");
   
    if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
        panic("Processor does not support SSE2 instructions.\n");
 
    /* Enable No-execute pages */
    set_efer_flag(AMD_NXE_FLAG);
    /* Enable FPU */
    cpu_setup_fpu();
 
    /* Initialize segmentation */
    pm_init();
 
        /* Disable I/O on nonprivileged levels
     * clear the NT(nested-thread) flag
     */
    clean_IOPL_NT_flags();
    /* Disable alignment check */
    clean_AM_flag();
 
    if (config.cpu_active == 1) {
        bios_init();
        i8259_init();   /* PIC */
        i8254_init();   /* hard clock */
 
        #ifdef CONFIG_SMP
        exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
                 tlb_shootdown_ipi);
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_mm_init(void)
{
    if (config.cpu_active == 1) {
#ifdef CONFIG_FB
        if (vesa_present())
            vesa_init();
        else
#endif
            ega_init(); /* video */
        /* Enable debugger */
        debugger_init();
        /* Merge all memory zones to 1 big zone */
        zone_merge_all();
    }
    /* Setup fast SYSCALL/SYSRET */
    syscall_setup_cpu();
   
}
 
void arch_pre_smp_init(void)
{
    if (config.cpu_active == 1) {
        memory_print_map();
       
        #ifdef CONFIG_SMP
        acpi_init();
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_smp_init(void)
{
    i8042_init();   /* keyboard controller */
}
 
void calibrate_delay_loop(void)
{
    i8254_calibrate_delay_loop();
    i8254_normal_operation();
}
 
/** Set thread-local-storage pointer
 *
 * TLS pointer is set in FS register. Unfortunately the 64-bit
 * part can be set only in CPL0 mode.
 *
 * The specs say, that on %fs:0 there is stored contents of %fs register,
 * we need not to go to CPL0 to read it.
 */
__native sys_tls_set(__native addr)
{
    THREAD->arch.tls = addr;
    write_msr(AMD_MSR_FS, addr);
    return 0;
}
 

Rev 1289	Rev 1303
1	/*	1	/*
2	* Copyright (C) 2005 Ondrej Palkovsky	2	* Copyright (C) 2005 Ondrej Palkovsky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch.h>	29	#include <arch.h>
30		30
31	#include <arch/types.h>	31	#include <arch/types.h>
32		32
33	#include <config.h>	33	#include <config.h>
34		34
35	#include <proc/thread.h>	35	#include <proc/thread.h>
36	#include <arch/ega.h>	36	#include <arch/ega.h>
37	#include <arch/vesa.h>	37	#include <arch/vesa.h>
38	#include <genarch/i8042/i8042.h>	38	#include <genarch/i8042/i8042.h>
39	#include <arch/i8254.h>	39	#include <arch/i8254.h>
40	#include <arch/i8259.h>	40	#include <arch/i8259.h>
41		41
42	#include <arch/bios/bios.h>	42	#include <arch/bios/bios.h>
43	#include <arch/mm/memory_init.h>	43	#include <arch/mm/memory_init.h>
44	#include <arch/cpu.h>	44	#include <arch/cpu.h>
45	#include <print.h>	45	#include <print.h>
46	#include <arch/cpuid.h>	46	#include <arch/cpuid.h>
47	#include <genarch/acpi/acpi.h>	47	#include <genarch/acpi/acpi.h>
48	#include <panic.h>	48	#include <panic.h>
49	#include <interrupt.h>	49	#include <interrupt.h>
50	#include <arch/syscall.h>	50	#include <arch/syscall.h>
51	#include <arch/debugger.h>	51	#include <arch/debugger.h>
52	#include <syscall/syscall.h>	52	#include <syscall/syscall.h>
53		53
54		54
55	/** Disable I/O on non-privileged levels	55	/** Disable I/O on non-privileged levels
56	*	56	*
57	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register	57	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register
58	*/	58	*/
59	static void clean_IOPL_NT_flags(void)	59	static void clean_IOPL_NT_flags(void)
60	{	60	{
61	asm	61	asm
62	(	62	(
63	"pushfq;"	63	"pushfq;"
64	"pop %%rax;"	64	"pop %%rax;"
65	"and $~(0x7000),%%rax;"	65	"and $~(0x7000),%%rax;"
66	"pushq %%rax;"	66	"pushq %%rax;"
67	"popfq;"	67	"popfq;"
68	:	68	:
69	:	69	:
70	:"%rax"	70	:"%rax"
71	);	71	);
72	}	72	}
73		73
74	/** Disable alignment check	74	/** Disable alignment check
75	*	75	*
76	* Clean AM(18) flag in CR0 register	76	* Clean AM(18) flag in CR0 register
77	*/	77	*/
78	static void clean_AM_flag(void)	78	static void clean_AM_flag(void)
79	{	79	{
80	asm	80	asm
81	(	81	(
82	"mov %%cr0,%%rax;"	82	"mov %%cr0,%%rax;"
83	"and $~(0x40000),%%rax;"	83	"and $~(0x40000),%%rax;"
84	"mov %%rax,%%cr0;"	84	"mov %%rax,%%cr0;"
85	:	85	:
86	:	86	:
87	:"%rax"	87	:"%rax"
88	);	88	);
89	}	89	}
90		90
91	void arch_pre_mm_init(void)	91	void arch_pre_mm_init(void)
92	{	92	{
93	struct cpu_info cpuid_s;	93	struct cpu_info cpuid_s;
94		94
95	cpuid(AMD_CPUID_EXTENDED,&cpuid_s);	95	cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
96	if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))	96	if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
97	panic("Processor does not support No-execute pages.\n");	97	panic("Processor does not support No-execute pages.\n");
98		98
99	cpuid(INTEL_CPUID_STANDARD,&cpuid_s);	99	cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
100	if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))	100	if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
101	panic("Processor does not support FXSAVE/FXRESTORE.\n");	101	panic("Processor does not support FXSAVE/FXRESTORE.\n");
102		102
103	if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))	103	if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
104	panic("Processor does not support SSE2 instructions.\n");	104	panic("Processor does not support SSE2 instructions.\n");
105		105
106	/* Enable No-execute pages */	106	/* Enable No-execute pages */
107	set_efer_flag(AMD_NXE_FLAG);	107	set_efer_flag(AMD_NXE_FLAG);
108	/* Enable FPU */	108	/* Enable FPU */
109	cpu_setup_fpu();	109	cpu_setup_fpu();
110		110
111	/* Initialize segmentation */	111	/* Initialize segmentation */
112	pm_init();	112	pm_init();
113		113
114	/* Disable I/O on nonprivileged levels	114	/* Disable I/O on nonprivileged levels
115	* clear the NT(nested-thread) flag	115	* clear the NT(nested-thread) flag
116	*/	116	*/
117	clean_IOPL_NT_flags();	117	clean_IOPL_NT_flags();
118	/* Disable alignment check */	118	/* Disable alignment check */
119	clean_AM_flag();	119	clean_AM_flag();
120		120
121	if (config.cpu_active == 1) {	121	if (config.cpu_active == 1) {
122	bios_init();	122	bios_init();
123	i8259_init(); /* PIC */	123	i8259_init(); /* PIC */
124	i8254_init(); /* hard clock */	124	i8254_init(); /* hard clock */
125		125
126	#ifdef CONFIG_SMP	126	#ifdef CONFIG_SMP
127	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",	127	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
128	tlb_shootdown_ipi);	128	tlb_shootdown_ipi);
129	#endif /* CONFIG_SMP */	129	#endif /* CONFIG_SMP */
130	}	130	}
131	}	131	}
132		132
133	void arch_post_mm_init(void)	133	void arch_post_mm_init(void)
134	{	134	{
135	if (config.cpu_active == 1) {	135	if (config.cpu_active == 1) {
136	#ifdef CONFIG_FB	136	#ifdef CONFIG_FB
137	if (vesa_present()) vesa_init();	137	if (vesa_present())
-		138	vesa_init();
138	else	139	else
139	#endif	140	#endif
140	ega_init(); /* video */	141	ega_init(); /* video */
141	/* Enable debugger */	142	/* Enable debugger */
142	debugger_init();	143	debugger_init();
-		144	/* Merge all memory zones to 1 big zone */
-		145	zone_merge_all();
143	}	146	}
144	/* Setup fast SYSCALL/SYSRET */	147	/* Setup fast SYSCALL/SYSRET */
145	syscall_setup_cpu();	148	syscall_setup_cpu();
146		149
147	}	150	}
148		151
149	void arch_pre_smp_init(void)	152	void arch_pre_smp_init(void)
150	{	153	{
151	if (config.cpu_active == 1) {	154	if (config.cpu_active == 1) {
152	memory_print_map();	155	memory_print_map();
153		156
154	#ifdef CONFIG_SMP	157	#ifdef CONFIG_SMP
155	acpi_init();	158	acpi_init();
156	#endif /* CONFIG_SMP */	159	#endif /* CONFIG_SMP */
157	}	160	}
158	}	161	}
159		162
160	void arch_post_smp_init(void)	163	void arch_post_smp_init(void)
161	{	164	{
162	i8042_init(); /* keyboard controller */	165	i8042_init(); /* keyboard controller */
163	}	166	}
164		167
165	void calibrate_delay_loop(void)	168	void calibrate_delay_loop(void)
166	{	169	{
167	i8254_calibrate_delay_loop();	170	i8254_calibrate_delay_loop();
168	i8254_normal_operation();	171	i8254_normal_operation();
169	}	172	}
170		173
171	/** Set thread-local-storage pointer	174	/** Set thread-local-storage pointer
172	*	175	*
173	* TLS pointer is set in FS register. Unfortunately the 64-bit	176	* TLS pointer is set in FS register. Unfortunately the 64-bit
174	* part can be set only in CPL0 mode.	177	* part can be set only in CPL0 mode.
175	*	178	*
176	* The specs say, that on %fs:0 there is stored contents of %fs register,	179	* The specs say, that on %fs:0 there is stored contents of %fs register,
177	* we need not to go to CPL0 to read it.	180	* we need not to go to CPL0 to read it.
178	*/	181	*/
179	__native sys_tls_set(__native addr)	182	__native sys_tls_set(__native addr)
180	{	183	{
181	THREAD->arch.tls = addr;	184	THREAD->arch.tls = addr;
182	write_msr(AMD_MSR_FS, addr);	185	write_msr(AMD_MSR_FS, addr);
183	return 0;	186	return 0;
184	}	187	}
185		188

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/src/amd64.c @ 1780 – Rev 1289 → 1303