WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/amd64.c


/*
 * Copyright (C) 2005 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch.h>
 
#include <arch/types.h>
 
#include <config.h>
 
#include <proc/thread.h>
#include <arch/ega.h>
#include <genarch/i8042/i8042.h>
#include <arch/i8254.h>
#include <arch/i8259.h>
 
#include <arch/bios/bios.h>
#include <arch/mm/memory_init.h>
#include <arch/cpu.h>
#include <print.h>
#include <arch/cpuid.h>
#include <genarch/acpi/acpi.h>
#include <panic.h>
#include <interrupt.h>
#include <arch/syscall.h>
#include <arch/debugger.h>
#include <syscall/syscall.h>
 
 
/** Disable I/O on non-privileged levels
 *
 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
 */
static void clean_IOPL_NT_flags(void)
{
    asm
    (
        "pushfq;"
        "pop %%rax;"
        "and $~(0x7000),%%rax;"
        "pushq %%rax;"
        "popfq;"
        :
        :
        :"%rax"
    );
}
 
/** Disable alignment check
 *
 * Clean AM(18) flag in CR0 register
 */
static void clean_AM_flag(void)
{
    asm
    (
        "mov %%cr0,%%rax;"
        "and $~(0x40000),%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
    );
}
 
void arch_pre_mm_init(void)
{
    struct cpu_info cpuid_s;
 
    cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
    if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
        panic("Processor does not support No-execute pages.\n");
 
    cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
    if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
        panic("Processor does not support FXSAVE/FXRESTORE.\n");
   
    if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
        panic("Processor does not support SSE2 instructions.\n");
 
    /* Enable No-execute pages */
    set_efer_flag(AMD_NXE_FLAG);
    /* Enable FPU */
    cpu_setup_fpu();
 
    /* Initialize segmentation */
    pm_init();
 
        /* Disable I/O on nonprivileged levels
     * clear the NT(nested-thread) flag
     */
    clean_IOPL_NT_flags();
    /* Disable alignment check */
    clean_AM_flag();
 
    if (config.cpu_active == 1) {
        bios_init();
        i8259_init();   /* PIC */
        i8254_init();   /* hard clock */
 
        #ifdef CONFIG_SMP
        exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
                 tlb_shootdown_ipi);
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_mm_init(void)
{
    if (config.cpu_active == 1) {
        ega_init(); /* video */
        /* Enable debugger */
        debugger_init();
    }
    /* Setup fast SYSCALL/SYSRET */
    syscall_setup_cpu();
   
}
 
void arch_pre_smp_init(void)
{
    if (config.cpu_active == 1) {
        memory_print_map();
       
        #ifdef CONFIG_SMP
        acpi_init();
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_smp_init(void)
{
    i8042_init();   /* keyboard controller */
}
 
void calibrate_delay_loop(void)
{
    i8254_calibrate_delay_loop();
    i8254_normal_operation();
}
 
/** Set thread-local-storage pointer
 *
 * TLS pointer is set in FS register. Unfortunately the 64-bit
 * part can be set only in CPL0 mode.
 *
 * The specs say, that on %fs:0 there is stored contents of %fs register,
 * we need not to go to CPL0 to read it.
 */
__native sys_tls_set(__native addr)
{
    THREAD->tls = addr;
    write_msr(AMD_MSR_FS, addr);
    return 0;
}
 

Rev 1112	Rev 1121
1	/*	1	/*
2	* Copyright (C) 2005 Ondrej Palkovsky	2	* Copyright (C) 2005 Ondrej Palkovsky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch.h>	29	#include <arch.h>
30		30
31	#include <arch/types.h>	31	#include <arch/types.h>
32		32
33	#include <config.h>	33	#include <config.h>
34		34
35	#include <proc/thread.h>	35	#include <proc/thread.h>
36	#include <arch/ega.h>	36	#include <arch/ega.h>
37	#include <genarch/i8042/i8042.h>	37	#include <genarch/i8042/i8042.h>
38	#include <arch/i8254.h>	38	#include <arch/i8254.h>
39	#include <arch/i8259.h>	39	#include <arch/i8259.h>
40		40
41	#include <arch/bios/bios.h>	41	#include <arch/bios/bios.h>
42	#include <arch/mm/memory_init.h>	42	#include <arch/mm/memory_init.h>
43	#include <arch/cpu.h>	43	#include <arch/cpu.h>
44	#include <print.h>	44	#include <print.h>
45	#include <arch/cpuid.h>	45	#include <arch/cpuid.h>
46	#include <genarch/acpi/acpi.h>	46	#include <genarch/acpi/acpi.h>
47	#include <panic.h>	47	#include <panic.h>
48	#include <interrupt.h>	48	#include <interrupt.h>
49	#include <arch/syscall.h>	49	#include <arch/syscall.h>
50	#include <arch/debugger.h>	50	#include <arch/debugger.h>
51	#include <syscall/syscall.h>	51	#include <syscall/syscall.h>
52		52
53		53
54	/** Disable I/O on non-privileged levels	54	/** Disable I/O on non-privileged levels
55	*	55	*
56	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register	56	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register
57	*/	57	*/
58	static void clean_IOPL_NT_flags(void)	58	static void clean_IOPL_NT_flags(void)
59	{	59	{
60	asm	60	asm
61	(	61	(
62	"pushfq;"	62	"pushfq;"
63	"pop %%rax;"	63	"pop %%rax;"
64	"and $~(0x7000),%%rax;"	64	"and $~(0x7000),%%rax;"
65	"pushq %%rax;"	65	"pushq %%rax;"
66	"popfq;"	66	"popfq;"
67	:	67	:
68	:	68	:
69	:"%rax"	69	:"%rax"
70	);	70	);
71	}	71	}
72		72
73	/** Disable alignment check	73	/** Disable alignment check
74	*	74	*
75	* Clean AM(18) flag in CR0 register	75	* Clean AM(18) flag in CR0 register
76	*/	76	*/
77	static void clean_AM_flag(void)	77	static void clean_AM_flag(void)
78	{	78	{
79	asm	79	asm
80	(	80	(
81	"mov %%cr0,%%rax;"	81	"mov %%cr0,%%rax;"
82	"and $~(0x40000),%%rax;"	82	"and $~(0x40000),%%rax;"
83	"mov %%rax,%%cr0;"	83	"mov %%rax,%%cr0;"
84	:	84	:
85	:	85	:
86	:"%rax"	86	:"%rax"
87	);	87	);
88	}	88	}
89		89
90	void arch_pre_mm_init(void)	90	void arch_pre_mm_init(void)
91	{	91	{
92	struct cpu_info cpuid_s;	92	struct cpu_info cpuid_s;
93		93
94	cpuid(AMD_CPUID_EXTENDED,&cpuid_s);	94	cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
95	if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))	95	if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
96	panic("Processor does not support No-execute pages.\n");	96	panic("Processor does not support No-execute pages.\n");
97		97
98	cpuid(INTEL_CPUID_STANDARD,&cpuid_s);	98	cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
99	if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))	99	if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
100	panic("Processor does not support FXSAVE/FXRESTORE.\n");	100	panic("Processor does not support FXSAVE/FXRESTORE.\n");
101		101
102	if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))	102	if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
103	panic("Processor does not support SSE2 instructions.\n");	103	panic("Processor does not support SSE2 instructions.\n");
104		104
105	/* Enable No-execute pages */	105	/* Enable No-execute pages */
106	set_efer_flag(AMD_NXE_FLAG);	106	set_efer_flag(AMD_NXE_FLAG);
107	/* Enable FPU */	107	/* Enable FPU */
108	cpu_setup_fpu();	108	cpu_setup_fpu();
109		109
110	/* Initialize segmentation */	110	/* Initialize segmentation */
111	pm_init();	111	pm_init();
112		112
113	/* Disable I/O on nonprivileged levels	113	/* Disable I/O on nonprivileged levels
114	* clear the NT(nested-thread) flag	114	* clear the NT(nested-thread) flag
115	*/	115	*/
116	clean_IOPL_NT_flags();	116	clean_IOPL_NT_flags();
117	/* Disable alignment check */	117	/* Disable alignment check */
118	clean_AM_flag();	118	clean_AM_flag();
119		119
120	if (config.cpu_active == 1) {	120	if (config.cpu_active == 1) {
121	bios_init();	121	bios_init();
122	i8259_init(); /* PIC */	122	i8259_init(); /* PIC */
123	i8254_init(); /* hard clock */	123	i8254_init(); /* hard clock */
124		124
125	#ifdef CONFIG_SMP	125	#ifdef CONFIG_SMP
126	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",	126	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
127	tlb_shootdown_ipi);	127	tlb_shootdown_ipi);
128	#endif /* CONFIG_SMP */	128	#endif /* CONFIG_SMP */
129	}	129	}
130	}	130	}
131		131
132	void arch_post_mm_init(void)	132	void arch_post_mm_init(void)
133	{	133	{
134	if (config.cpu_active == 1) {	134	if (config.cpu_active == 1) {
135	ega_init(); /* video */	135	ega_init(); /* video */
136	/* Enable debugger */	136	/* Enable debugger */
137	debugger_init();	137	debugger_init();
138	}	138	}
139	/* Setup fast SYSCALL/SYSRET */	139	/* Setup fast SYSCALL/SYSRET */
140	syscall_setup_cpu();	140	syscall_setup_cpu();
141		141
142	}	142	}
143		143
144	void arch_pre_smp_init(void)	144	void arch_pre_smp_init(void)
145	{	145	{
146	if (config.cpu_active == 1) {	146	if (config.cpu_active == 1) {
147	memory_print_map();	147	memory_print_map();
148		148
149	#ifdef CONFIG_SMP	149	#ifdef CONFIG_SMP
150	acpi_init();	150	acpi_init();
151	#endif /* CONFIG_SMP */	151	#endif /* CONFIG_SMP */
152	}	152	}
153	}	153	}
154		154
155	void arch_post_smp_init(void)	155	void arch_post_smp_init(void)
156	{	156	{
157	i8042_init(); /* keyboard controller */	157	i8042_init(); /* keyboard controller */
158	}	158	}
159		159
160	void calibrate_delay_loop(void)	160	void calibrate_delay_loop(void)
161	{	161	{
162	i8254_calibrate_delay_loop();	162	i8254_calibrate_delay_loop();
163	i8254_normal_operation();	163	i8254_normal_operation();
164	}	164	}
165		165
166	/** Set Thread-local-storeage pointer	166	/** Set thread-local-storage pointer
167	*	167	*
168	* TLS pointer is set in FS register. Unfortunately the 64-bit	168	* TLS pointer is set in FS register. Unfortunately the 64-bit
169	* part can be set only in CPL0 mode.	169	* part can be set only in CPL0 mode.
170	*	170	*
171	* The specs says, that on %fs:0 there is stored contents of %fs register,	171	* The specs say, that on %fs:0 there is stored contents of %fs register,
172	* we need not to go to CPL0 to read it.	172	* we need not to go to CPL0 to read it.
173	*/	173	*/
174	__native sys_tls_set(__native addr)	174	__native sys_tls_set(__native addr)
175	{	175	{
176	THREAD->tls = addr;	176	THREAD->tls = addr;
177	write_msr(AMD_MSR_FS, addr);	177	write_msr(AMD_MSR_FS, addr);
178	return 0;	178	return 0;
179	}	179	}
180		180

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/src/amd64.c – Rev 1112 → 1121