WebSVN – HelenOS – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
 
void asm_delay_loop(__u32 t);
void asm_fake_loop(__u32 t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__("hlt"); };
static inline void cpu_halt(void) { __asm__("hlt"); };
 
 
static inline __u8 inb(__u16 port)
{
    __u8 out;
 
    __asm__ volatile (
        "mov %1, %%dx;"
        "inb %%dx,%%al;"
        "mov %%al, %0;"
        :"=m"(out)
        :"m"(port)
        :"%rdx","%rax"
        );
    return out;
}
 
static inline __u8 outb(__u16 port,__u8 b)
{
    __asm__ volatile (
        "mov %0,%%dx;"
        "mov %1,%%al;"
        "outb %%al,%%dx;"
        :
        :"m"( port), "m" (b)
        :"%rdx","%rax"
        );
}
 
/** Set priority level low
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_low(void) {
    pri_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Set priority level high
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_high(void) {
    pri_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore priority level
 *
 * Restore EFLAGS.
 */
static inline void cpu_priority_restore(pri_t pri) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (pri)
        );
}
 
/** Return raw priority level
 *
 * Return EFLAFS.
 */
static inline pri_t cpu_priority_read(void) {
    pri_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; }
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u64 v) { __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); }
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; }
 
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 

Rev 252	Rev 253
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __amd64_ASM_H__	29	#ifndef __amd64_ASM_H__
30	#define __amd64_ASM_H__	30	#define __amd64_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35		35
36	void asm_delay_loop(__u32 t);	36	void asm_delay_loop(__u32 t);
37	void asm_fake_loop(__u32 t);	37	void asm_fake_loop(__u32 t);
38		38
-		39	/** Return base address of current stack.
-		40	*
-		41	* Return the base address of the current stack.
-		42	* The stack is assumed to be STACK_SIZE bytes long.
-		43	* The stack must start on page boundary.
-		44	*/
39	static inline __address get_stack_base(void)	45	static inline __address get_stack_base(void)
40	{	46	{
41	__address v;	47	__address v;
42		48
43	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	49	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
44		50
45	return v;	51	return v;
46	}	52	}
47		53
48	static inline void cpu_sleep(void) { __asm__("hlt"); };	54	static inline void cpu_sleep(void) { __asm__("hlt"); };
49	static inline void cpu_halt(void) { __asm__("hlt"); };	55	static inline void cpu_halt(void) { __asm__("hlt"); };
50		56
51		57
52	static inline __u8 inb(__u16 port)	58	static inline __u8 inb(__u16 port)
53	{	59	{
54	__u8 out;	60	__u8 out;
55		61
56	__asm__ volatile (	62	__asm__ volatile (
57	"mov %1, %%dx;"	63	"mov %1, %%dx;"
58	"inb %%dx,%%al;"	64	"inb %%dx,%%al;"
59	"mov %%al, %0;"	65	"mov %%al, %0;"
60	:"=m"(out)	66	:"=m"(out)
61	:"m"(port)	67	:"m"(port)
62	:"%rdx","%rax"	68	:"%rdx","%rax"
63	);	69	);
64	return out;	70	return out;
65	}	71	}
66		72
67	static inline __u8 outb(__u16 port,__u8 b)	73	static inline __u8 outb(__u16 port,__u8 b)
68	{	74	{
69	__asm__ volatile (	75	__asm__ volatile (
70	"mov %0,%%dx;"	76	"mov %0,%%dx;"
71	"mov %1,%%al;"	77	"mov %1,%%al;"
72	"outb %%al,%%dx;"	78	"outb %%al,%%dx;"
73	:	79	:
74	:"m"( port), "m" (b)	80	:"m"( port), "m" (b)
75	:"%rdx","%rax"	81	:"%rdx","%rax"
76	);	82	);
77	}	83	}
78		84
79	/** Set priority level low	85	/** Set priority level low
80	*	86	*
81	* Enable interrupts and return previous	87	* Enable interrupts and return previous
82	* value of EFLAGS.	88	* value of EFLAGS.
83	*/	89	*/
84	static inline pri_t cpu_priority_low(void) {	90	static inline pri_t cpu_priority_low(void) {
85	pri_t v;	91	pri_t v;
86	__asm__ volatile (	92	__asm__ volatile (
87	"pushfq\n"	93	"pushfq\n"
88	"popq %0\n"	94	"popq %0\n"
89	"sti\n"	95	"sti\n"
90	: "=r" (v)	96	: "=r" (v)
91	);	97	);
92	return v;	98	return v;
93	}	99	}
94		100
95	/** Set priority level high	101	/** Set priority level high
96	*	102	*
97	* Disable interrupts and return previous	103	* Disable interrupts and return previous
98	* value of EFLAGS.	104	* value of EFLAGS.
99	*/	105	*/
100	static inline pri_t cpu_priority_high(void) {	106	static inline pri_t cpu_priority_high(void) {
101	pri_t v;	107	pri_t v;
102	__asm__ volatile (	108	__asm__ volatile (
103	"pushfq\n"	109	"pushfq\n"
104	"popq %0\n"	110	"popq %0\n"
105	"cli\n"	111	"cli\n"
106	: "=r" (v)	112	: "=r" (v)
107	);	113	);
108	return v;	114	return v;
109	}	115	}
110		116
111	/** Restore priority level	117	/** Restore priority level
112	*	118	*
113	* Restore EFLAGS.	119	* Restore EFLAGS.
114	*/	120	*/
115	static inline void cpu_priority_restore(pri_t pri) {	121	static inline void cpu_priority_restore(pri_t pri) {
116	__asm__ volatile (	122	__asm__ volatile (
117	"pushq %0\n"	123	"pushq %0\n"
118	"popfq\n"	124	"popfq\n"
119	: : "r" (pri)	125	: : "r" (pri)
120	);	126	);
121	}	127	}
122		128
123	/** Return raw priority level	129	/** Return raw priority level
124	*	130	*
125	* Return EFLAFS.	131	* Return EFLAFS.
126	*/	132	*/
127	static inline pri_t cpu_priority_read(void) {	133	static inline pri_t cpu_priority_read(void) {
128	pri_t v;	134	pri_t v;
129	__asm__ volatile (	135	__asm__ volatile (
130	"pushfq\n"	136	"pushfq\n"
131	"popq %0\n"	137	"popq %0\n"
132	: "=r" (v)	138	: "=r" (v)
133	);	139	);
134	return v;	140	return v;
135	}	141	}
136		142
137	/** Read CR2	143	/** Read CR2
138	*	144	*
139	* Return value in CR2	145	* Return value in CR2
140	*	146	*
141	* @return Value read.	147	* @return Value read.
142	*/	148	*/
143	static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; }	149	static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; }
144		150
145	/** Write CR3	151	/** Write CR3
146	*	152	*
147	* Write value to CR3.	153	* Write value to CR3.
148	*	154	*
149	* @param v Value to be written.	155	* @param v Value to be written.
150	*/	156	*/
151	static inline void write_cr3(__u64 v) { __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); }	157	static inline void write_cr3(__u64 v) { __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); }
152		158
153	/** Read CR3	159	/** Read CR3
154	*	160	*
155	* Return value in CR3	161	* Return value in CR3
156	*	162	*
157	* @return Value read.	163	* @return Value read.
158	*/	164	*/
159	static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; }	165	static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; }
160		166
161		167
162	extern size_t interrupt_handler_size;	168	extern size_t interrupt_handler_size;
163	extern void interrupt_handlers(void);	169	extern void interrupt_handlers(void);
164		170
165	#endif	171	#endif
166		172

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(root)/kernel/trunk/arch/amd64/include/asm.h @ 655 – Rev 252 → 253