WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
extern void asm_delay_loop(__u32 t);
extern void asm_fake_loop(__u32 t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
 
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
 
 
 
 
 
/** Byte to port
 
 
 
 *
 
 * Output byte to port
 *
 * @param port Port to write to
 
 
 * @param val Value to write
 */
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
 
 
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (ipl)
        );
}
 
/** Return interrupt priority level.
 *
 * Return EFLAFS.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Read CR0
 *
 * Return value in CR0
 *
 * @return Value read.
 */
static inline __u64 read_cr0(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
    return v;
}
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u64 read_cr2(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
    return v;
}
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u64 v)
{
    __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
}
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u64 read_cr3(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr3,%0" : "=r" (v));
    return v;
}
 
 
/** Enable local APIC
 *
 * Enable local APIC in MSR.
 */
static inline void enable_l_apic_in_msr()
{
    __asm__ volatile (
        "movl $0x1b, %%ecx\n"
        "rdmsr\n"
        "orl $(1<<11),%%eax\n"
        "orl $(0xfee00000),%%eax\n"
        "wrmsr\n"
        :
        :
        :"%eax","%ecx","%edx"
        );
}
 
static inline __address * get_ip()
{
    __address *ip;
 
    __asm__ volatile (
        "mov %%rip, %0"
        : "=r" (ip)
        );
    return ip;
}
 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(__address addr)
{
        __asm__ volatile ("invlpg %0\n" :: "m" (addr));
}
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 

Rev 597	Rev 625
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __amd64_ASM_H__	29	#ifndef __amd64_ASM_H__
30	#define __amd64_ASM_H__	30	#define __amd64_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35	extern void asm_delay_loop(__u32 t);	35	extern void asm_delay_loop(__u32 t);
36	extern void asm_fake_loop(__u32 t);	36	extern void asm_fake_loop(__u32 t);
37		37
38	/** Return base address of current stack.	38	/** Return base address of current stack.
39	*	39	*
40	* Return the base address of the current stack.	40	* Return the base address of the current stack.
41	* The stack is assumed to be STACK_SIZE bytes long.	41	* The stack is assumed to be STACK_SIZE bytes long.
42	* The stack must start on page boundary.	42	* The stack must start on page boundary.
43	*/	43	*/
44	static inline __address get_stack_base(void)	44	static inline __address get_stack_base(void)
45	{	45	{
46	__address v;	46	__address v;
47		47
48	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	48	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
49		49
50	return v;	50	return v;
51	}	51	}
52		52
53	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };	53	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
54	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };	54	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
55		55
56		56
-		57	/** Byte from port
-		58	*
57	static inline __u8 inb(__u16 port)	59	* Get byte from port
58	{	60	*
-		61	* @param port Port to read from
59	__u8 out;	62	* @return Value read
-		63	*/
-		64	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
60		65
61	__asm__ volatile (	-
62	"mov %1, %%dx\n"	-
63	"inb %%dx,%%al\n"	-
64	"mov %%al, %0\n"	-
65	:"=m"(out)	-
66	:"m"(port)	66	/** Byte to port
67	:"%rdx","%rax"	-
68	);	-
69	return out;	-
70	}	67	*
71		-
72	static inline __u8 outb(__u16 port,__u8 b)	68	* Output byte to port
73	{	69	*
74	__asm__ volatile (	70	* @param port Port to write to
75	"mov %0,%%dx\n"	-
76	"mov %1,%%al\n"	-
77	"outb %%al,%%dx\n"	71	* @param val Value to write
78	:	72	*/
79	:"m"( port), "m" (b)	73	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
80	:"%rdx","%rax"	-
81	);	-
82	}	-
83		74
84	/** Enable interrupts.	75	/** Enable interrupts.
85	*	76	*
86	* Enable interrupts and return previous	77	* Enable interrupts and return previous
87	* value of EFLAGS.	78	* value of EFLAGS.
88	*	79	*
89	* @return Old interrupt priority level.	80	* @return Old interrupt priority level.
90	*/	81	*/
91	static inline ipl_t interrupts_enable(void) {	82	static inline ipl_t interrupts_enable(void) {
92	ipl_t v;	83	ipl_t v;
93	__asm__ volatile (	84	__asm__ volatile (
94	"pushfq\n"	85	"pushfq\n"
95	"popq %0\n"	86	"popq %0\n"
96	"sti\n"	87	"sti\n"
97	: "=r" (v)	88	: "=r" (v)
98	);	89	);
99	return v;	90	return v;
100	}	91	}
101		92
102	/** Disable interrupts.	93	/** Disable interrupts.
103	*	94	*
104	* Disable interrupts and return previous	95	* Disable interrupts and return previous
105	* value of EFLAGS.	96	* value of EFLAGS.
106	*	97	*
107	* @return Old interrupt priority level.	98	* @return Old interrupt priority level.
108	*/	99	*/
109	static inline ipl_t interrupts_disable(void) {	100	static inline ipl_t interrupts_disable(void) {
110	ipl_t v;	101	ipl_t v;
111	__asm__ volatile (	102	__asm__ volatile (
112	"pushfq\n"	103	"pushfq\n"
113	"popq %0\n"	104	"popq %0\n"
114	"cli\n"	105	"cli\n"
115	: "=r" (v)	106	: "=r" (v)
116	);	107	);
117	return v;	108	return v;
118	}	109	}
119		110
120	/** Restore interrupt priority level.	111	/** Restore interrupt priority level.
121	*	112	*
122	* Restore EFLAGS.	113	* Restore EFLAGS.
123	*	114	*
124	* @param ipl Saved interrupt priority level.	115	* @param ipl Saved interrupt priority level.
125	*/	116	*/
126	static inline void interrupts_restore(ipl_t ipl) {	117	static inline void interrupts_restore(ipl_t ipl) {
127	__asm__ volatile (	118	__asm__ volatile (
128	"pushq %0\n"	119	"pushq %0\n"
129	"popfq\n"	120	"popfq\n"
130	: : "r" (ipl)	121	: : "r" (ipl)
131	);	122	);
132	}	123	}
133		124
134	/** Return interrupt priority level.	125	/** Return interrupt priority level.
135	*	126	*
136	* Return EFLAFS.	127	* Return EFLAFS.
137	*	128	*
138	* @return Current interrupt priority level.	129	* @return Current interrupt priority level.
139	*/	130	*/
140	static inline ipl_t interrupts_read(void) {	131	static inline ipl_t interrupts_read(void) {
141	ipl_t v;	132	ipl_t v;
142	__asm__ volatile (	133	__asm__ volatile (
143	"pushfq\n"	134	"pushfq\n"
144	"popq %0\n"	135	"popq %0\n"
145	: "=r" (v)	136	: "=r" (v)
146	);	137	);
147	return v;	138	return v;
148	}	139	}
149		140
150	/** Read CR0	141	/** Read CR0
151	*	142	*
152	* Return value in CR0	143	* Return value in CR0
153	*	144	*
154	* @return Value read.	145	* @return Value read.
155	*/	146	*/
156	static inline __u64 read_cr0(void)	147	static inline __u64 read_cr0(void)
157	{	148	{
158	__u64 v;	149	__u64 v;
159	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));	150	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
160	return v;	151	return v;
161	}	152	}
162		153
163	/** Read CR2	154	/** Read CR2
164	*	155	*
165	* Return value in CR2	156	* Return value in CR2
166	*	157	*
167	* @return Value read.	158	* @return Value read.
168	*/	159	*/
169	static inline __u64 read_cr2(void)	160	static inline __u64 read_cr2(void)
170	{	161	{
171	__u64 v;	162	__u64 v;
172	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));	163	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
173	return v;	164	return v;
174	}	165	}
175		166
176	/** Write CR3	167	/** Write CR3
177	*	168	*
178	* Write value to CR3.	169	* Write value to CR3.
179	*	170	*
180	* @param v Value to be written.	171	* @param v Value to be written.
181	*/	172	*/
182	static inline void write_cr3(__u64 v)	173	static inline void write_cr3(__u64 v)
183	{	174	{
184	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));	175	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
185	}	176	}
186		177
187	/** Read CR3	178	/** Read CR3
188	*	179	*
189	* Return value in CR3	180	* Return value in CR3
190	*	181	*
191	* @return Value read.	182	* @return Value read.
192	*/	183	*/
193	static inline __u64 read_cr3(void)	184	static inline __u64 read_cr3(void)
194	{	185	{
195	__u64 v;	186	__u64 v;
196	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));	187	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));
197	return v;	188	return v;
198	}	189	}
199		190
200		191
201	/** Enable local APIC	192	/** Enable local APIC
202	*	193	*
203	* Enable local APIC in MSR.	194	* Enable local APIC in MSR.
204	*/	195	*/
205	static inline void enable_l_apic_in_msr()	196	static inline void enable_l_apic_in_msr()
206	{	197	{
207	__asm__ volatile (	198	__asm__ volatile (
208	"movl $0x1b, %%ecx\n"	199	"movl $0x1b, %%ecx\n"
209	"rdmsr\n"	200	"rdmsr\n"
210	"orl $(1<<11),%%eax\n"	201	"orl $(1<<11),%%eax\n"
211	"orl $(0xfee00000),%%eax\n"	202	"orl $(0xfee00000),%%eax\n"
212	"wrmsr\n"	203	"wrmsr\n"
213	:	204	:
214	:	205	:
215	:"%eax","%ecx","%edx"	206	:"%eax","%ecx","%edx"
216	);	207	);
217	}	208	}
218		209
219	static inline __address * get_ip()	210	static inline __address * get_ip()
220	{	211	{
221	__address *ip;	212	__address *ip;
222		213
223	__asm__ volatile (	214	__asm__ volatile (
224	"mov %%rip, %0"	215	"mov %%rip, %0"
225	: "=r" (ip)	216	: "=r" (ip)
226	);	217	);
227	return ip;	218	return ip;
228	}	219	}
229		220
230	/** Invalidate TLB Entry.	221	/** Invalidate TLB Entry.
231	*	222	*
232	* @param addr Address on a page whose TLB entry is to be invalidated.	223	* @param addr Address on a page whose TLB entry is to be invalidated.
233	*/	224	*/
234	static inline void invlpg(__address addr)	225	static inline void invlpg(__address addr)
235	{	226	{
236	__asm__ volatile ("invlpg %0\n" :: "m" (addr));	227	__asm__ volatile ("invlpg %0\n" :: "m" (addr));
237	}	228	}
238		229
239	extern size_t interrupt_handler_size;	230	extern size_t interrupt_handler_size;
240	extern void interrupt_handlers(void);	231	extern void interrupt_handlers(void);
241		232
242	#endif	233	#endif
243		234

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(root)/kernel/trunk/arch/amd64/include/asm.h – Rev 597 → 625