WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
extern void asm_delay_loop(__u32 t);
extern void asm_fake_loop(__u32 t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
 
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Swap Hidden part of GS register with visible one */
static inline void swapgs(void) { __asm__ volatile("swapgs"); }
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (ipl)
        );
}
 
/** Return interrupt priority level.
 *
 * Return EFLAFS.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Read CR0
 *
 * Return value in CR0
 *
 * @return Value read.
 */
static inline __u64 read_cr0(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
    return v;
}
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u64 read_cr2(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
    return v;
}
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u64 v)
{
    __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
}
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u64 read_cr3(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr3,%0" : "=r" (v));
    return v;
}
 
/** Write to MSR */
static inline void write_msr(__u32 msr, __u64 value)
{
    __asm__ volatile (
        "wrmsr;" : : "c" (msr),
        "a" ((__u32)(value)),
        "d" ((__u32)(value >> 32))
        );
}
 
static inline __native read_msr(__u32 msr)
{
    __u32 ax, dx;
 
    __asm__ volatile (
        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
        );
    return ((__u64)dx << 32) | ax;
}
 
 
/** Enable local APIC
 *
 * Enable local APIC in MSR.
 */
static inline void enable_l_apic_in_msr()
{
    __asm__ volatile (
        "movl $0x1b, %%ecx\n"
        "rdmsr\n"
        "orl $(1<<11),%%eax\n"
        "orl $(0xfee00000),%%eax\n"
        "wrmsr\n"
        :
        :
        :"%eax","%ecx","%edx"
        );
}
 
static inline __address * get_ip()
{
    __address *ip;
 
    __asm__ volatile (
        "mov %%rip, %0"
        : "=r" (ip)
        );
    return ip;
}
 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(__address addr)
{
        __asm__ volatile ("invlpg %0\n" :: "m" (addr));
}
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 

Rev 803	Rev 806
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __amd64_ASM_H__	29	#ifndef __amd64_ASM_H__
30	#define __amd64_ASM_H__	30	#define __amd64_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35	extern void asm_delay_loop(__u32 t);	35	extern void asm_delay_loop(__u32 t);
36	extern void asm_fake_loop(__u32 t);	36	extern void asm_fake_loop(__u32 t);
37		37
38	/** Return base address of current stack.	38	/** Return base address of current stack.
39	*	39	*
40	* Return the base address of the current stack.	40	* Return the base address of the current stack.
41	* The stack is assumed to be STACK_SIZE bytes long.	41	* The stack is assumed to be STACK_SIZE bytes long.
42	* The stack must start on page boundary.	42	* The stack must start on page boundary.
43	*/	43	*/
44	static inline __address get_stack_base(void)	44	static inline __address get_stack_base(void)
45	{	45	{
46	__address v;	46	__address v;
47		47
48	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	48	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
49		49
50	return v;	50	return v;
51	}	51	}
52		52
53	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };	53	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
54	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };	54	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
55		55
56		56
57	/** Byte from port	57	/** Byte from port
58	*	58	*
59	* Get byte from port	59	* Get byte from port
60	*	60	*
61	* @param port Port to read from	61	* @param port Port to read from
62	* @return Value read	62	* @return Value read
63	*/	63	*/
64	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	64	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
65		65
66	/** Byte to port	66	/** Byte to port
67	*	67	*
68	* Output byte to port	68	* Output byte to port
69	*	69	*
70	* @param port Port to write to	70	* @param port Port to write to
71	* @param val Value to write	71	* @param val Value to write
72	*/	72	*/
73	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	73	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
74		74
-		75	/** Swap Hidden part of GS register with visible one */
-		76	static inline void swapgs(void) { __asm__ volatile("swapgs"); }
-		77
75	/** Enable interrupts.	78	/** Enable interrupts.
76	*	79	*
77	* Enable interrupts and return previous	80	* Enable interrupts and return previous
78	* value of EFLAGS.	81	* value of EFLAGS.
79	*	82	*
80	* @return Old interrupt priority level.	83	* @return Old interrupt priority level.
81	*/	84	*/
82	static inline ipl_t interrupts_enable(void) {	85	static inline ipl_t interrupts_enable(void) {
83	ipl_t v;	86	ipl_t v;
84	__asm__ volatile (	87	__asm__ volatile (
85	"pushfq\n"	88	"pushfq\n"
86	"popq %0\n"	89	"popq %0\n"
87	"sti\n"	90	"sti\n"
88	: "=r" (v)	91	: "=r" (v)
89	);	92	);
90	return v;	93	return v;
91	}	94	}
92		95
93	/** Disable interrupts.	96	/** Disable interrupts.
94	*	97	*
95	* Disable interrupts and return previous	98	* Disable interrupts and return previous
96	* value of EFLAGS.	99	* value of EFLAGS.
97	*	100	*
98	* @return Old interrupt priority level.	101	* @return Old interrupt priority level.
99	*/	102	*/
100	static inline ipl_t interrupts_disable(void) {	103	static inline ipl_t interrupts_disable(void) {
101	ipl_t v;	104	ipl_t v;
102	__asm__ volatile (	105	__asm__ volatile (
103	"pushfq\n"	106	"pushfq\n"
104	"popq %0\n"	107	"popq %0\n"
105	"cli\n"	108	"cli\n"
106	: "=r" (v)	109	: "=r" (v)
107	);	110	);
108	return v;	111	return v;
109	}	112	}
110		113
111	/** Restore interrupt priority level.	114	/** Restore interrupt priority level.
112	*	115	*
113	* Restore EFLAGS.	116	* Restore EFLAGS.
114	*	117	*
115	* @param ipl Saved interrupt priority level.	118	* @param ipl Saved interrupt priority level.
116	*/	119	*/
117	static inline void interrupts_restore(ipl_t ipl) {	120	static inline void interrupts_restore(ipl_t ipl) {
118	__asm__ volatile (	121	__asm__ volatile (
119	"pushq %0\n"	122	"pushq %0\n"
120	"popfq\n"	123	"popfq\n"
121	: : "r" (ipl)	124	: : "r" (ipl)
122	);	125	);
123	}	126	}
124		127
125	/** Return interrupt priority level.	128	/** Return interrupt priority level.
126	*	129	*
127	* Return EFLAFS.	130	* Return EFLAFS.
128	*	131	*
129	* @return Current interrupt priority level.	132	* @return Current interrupt priority level.
130	*/	133	*/
131	static inline ipl_t interrupts_read(void) {	134	static inline ipl_t interrupts_read(void) {
132	ipl_t v;	135	ipl_t v;
133	__asm__ volatile (	136	__asm__ volatile (
134	"pushfq\n"	137	"pushfq\n"
135	"popq %0\n"	138	"popq %0\n"
136	: "=r" (v)	139	: "=r" (v)
137	);	140	);
138	return v;	141	return v;
139	}	142	}
140		143
141	/** Read CR0	144	/** Read CR0
142	*	145	*
143	* Return value in CR0	146	* Return value in CR0
144	*	147	*
145	* @return Value read.	148	* @return Value read.
146	*/	149	*/
147	static inline __u64 read_cr0(void)	150	static inline __u64 read_cr0(void)
148	{	151	{
149	__u64 v;	152	__u64 v;
150	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));	153	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
151	return v;	154	return v;
152	}	155	}
153		156
154	/** Read CR2	157	/** Read CR2
155	*	158	*
156	* Return value in CR2	159	* Return value in CR2
157	*	160	*
158	* @return Value read.	161	* @return Value read.
159	*/	162	*/
160	static inline __u64 read_cr2(void)	163	static inline __u64 read_cr2(void)
161	{	164	{
162	__u64 v;	165	__u64 v;
163	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));	166	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
164	return v;	167	return v;
165	}	168	}
166		169
167	/** Write CR3	170	/** Write CR3
168	*	171	*
169	* Write value to CR3.	172	* Write value to CR3.
170	*	173	*
171	* @param v Value to be written.	174	* @param v Value to be written.
172	*/	175	*/
173	static inline void write_cr3(__u64 v)	176	static inline void write_cr3(__u64 v)
174	{	177	{
175	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));	178	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
176	}	179	}
177		180
178	/** Read CR3	181	/** Read CR3
179	*	182	*
180	* Return value in CR3	183	* Return value in CR3
181	*	184	*
182	* @return Value read.	185	* @return Value read.
183	*/	186	*/
184	static inline __u64 read_cr3(void)	187	static inline __u64 read_cr3(void)
185	{	188	{
186	__u64 v;	189	__u64 v;
187	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));	190	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));
188	return v;	191	return v;
189	}	192	}
190		193
191	/** Write to MSR */	194	/** Write to MSR */
192	static inline void write_msr(__u32 msr, __u64 value)	195	static inline void write_msr(__u32 msr, __u64 value)
193	{	196	{
194	__asm__ volatile (	197	__asm__ volatile (
195	"wrmsr;" : : "c" (msr),	198	"wrmsr;" : : "c" (msr),
196	"a" ((__u32)(value)),	199	"a" ((__u32)(value)),
197	"d" ((__u32)(value >> 32))	200	"d" ((__u32)(value >> 32))
198	);	201	);
199	}	202	}
200		203
201	static inline __native read_msr(__u32 msr)	204	static inline __native read_msr(__u32 msr)
202	{	205	{
203	__u32 ax, dx;	206	__u32 ax, dx;
204		207
205	__asm__ volatile (	208	__asm__ volatile (
206	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)	209	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
207	);	210	);
208	return ((__u64)dx << 32) \| ax;	211	return ((__u64)dx << 32) \| ax;
209	}	212	}
210		213
211		214
212	/** Enable local APIC	215	/** Enable local APIC
213	*	216	*
214	* Enable local APIC in MSR.	217	* Enable local APIC in MSR.
215	*/	218	*/
216	static inline void enable_l_apic_in_msr()	219	static inline void enable_l_apic_in_msr()
217	{	220	{
218	__asm__ volatile (	221	__asm__ volatile (
219	"movl $0x1b, %%ecx\n"	222	"movl $0x1b, %%ecx\n"
220	"rdmsr\n"	223	"rdmsr\n"
221	"orl $(1<<11),%%eax\n"	224	"orl $(1<<11),%%eax\n"
222	"orl $(0xfee00000),%%eax\n"	225	"orl $(0xfee00000),%%eax\n"
223	"wrmsr\n"	226	"wrmsr\n"
224	:	227	:
225	:	228	:
226	:"%eax","%ecx","%edx"	229	:"%eax","%ecx","%edx"
227	);	230	);
228	}	231	}
229		232
230	static inline __address * get_ip()	233	static inline __address * get_ip()
231	{	234	{
232	__address *ip;	235	__address *ip;
233		236
234	__asm__ volatile (	237	__asm__ volatile (
235	"mov %%rip, %0"	238	"mov %%rip, %0"
236	: "=r" (ip)	239	: "=r" (ip)
237	);	240	);
238	return ip;	241	return ip;
239	}	242	}
240		243
241	/** Invalidate TLB Entry.	244	/** Invalidate TLB Entry.
242	*	245	*
243	* @param addr Address on a page whose TLB entry is to be invalidated.	246	* @param addr Address on a page whose TLB entry is to be invalidated.
244	*/	247	*/
245	static inline void invlpg(__address addr)	248	static inline void invlpg(__address addr)
246	{	249	{
247	__asm__ volatile ("invlpg %0\n" :: "m" (addr));	250	__asm__ volatile ("invlpg %0\n" :: "m" (addr));
248	}	251	}
249		252
250	extern size_t interrupt_handler_size;	253	extern size_t interrupt_handler_size;
251	extern void interrupt_handlers(void);	254	extern void interrupt_handlers(void);
252		255
253	#endif	256	#endif
254		257

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(root)/kernel/trunk/arch/amd64/include/asm.h @ 1780 – Rev 803 → 806