WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
extern void asm_delay_loop(__u32 t);
extern void asm_fake_loop(__u32 t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
 
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (ipl)
        );
}
 
/** Return interrupt priority level.
 *
 * Return EFLAFS.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Read CR0
 *
 * Return value in CR0
 *
 * @return Value read.
 */
static inline __u64 read_cr0(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
    return v;
}
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u64 read_cr2(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
    return v;
}
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u64 v)
{
    __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
}
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u64 read_cr3(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr3,%0" : "=r" (v));
    return v;
}
 
/** Write to MSR */
static inline void write_msr(__u32 msr, __u64 value)
{
    __asm__ volatile (
        "wrmsr;" : : "c" (msr),
        "a" ((__u32)(value)),
        "d" ((__u32)(value >> 32))
        );
}
 
static inline __native read_msr(__u32 msr)
{
    __u32 ax, dx;
 
    __asm__ volatile (
        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
        );
    return ((__u64)dx << 32) | ax;
}
 
 
/** Enable local APIC
 *
 * Enable local APIC in MSR.
 */
static inline void enable_l_apic_in_msr()
{
    __asm__ volatile (
        "movl $0x1b, %%ecx\n"
        "rdmsr\n"
        "orl $(1<<11),%%eax\n"
        "orl $(0xfee00000),%%eax\n"
        "wrmsr\n"
        :
        :
        :"%eax","%ecx","%edx"
        );
}
 
static inline __address * get_ip()
{
    __address *ip;
 
    __asm__ volatile (
        "mov %%rip, %0"
        : "=r" (ip)
        );
    return ip;
}
 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(__address addr)
{
        __asm__ volatile ("invlpg %0\n" :: "m" (addr));
}
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 

Rev 625	Rev 803
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __amd64_ASM_H__	29	#ifndef __amd64_ASM_H__
30	#define __amd64_ASM_H__	30	#define __amd64_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35	extern void asm_delay_loop(__u32 t);	35	extern void asm_delay_loop(__u32 t);
36	extern void asm_fake_loop(__u32 t);	36	extern void asm_fake_loop(__u32 t);
37		37
38	/** Return base address of current stack.	38	/** Return base address of current stack.
39	*	39	*
40	* Return the base address of the current stack.	40	* Return the base address of the current stack.
41	* The stack is assumed to be STACK_SIZE bytes long.	41	* The stack is assumed to be STACK_SIZE bytes long.
42	* The stack must start on page boundary.	42	* The stack must start on page boundary.
43	*/	43	*/
44	static inline __address get_stack_base(void)	44	static inline __address get_stack_base(void)
45	{	45	{
46	__address v;	46	__address v;
47		47
48	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	48	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
49		49
50	return v;	50	return v;
51	}	51	}
52		52
53	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };	53	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
54	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };	54	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
55		55
56		56
57	/** Byte from port	57	/** Byte from port
58	*	58	*
59	* Get byte from port	59	* Get byte from port
60	*	60	*
61	* @param port Port to read from	61	* @param port Port to read from
62	* @return Value read	62	* @return Value read
63	*/	63	*/
64	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	64	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
65		65
66	/** Byte to port	66	/** Byte to port
67	*	67	*
68	* Output byte to port	68	* Output byte to port
69	*	69	*
70	* @param port Port to write to	70	* @param port Port to write to
71	* @param val Value to write	71	* @param val Value to write
72	*/	72	*/
73	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	73	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
74		74
75	/** Enable interrupts.	75	/** Enable interrupts.
76	*	76	*
77	* Enable interrupts and return previous	77	* Enable interrupts and return previous
78	* value of EFLAGS.	78	* value of EFLAGS.
79	*	79	*
80	* @return Old interrupt priority level.	80	* @return Old interrupt priority level.
81	*/	81	*/
82	static inline ipl_t interrupts_enable(void) {	82	static inline ipl_t interrupts_enable(void) {
83	ipl_t v;	83	ipl_t v;
84	__asm__ volatile (	84	__asm__ volatile (
85	"pushfq\n"	85	"pushfq\n"
86	"popq %0\n"	86	"popq %0\n"
87	"sti\n"	87	"sti\n"
88	: "=r" (v)	88	: "=r" (v)
89	);	89	);
90	return v;	90	return v;
91	}	91	}
92		92
93	/** Disable interrupts.	93	/** Disable interrupts.
94	*	94	*
95	* Disable interrupts and return previous	95	* Disable interrupts and return previous
96	* value of EFLAGS.	96	* value of EFLAGS.
97	*	97	*
98	* @return Old interrupt priority level.	98	* @return Old interrupt priority level.
99	*/	99	*/
100	static inline ipl_t interrupts_disable(void) {	100	static inline ipl_t interrupts_disable(void) {
101	ipl_t v;	101	ipl_t v;
102	__asm__ volatile (	102	__asm__ volatile (
103	"pushfq\n"	103	"pushfq\n"
104	"popq %0\n"	104	"popq %0\n"
105	"cli\n"	105	"cli\n"
106	: "=r" (v)	106	: "=r" (v)
107	);	107	);
108	return v;	108	return v;
109	}	109	}
110		110
111	/** Restore interrupt priority level.	111	/** Restore interrupt priority level.
112	*	112	*
113	* Restore EFLAGS.	113	* Restore EFLAGS.
114	*	114	*
115	* @param ipl Saved interrupt priority level.	115	* @param ipl Saved interrupt priority level.
116	*/	116	*/
117	static inline void interrupts_restore(ipl_t ipl) {	117	static inline void interrupts_restore(ipl_t ipl) {
118	__asm__ volatile (	118	__asm__ volatile (
119	"pushq %0\n"	119	"pushq %0\n"
120	"popfq\n"	120	"popfq\n"
121	: : "r" (ipl)	121	: : "r" (ipl)
122	);	122	);
123	}	123	}
124		124
125	/** Return interrupt priority level.	125	/** Return interrupt priority level.
126	*	126	*
127	* Return EFLAFS.	127	* Return EFLAFS.
128	*	128	*
129	* @return Current interrupt priority level.	129	* @return Current interrupt priority level.
130	*/	130	*/
131	static inline ipl_t interrupts_read(void) {	131	static inline ipl_t interrupts_read(void) {
132	ipl_t v;	132	ipl_t v;
133	__asm__ volatile (	133	__asm__ volatile (
134	"pushfq\n"	134	"pushfq\n"
135	"popq %0\n"	135	"popq %0\n"
136	: "=r" (v)	136	: "=r" (v)
137	);	137	);
138	return v;	138	return v;
139	}	139	}
140		140
141	/** Read CR0	141	/** Read CR0
142	*	142	*
143	* Return value in CR0	143	* Return value in CR0
144	*	144	*
145	* @return Value read.	145	* @return Value read.
146	*/	146	*/
147	static inline __u64 read_cr0(void)	147	static inline __u64 read_cr0(void)
148	{	148	{
149	__u64 v;	149	__u64 v;
150	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));	150	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
151	return v;	151	return v;
152	}	152	}
153		153
154	/** Read CR2	154	/** Read CR2
155	*	155	*
156	* Return value in CR2	156	* Return value in CR2
157	*	157	*
158	* @return Value read.	158	* @return Value read.
159	*/	159	*/
160	static inline __u64 read_cr2(void)	160	static inline __u64 read_cr2(void)
161	{	161	{
162	__u64 v;	162	__u64 v;
163	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));	163	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
164	return v;	164	return v;
165	}	165	}
166		166
167	/** Write CR3	167	/** Write CR3
168	*	168	*
169	* Write value to CR3.	169	* Write value to CR3.
170	*	170	*
171	* @param v Value to be written.	171	* @param v Value to be written.
172	*/	172	*/
173	static inline void write_cr3(__u64 v)	173	static inline void write_cr3(__u64 v)
174	{	174	{
175	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));	175	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
176	}	176	}
177		177
178	/** Read CR3	178	/** Read CR3
179	*	179	*
180	* Return value in CR3	180	* Return value in CR3
181	*	181	*
182	* @return Value read.	182	* @return Value read.
183	*/	183	*/
184	static inline __u64 read_cr3(void)	184	static inline __u64 read_cr3(void)
185	{	185	{
186	__u64 v;	186	__u64 v;
187	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));	187	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));
188	return v;	188	return v;
189	}	189	}
190		190
-		191	/** Write to MSR */
-		192	static inline void write_msr(__u32 msr, __u64 value)
-		193	{
-		194	__asm__ volatile (
-		195	"wrmsr;" : : "c" (msr),
-		196	"a" ((__u32)(value)),
-		197	"d" ((__u32)(value >> 32))
-		198	);
-		199	}
-		200
-		201	static inline __native read_msr(__u32 msr)
-		202	{
-		203	__u32 ax, dx;
-		204
-		205	__asm__ volatile (
-		206	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
-		207	);
-		208	return ((__u64)dx << 32) \| ax;
-		209	}
-		210
191		211
192	/** Enable local APIC	212	/** Enable local APIC
193	*	213	*
194	* Enable local APIC in MSR.	214	* Enable local APIC in MSR.
195	*/	215	*/
196	static inline void enable_l_apic_in_msr()	216	static inline void enable_l_apic_in_msr()
197	{	217	{
198	__asm__ volatile (	218	__asm__ volatile (
199	"movl $0x1b, %%ecx\n"	219	"movl $0x1b, %%ecx\n"
200	"rdmsr\n"	220	"rdmsr\n"
201	"orl $(1<<11),%%eax\n"	221	"orl $(1<<11),%%eax\n"
202	"orl $(0xfee00000),%%eax\n"	222	"orl $(0xfee00000),%%eax\n"
203	"wrmsr\n"	223	"wrmsr\n"
204	:	224	:
205	:	225	:
206	:"%eax","%ecx","%edx"	226	:"%eax","%ecx","%edx"
207	);	227	);
208	}	228	}
209		229
210	static inline __address * get_ip()	230	static inline __address * get_ip()
211	{	231	{
212	__address *ip;	232	__address *ip;
213		233
214	__asm__ volatile (	234	__asm__ volatile (
215	"mov %%rip, %0"	235	"mov %%rip, %0"
216	: "=r" (ip)	236	: "=r" (ip)
217	);	237	);
218	return ip;	238	return ip;
219	}	239	}
220		240
221	/** Invalidate TLB Entry.	241	/** Invalidate TLB Entry.
222	*	242	*
223	* @param addr Address on a page whose TLB entry is to be invalidated.	243	* @param addr Address on a page whose TLB entry is to be invalidated.
224	*/	244	*/
225	static inline void invlpg(__address addr)	245	static inline void invlpg(__address addr)
226	{	246	{
227	__asm__ volatile ("invlpg %0\n" :: "m" (addr));	247	__asm__ volatile ("invlpg %0\n" :: "m" (addr));
228	}	248	}
229		249
230	extern size_t interrupt_handler_size;	250	extern size_t interrupt_handler_size;
231	extern void interrupt_handlers(void);	251	extern void interrupt_handlers(void);
232		252
233	#endif	253	#endif
234		254

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(root)/kernel/trunk/arch/amd64/include/asm.h @ 1780 – Rev 625 → 803