WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
 
void asm_delay_loop(__u32 t);
void asm_fake_loop(__u32 t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
 
 
static inline __u8 inb(__u16 port)
{
    __u8 out;
 
    __asm__ volatile (
        "mov %1, %%dx\n"
        "inb %%dx,%%al\n"
        "mov %%al, %0\n"
        :"=m"(out)
        :"m"(port)
        :"%rdx","%rax"
        );
    return out;
}
 
static inline __u8 outb(__u16 port,__u8 b)
{
    __asm__ volatile (
        "mov %0,%%dx\n"
        "mov %1,%%al\n"
        "outb %%al,%%dx\n"
        :
        :"m"( port), "m" (b)
        :"%rdx","%rax"
        );
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (ipl)
        );
}
 
/** Return interrupt priority level.
 *
 * Return EFLAFS.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Read CR0
 *
 * Return value in CR0
 *
 * @return Value read.
 */
static inline __u64 read_cr0(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
    return v;
}
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u64 read_cr2(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
    return v;
}
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u64 v)
{
    __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
}
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u64 read_cr3(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr3,%0" : "=r" (v));
    return v;
}
 
 
/** Enable local APIC
 *
 * Enable local APIC in MSR.
 */
static inline void enable_l_apic_in_msr()
{
    __asm__ volatile (
        "movl $0x1b, %%ecx\n"
        "rdmsr\n"
        "orl $(1<<11),%%eax\n"
        "orl $(0xfee00000),%%eax\n"
        "wrmsr\n"
        :
        :
        :"%eax","%ecx","%edx"
        );
}
 
static inline __address * get_ip()
{
    __address *ip;
 
    __asm__ volatile (
        "mov %%rip, %0"
        : "=r" (ip)
        );
    return ip;
}
 
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 

Rev 534	Rev 581
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __amd64_ASM_H__	29	#ifndef __amd64_ASM_H__
30	#define __amd64_ASM_H__	30	#define __amd64_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35		35
36	void asm_delay_loop(__u32 t);	36	void asm_delay_loop(__u32 t);
37	void asm_fake_loop(__u32 t);	37	void asm_fake_loop(__u32 t);
38		38
39	/** Return base address of current stack.	39	/** Return base address of current stack.
40	*	40	*
41	* Return the base address of the current stack.	41	* Return the base address of the current stack.
42	* The stack is assumed to be STACK_SIZE bytes long.	42	* The stack is assumed to be STACK_SIZE bytes long.
43	* The stack must start on page boundary.	43	* The stack must start on page boundary.
44	*/	44	*/
45	static inline __address get_stack_base(void)	45	static inline __address get_stack_base(void)
46	{	46	{
47	__address v;	47	__address v;
48		48
49	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	49	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
50		50
51	return v;	51	return v;
52	}	52	}
53		53
54	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };	54	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
55	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };	55	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
56		56
57		57
58	static inline __u8 inb(__u16 port)	58	static inline __u8 inb(__u16 port)
59	{	59	{
60	__u8 out;	60	__u8 out;
61		61
62	__asm__ volatile (	62	__asm__ volatile (
63	"mov %1, %%dx\n"	63	"mov %1, %%dx\n"
64	"inb %%dx,%%al\n"	64	"inb %%dx,%%al\n"
65	"mov %%al, %0\n"	65	"mov %%al, %0\n"
66	:"=m"(out)	66	:"=m"(out)
67	:"m"(port)	67	:"m"(port)
68	:"%rdx","%rax"	68	:"%rdx","%rax"
69	);	69	);
70	return out;	70	return out;
71	}	71	}
72		72
73	static inline __u8 outb(__u16 port,__u8 b)	73	static inline __u8 outb(__u16 port,__u8 b)
74	{	74	{
75	__asm__ volatile (	75	__asm__ volatile (
76	"mov %0,%%dx\n"	76	"mov %0,%%dx\n"
77	"mov %1,%%al\n"	77	"mov %1,%%al\n"
78	"outb %%al,%%dx\n"	78	"outb %%al,%%dx\n"
79	:	79	:
80	:"m"( port), "m" (b)	80	:"m"( port), "m" (b)
81	:"%rdx","%rax"	81	:"%rdx","%rax"
82	);	82	);
83	}	83	}
84		84
85	/** Enable interrupts.	85	/** Enable interrupts.
86	*	86	*
87	* Enable interrupts and return previous	87	* Enable interrupts and return previous
88	* value of EFLAGS.	88	* value of EFLAGS.
89	*	89	*
90	* @return Old interrupt priority level.	90	* @return Old interrupt priority level.
91	*/	91	*/
92	static inline ipl_t interrupts_enable(void) {	92	static inline ipl_t interrupts_enable(void) {
93	ipl_t v;	93	ipl_t v;
94	__asm__ volatile (	94	__asm__ volatile (
95	"pushfq\n"	95	"pushfq\n"
96	"popq %0\n"	96	"popq %0\n"
97	"sti\n"	97	"sti\n"
98	: "=r" (v)	98	: "=r" (v)
99	);	99	);
100	return v;	100	return v;
101	}	101	}
102		102
103	/** Disable interrupts.	103	/** Disable interrupts.
104	*	104	*
105	* Disable interrupts and return previous	105	* Disable interrupts and return previous
106	* value of EFLAGS.	106	* value of EFLAGS.
107	*	107	*
108	* @return Old interrupt priority level.	108	* @return Old interrupt priority level.
109	*/	109	*/
110	static inline ipl_t interrupts_disable(void) {	110	static inline ipl_t interrupts_disable(void) {
111	ipl_t v;	111	ipl_t v;
112	__asm__ volatile (	112	__asm__ volatile (
113	"pushfq\n"	113	"pushfq\n"
114	"popq %0\n"	114	"popq %0\n"
115	"cli\n"	115	"cli\n"
116	: "=r" (v)	116	: "=r" (v)
117	);	117	);
118	return v;	118	return v;
119	}	119	}
120		120
121	/** Restore interrupt priority level.	121	/** Restore interrupt priority level.
122	*	122	*
123	* Restore EFLAGS.	123	* Restore EFLAGS.
124	*	124	*
125	* @param ipl Saved interrupt priority level.	125	* @param ipl Saved interrupt priority level.
126	*/	126	*/
127	static inline void interrupts_restore(ipl_t ipl) {	127	static inline void interrupts_restore(ipl_t ipl) {
128	__asm__ volatile (	128	__asm__ volatile (
129	"pushq %0\n"	129	"pushq %0\n"
130	"popfq\n"	130	"popfq\n"
131	: : "r" (ipl)	131	: : "r" (ipl)
132	);	132	);
133	}	133	}
134		134
135	/** Return interrupt priority level.	135	/** Return interrupt priority level.
136	*	136	*
137	* Return EFLAFS.	137	* Return EFLAFS.
138	*	138	*
139	* @return Current interrupt priority level.	139	* @return Current interrupt priority level.
140	*/	140	*/
141	static inline ipl_t interrupts_read(void) {	141	static inline ipl_t interrupts_read(void) {
142	ipl_t v;	142	ipl_t v;
143	__asm__ volatile (	143	__asm__ volatile (
144	"pushfq\n"	144	"pushfq\n"
145	"popq %0\n"	145	"popq %0\n"
146	: "=r" (v)	146	: "=r" (v)
147	);	147	);
148	return v;	148	return v;
149	}	149	}
150		150
151	/** Read CR0	151	/** Read CR0
152	*	152	*
153	* Return value in CR0	153	* Return value in CR0
154	*	154	*
155	* @return Value read.	155	* @return Value read.
156	*/	156	*/
157	static inline __u64 read_cr0(void)	157	static inline __u64 read_cr0(void)
158	{	158	{
159	__u64 v;	159	__u64 v;
160	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));	160	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
161	return v;	161	return v;
162	}	162	}
163		163
164	/** Read CR2	164	/** Read CR2
165	*	165	*
166	* Return value in CR2	166	* Return value in CR2
167	*	167	*
168	* @return Value read.	168	* @return Value read.
169	*/	169	*/
170	static inline __u64 read_cr2(void)	170	static inline __u64 read_cr2(void)
171	{	171	{
172	__u64 v;	172	__u64 v;
173	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));	173	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
174	return v;	174	return v;
175	}	175	}
176		176
177	/** Write CR3	177	/** Write CR3
178	*	178	*
179	* Write value to CR3.	179	* Write value to CR3.
180	*	180	*
181	* @param v Value to be written.	181	* @param v Value to be written.
182	*/	182	*/
183	static inline void write_cr3(__u64 v)	183	static inline void write_cr3(__u64 v)
184	{	184	{
185	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));	185	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
186	}	186	}
187		187
188	/** Read CR3	188	/** Read CR3
189	*	189	*
190	* Return value in CR3	190	* Return value in CR3
191	*	191	*
192	* @return Value read.	192	* @return Value read.
193	*/	193	*/
194	static inline __u64 read_cr3(void)	194	static inline __u64 read_cr3(void)
195	{	195	{
196	__u64 v;	196	__u64 v;
197	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));	197	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));
198	return v;	198	return v;
199	}	199	}
200		200
201		201
202	/** Enable local APIC	202	/** Enable local APIC
203	*	203	*
204	* Enable local APIC in MSR.	204	* Enable local APIC in MSR.
205	*/	205	*/
206	static inline void enable_l_apic_in_msr()	206	static inline void enable_l_apic_in_msr()
207	{	207	{
208	__asm__ volatile (	208	__asm__ volatile (
209	"movl $0x1b, %%ecx\n"	209	"movl $0x1b, %%ecx\n"
210	"rdmsr\n"	210	"rdmsr\n"
211	"orl $(1<<11),%%eax\n"	211	"orl $(1<<11),%%eax\n"
212	"orl $(0xfee00000),%%eax\n"	212	"orl $(0xfee00000),%%eax\n"
213	"wrmsr\n"	213	"wrmsr\n"
214	:	214	:
215	:	215	:
216	:"%eax","%ecx","%edx"	216	:"%eax","%ecx","%edx"
217	);	217	);
218	}	218	}
219		219
-		220	static inline __address * get_ip()
-		221	{
-		222	__address *ip;
-		223
-		224	__asm__ volatile (
-		225	"mov %%rip, %0"
-		226	: "=r" (ip)
-		227	);
-		228	return ip;
-		229	}
-		230
-		231
220	extern size_t interrupt_handler_size;	232	extern size_t interrupt_handler_size;
221	extern void interrupt_handlers(void);	233	extern void interrupt_handlers(void);
222		234
223	#endif	235	#endif
224		236

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