WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
 
void asm_delay_loop(__u32 t);
void asm_fake_loop(__u32 t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
 
 
static inline __u8 inb(__u16 port)
{
    __u8 out;
 
    __asm__ volatile (
        "mov %1, %%dx\n"
        "inb %%dx,%%al\n"
        "mov %%al, %0\n"
        :"=m"(out)
        :"m"(port)
        :"%rdx","%rax"
        );
    return out;
}
 
static inline __u8 outb(__u16 port,__u8 b)
{
    __asm__ volatile (
        "mov %0,%%dx\n"
        "mov %1,%%al\n"
        "outb %%al,%%dx\n"
        :
        :"m"( port), "m" (b)
        :"%rdx","%rax"
        );
}
 
/** Set priority level low
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_low(void) {
    pri_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Set priority level high
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_high(void) {
    pri_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore priority level
 *
 * Restore EFLAGS.
 */
static inline void cpu_priority_restore(pri_t pri) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (pri)
        );
}
 
/** Return raw priority level
 *
 * Return EFLAFS.
 */
static inline pri_t cpu_priority_read(void) {
    pri_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Read CR0
 *
 * Return value in CR0
 *
 * @return Value read.
 */
static inline __u64 read_cr0(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
    return v;
}
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u64 read_cr2(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
    return v;
}
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u64 v)
{
    __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
}
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u64 read_cr3(void)
{
    __u64 v;
    __asm__ volatile ("movq %%cr3,%0" : "=r" (v));
    return v;
}
 
 
/** Enable local APIC
 *
 * Enable local APIC in MSR.
 */
static inline void enable_l_apic_in_msr()
{
    __asm__ volatile (
        "movl $0x1b, %%ecx\n"
        "rdmsr\n"
        "orl $(1<<11),%%eax\n"
        "orl $(0xfee00000),%%eax\n"
        "wrmsr\n"
        :
        :
        :"%eax","%ecx","%edx"
        );
}
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 

Rev 282	Rev 348
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __amd64_ASM_H__	29	#ifndef __amd64_ASM_H__
30	#define __amd64_ASM_H__	30	#define __amd64_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35		35
36	void asm_delay_loop(__u32 t);	36	void asm_delay_loop(__u32 t);
37	void asm_fake_loop(__u32 t);	37	void asm_fake_loop(__u32 t);
38		38
39	/** Return base address of current stack.	39	/** Return base address of current stack.
40	*	40	*
41	* Return the base address of the current stack.	41	* Return the base address of the current stack.
42	* The stack is assumed to be STACK_SIZE bytes long.	42	* The stack is assumed to be STACK_SIZE bytes long.
43	* The stack must start on page boundary.	43	* The stack must start on page boundary.
44	*/	44	*/
45	static inline __address get_stack_base(void)	45	static inline __address get_stack_base(void)
46	{	46	{
47	__address v;	47	__address v;
48		48
49	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	49	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
50		50
51	return v;	51	return v;
52	}	52	}
53		53
54	static inline void cpu_sleep(void) { __asm__ volatile ("hlt"); };	54	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
55	static inline void cpu_halt(void) { __asm__ volatile ("hlt"); };	55	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
56		56
57		57
58	static inline __u8 inb(__u16 port)	58	static inline __u8 inb(__u16 port)
59	{	59	{
60	__u8 out;	60	__u8 out;
61		61
62	__asm__ volatile (	62	__asm__ volatile (
63	"mov %1, %%dx;"	63	"mov %1, %%dx\n"
64	"inb %%dx,%%al;"	64	"inb %%dx,%%al\n"
65	"mov %%al, %0;"	65	"mov %%al, %0\n"
66	:"=m"(out)	66	:"=m"(out)
67	:"m"(port)	67	:"m"(port)
68	:"%rdx","%rax"	68	:"%rdx","%rax"
69	);	69	);
70	return out;	70	return out;
71	}	71	}
72		72
73	static inline __u8 outb(__u16 port,__u8 b)	73	static inline __u8 outb(__u16 port,__u8 b)
74	{	74	{
75	__asm__ volatile (	75	__asm__ volatile (
76	"mov %0,%%dx;"	76	"mov %0,%%dx\n"
77	"mov %1,%%al;"	77	"mov %1,%%al\n"
78	"outb %%al,%%dx;"	78	"outb %%al,%%dx\n"
79	:	79	:
80	:"m"( port), "m" (b)	80	:"m"( port), "m" (b)
81	:"%rdx","%rax"	81	:"%rdx","%rax"
82	);	82	);
83	}	83	}
84		84
85	/** Set priority level low	85	/** Set priority level low
86	*	86	*
87	* Enable interrupts and return previous	87	* Enable interrupts and return previous
88	* value of EFLAGS.	88	* value of EFLAGS.
89	*/	89	*/
90	static inline pri_t cpu_priority_low(void) {	90	static inline pri_t cpu_priority_low(void) {
91	pri_t v;	91	pri_t v;
92	__asm__ volatile (	92	__asm__ volatile (
93	"pushfq\n"	93	"pushfq\n"
94	"popq %0\n"	94	"popq %0\n"
95	"sti\n"	95	"sti\n"
96	: "=r" (v)	96	: "=r" (v)
97	);	97	);
98	return v;	98	return v;
99	}	99	}
100		100
101	/** Set priority level high	101	/** Set priority level high
102	*	102	*
103	* Disable interrupts and return previous	103	* Disable interrupts and return previous
104	* value of EFLAGS.	104	* value of EFLAGS.
105	*/	105	*/
106	static inline pri_t cpu_priority_high(void) {	106	static inline pri_t cpu_priority_high(void) {
107	pri_t v;	107	pri_t v;
108	__asm__ volatile (	108	__asm__ volatile (
109	"pushfq\n"	109	"pushfq\n"
110	"popq %0\n"	110	"popq %0\n"
111	"cli\n"	111	"cli\n"
112	: "=r" (v)	112	: "=r" (v)
113	);	113	);
114	return v;	114	return v;
115	}	115	}
116		116
117	/** Restore priority level	117	/** Restore priority level
118	*	118	*
119	* Restore EFLAGS.	119	* Restore EFLAGS.
120	*/	120	*/
121	static inline void cpu_priority_restore(pri_t pri) {	121	static inline void cpu_priority_restore(pri_t pri) {
122	__asm__ volatile (	122	__asm__ volatile (
123	"pushq %0\n"	123	"pushq %0\n"
124	"popfq\n"	124	"popfq\n"
125	: : "r" (pri)	125	: : "r" (pri)
126	);	126	);
127	}	127	}
128		128
129	/** Return raw priority level	129	/** Return raw priority level
130	*	130	*
131	* Return EFLAFS.	131	* Return EFLAFS.
132	*/	132	*/
133	static inline pri_t cpu_priority_read(void) {	133	static inline pri_t cpu_priority_read(void) {
134	pri_t v;	134	pri_t v;
135	__asm__ volatile (	135	__asm__ volatile (
136	"pushfq\n"	136	"pushfq\n"
137	"popq %0\n"	137	"popq %0\n"
138	: "=r" (v)	138	: "=r" (v)
139	);	139	);
140	return v;	140	return v;
141	}	141	}
142		142
143	/** Read CR0	143	/** Read CR0
144	*	144	*
145	* Return value in CR0	145	* Return value in CR0
146	*	146	*
147	* @return Value read.	147	* @return Value read.
148	*/	148	*/
149	static inline __u64 read_cr0(void)	149	static inline __u64 read_cr0(void)
150	{	150	{
151	__u64 v;	151	__u64 v;
152	__asm__ volatile ("movq %%cr0,%0" : "=r" (v));	152	__asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
153	return v;	153	return v;
154	}	154	}
155		155
156	/** Read CR2	156	/** Read CR2
157	*	157	*
158	* Return value in CR2	158	* Return value in CR2
159	*	159	*
160	* @return Value read.	160	* @return Value read.
161	*/	161	*/
162	static inline __u64 read_cr2(void)	162	static inline __u64 read_cr2(void)
163	{	163	{
164	__u64 v;	164	__u64 v;
165	__asm__ volatile ("movq %%cr2,%0" : "=r" (v));	165	__asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
166	return v;	166	return v;
167	}	167	}
168		168
169	/** Write CR3	169	/** Write CR3
170	*	170	*
171	* Write value to CR3.	171	* Write value to CR3.
172	*	172	*
173	* @param v Value to be written.	173	* @param v Value to be written.
174	*/	174	*/
175	static inline void write_cr3(__u64 v)	175	static inline void write_cr3(__u64 v)
176	{	176	{
177	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));	177	__asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
178	}	178	}
179		179
180	/** Read CR3	180	/** Read CR3
181	*	181	*
182	* Return value in CR3	182	* Return value in CR3
183	*	183	*
184	* @return Value read.	184	* @return Value read.
185	*/	185	*/
186	static inline __u64 read_cr3(void)	186	static inline __u64 read_cr3(void)
187	{	187	{
188	__u64 v;	188	__u64 v;
189	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));	189	__asm__ volatile ("movq %%cr3,%0" : "=r" (v));
190	return v;	190	return v;
191	}	191	}
192		192
193		193
194	/** Enable local APIC	194	/** Enable local APIC
195	*	195	*
196	* Enable local APIC in MSR.	196	* Enable local APIC in MSR.
197	*/	197	*/
198	static inline void enable_l_apic_in_msr()	198	static inline void enable_l_apic_in_msr()
199	{	199	{
200	__asm__ volatile (	200	__asm__ volatile (
201	"movl $0x1b, %%ecx;"	201	"movl $0x1b, %%ecx\n"
202	"rdmsr;"	202	"rdmsr\n"
203	"orl $(1<<11),%%eax;"	203	"orl $(1<<11),%%eax\n"
204	"orl $(0xfee00000),%%eax;"	204	"orl $(0xfee00000),%%eax\n"
205	"wrmsr;"	205	"wrmsr\n"
206	:	206	:
207	:	207	:
208	:"%eax","%ecx","%edx"	208	:"%eax","%ecx","%edx"
209	);	209	);
210	}	210	}
211		211
212	extern size_t interrupt_handler_size;	212	extern size_t interrupt_handler_size;
213	extern void interrupt_handlers(void);	213	extern void interrupt_handlers(void);
214		214
215	#endif	215	#endif
216		216

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(root)/kernel/trunk/arch/amd64/include/asm.h @ 1780 – Rev 282 → 348