WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
 
extern void asm_delay_loop(__u32 t);
extern void asm_fake_loop(__u32 t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
 
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Swap Hidden part of GS register with visible one */
static inline void swapgs(void) { __asm__ volatile("swapgs"); }
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (ipl)
        );
}
 
/** Return interrupt priority level.
 *
 * Return EFLAFS.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Write to MSR */
static inline void write_msr(__u32 msr, __u64 value)
{
    __asm__ volatile (
        "wrmsr;" : : "c" (msr),
        "a" ((__u32)(value)),
        "d" ((__u32)(value >> 32))
        );
}
 
static inline __native read_msr(__u32 msr)
{
    __u32 ax, dx;
 
    __asm__ volatile (
        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
        );
    return ((__u64)dx << 32) | ax;
}
 
 
/** Enable local APIC
 *
 * Enable local APIC in MSR.
 */
static inline void enable_l_apic_in_msr()
{
    __asm__ volatile (
        "movl $0x1b, %%ecx\n"
        "rdmsr\n"
        "orl $(1<<11),%%eax\n"
        "orl $(0xfee00000),%%eax\n"
        "wrmsr\n"
        :
        :
        :"%eax","%ecx","%edx"
        );
}
 
static inline __address * get_ip()
{
    __address *ip;
 
    __asm__ volatile (
        "mov %%rip, %0"
        : "=r" (ip)
        );
    return ip;
}
 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(__address addr)
{
    __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
}
 
/** Load GDTR register from memory.
 *
 * @param gdtr_reg Address of memory from where to load GDTR.
 */
static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
{
    __asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
}
 
/** Store GDTR register to memory.
 *
 * @param gdtr_reg Address of memory to where to load GDTR.
 */
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
{
    __asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
}
 
/** Load IDTR register from memory.
 *
 * @param idtr_reg Address of memory from where to load IDTR.
 */
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
{
    __asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
}
 
/** Load TR from descriptor table.
 *
 * @param sel Selector specifying descriptor of TSS segment.
 */
static inline void tr_load(__u16 sel)
{
    __asm__ volatile ("ltr %0" : : "r" (sel));
}
 
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
    { \
    __native res; \
    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
    return res; \
    }
 
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
    { \
    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
    }
 
GEN_READ_REG(cr0);
GEN_READ_REG(cr2);
GEN_READ_REG(cr3);
GEN_WRITE_REG(cr3);
 
GEN_READ_REG(dr0);
GEN_READ_REG(dr1);
GEN_READ_REG(dr2);
GEN_READ_REG(dr3);
GEN_READ_REG(dr6);
GEN_READ_REG(dr7);
 
GEN_WRITE_REG(dr0);
GEN_WRITE_REG(dr1);
GEN_WRITE_REG(dr2);
GEN_WRITE_REG(dr3);
GEN_WRITE_REG(dr6);
GEN_WRITE_REG(dr7);
 
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 

Rev 1072	Rev 1186
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __amd64_ASM_H__	29	#ifndef __amd64_ASM_H__
30	#define __amd64_ASM_H__	30	#define __amd64_ASM_H__
31		31
-		32	#include <arch/pm.h>
32	#include <arch/types.h>	33	#include <arch/types.h>
33	#include <config.h>	34	#include <config.h>
34		35
35	extern void asm_delay_loop(__u32 t);	36	extern void asm_delay_loop(__u32 t);
36	extern void asm_fake_loop(__u32 t);	37	extern void asm_fake_loop(__u32 t);
37		38
38	/** Return base address of current stack.	39	/** Return base address of current stack.
39	*	40	*
40	* Return the base address of the current stack.	41	* Return the base address of the current stack.
41	* The stack is assumed to be STACK_SIZE bytes long.	42	* The stack is assumed to be STACK_SIZE bytes long.
42	* The stack must start on page boundary.	43	* The stack must start on page boundary.
43	*/	44	*/
44	static inline __address get_stack_base(void)	45	static inline __address get_stack_base(void)
45	{	46	{
46	__address v;	47	__address v;
47		48
48	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	49	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
49		50
50	return v;	51	return v;
51	}	52	}
52		53
53	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };	54	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
54	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };	55	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
55		56
56		57
57	/** Byte from port	58	/** Byte from port
58	*	59	*
59	* Get byte from port	60	* Get byte from port
60	*	61	*
61	* @param port Port to read from	62	* @param port Port to read from
62	* @return Value read	63	* @return Value read
63	*/	64	*/
64	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	65	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
65		66
66	/** Byte to port	67	/** Byte to port
67	*	68	*
68	* Output byte to port	69	* Output byte to port
69	*	70	*
70	* @param port Port to write to	71	* @param port Port to write to
71	* @param val Value to write	72	* @param val Value to write
72	*/	73	*/
73	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	74	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
74		75
75	/** Swap Hidden part of GS register with visible one */	76	/** Swap Hidden part of GS register with visible one */
76	static inline void swapgs(void) { __asm__ volatile("swapgs"); }	77	static inline void swapgs(void) { __asm__ volatile("swapgs"); }
77		78
78	/** Enable interrupts.	79	/** Enable interrupts.
79	*	80	*
80	* Enable interrupts and return previous	81	* Enable interrupts and return previous
81	* value of EFLAGS.	82	* value of EFLAGS.
82	*	83	*
83	* @return Old interrupt priority level.	84	* @return Old interrupt priority level.
84	*/	85	*/
85	static inline ipl_t interrupts_enable(void) {	86	static inline ipl_t interrupts_enable(void) {
86	ipl_t v;	87	ipl_t v;
87	__asm__ volatile (	88	__asm__ volatile (
88	"pushfq\n"	89	"pushfq\n"
89	"popq %0\n"	90	"popq %0\n"
90	"sti\n"	91	"sti\n"
91	: "=r" (v)	92	: "=r" (v)
92	);	93	);
93	return v;	94	return v;
94	}	95	}
95		96
96	/** Disable interrupts.	97	/** Disable interrupts.
97	*	98	*
98	* Disable interrupts and return previous	99	* Disable interrupts and return previous
99	* value of EFLAGS.	100	* value of EFLAGS.
100	*	101	*
101	* @return Old interrupt priority level.	102	* @return Old interrupt priority level.
102	*/	103	*/
103	static inline ipl_t interrupts_disable(void) {	104	static inline ipl_t interrupts_disable(void) {
104	ipl_t v;	105	ipl_t v;
105	__asm__ volatile (	106	__asm__ volatile (
106	"pushfq\n"	107	"pushfq\n"
107	"popq %0\n"	108	"popq %0\n"
108	"cli\n"	109	"cli\n"
109	: "=r" (v)	110	: "=r" (v)
110	);	111	);
111	return v;	112	return v;
112	}	113	}
113		114
114	/** Restore interrupt priority level.	115	/** Restore interrupt priority level.
115	*	116	*
116	* Restore EFLAGS.	117	* Restore EFLAGS.
117	*	118	*
118	* @param ipl Saved interrupt priority level.	119	* @param ipl Saved interrupt priority level.
119	*/	120	*/
120	static inline void interrupts_restore(ipl_t ipl) {	121	static inline void interrupts_restore(ipl_t ipl) {
121	__asm__ volatile (	122	__asm__ volatile (
122	"pushq %0\n"	123	"pushq %0\n"
123	"popfq\n"	124	"popfq\n"
124	: : "r" (ipl)	125	: : "r" (ipl)
125	);	126	);
126	}	127	}
127		128
128	/** Return interrupt priority level.	129	/** Return interrupt priority level.
129	*	130	*
130	* Return EFLAFS.	131	* Return EFLAFS.
131	*	132	*
132	* @return Current interrupt priority level.	133	* @return Current interrupt priority level.
133	*/	134	*/
134	static inline ipl_t interrupts_read(void) {	135	static inline ipl_t interrupts_read(void) {
135	ipl_t v;	136	ipl_t v;
136	__asm__ volatile (	137	__asm__ volatile (
137	"pushfq\n"	138	"pushfq\n"
138	"popq %0\n"	139	"popq %0\n"
139	: "=r" (v)	140	: "=r" (v)
140	);	141	);
141	return v;	142	return v;
142	}	143	}
143		144
144	/** Write to MSR */	145	/** Write to MSR */
145	static inline void write_msr(__u32 msr, __u64 value)	146	static inline void write_msr(__u32 msr, __u64 value)
146	{	147	{
147	__asm__ volatile (	148	__asm__ volatile (
148	"wrmsr;" : : "c" (msr),	149	"wrmsr;" : : "c" (msr),
149	"a" ((__u32)(value)),	150	"a" ((__u32)(value)),
150	"d" ((__u32)(value >> 32))	151	"d" ((__u32)(value >> 32))
151	);	152	);
152	}	153	}
153		154
154	static inline __native read_msr(__u32 msr)	155	static inline __native read_msr(__u32 msr)
155	{	156	{
156	__u32 ax, dx;	157	__u32 ax, dx;
157		158
158	__asm__ volatile (	159	__asm__ volatile (
159	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)	160	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
160	);	161	);
161	return ((__u64)dx << 32) \| ax;	162	return ((__u64)dx << 32) \| ax;
162	}	163	}
163		164
164		165
165	/** Enable local APIC	166	/** Enable local APIC
166	*	167	*
167	* Enable local APIC in MSR.	168	* Enable local APIC in MSR.
168	*/	169	*/
169	static inline void enable_l_apic_in_msr()	170	static inline void enable_l_apic_in_msr()
170	{	171	{
171	__asm__ volatile (	172	__asm__ volatile (
172	"movl $0x1b, %%ecx\n"	173	"movl $0x1b, %%ecx\n"
173	"rdmsr\n"	174	"rdmsr\n"
174	"orl $(1<<11),%%eax\n"	175	"orl $(1<<11),%%eax\n"
175	"orl $(0xfee00000),%%eax\n"	176	"orl $(0xfee00000),%%eax\n"
176	"wrmsr\n"	177	"wrmsr\n"
177	:	178	:
178	:	179	:
179	:"%eax","%ecx","%edx"	180	:"%eax","%ecx","%edx"
180	);	181	);
181	}	182	}
182		183
183	static inline __address * get_ip()	184	static inline __address * get_ip()
184	{	185	{
185	__address *ip;	186	__address *ip;
186		187
187	__asm__ volatile (	188	__asm__ volatile (
188	"mov %%rip, %0"	189	"mov %%rip, %0"
189	: "=r" (ip)	190	: "=r" (ip)
190	);	191	);
191	return ip;	192	return ip;
192	}	193	}
193		194
194	/** Invalidate TLB Entry.	195	/** Invalidate TLB Entry.
195	*	196	*
196	* @param addr Address on a page whose TLB entry is to be invalidated.	197	* @param addr Address on a page whose TLB entry is to be invalidated.
197	*/	198	*/
198	static inline void invlpg(__address addr)	199	static inline void invlpg(__address addr)
199	{	200	{
200	__asm__ volatile ("invlpg %0\n" :: "m" (((__native )addr)));	201	__asm__ volatile ("invlpg %0\n" :: "m" (((__native )addr)));
-		202	}
-		203
-		204	/** Load GDTR register from memory.
-		205	*
-		206	* @param gdtr_reg Address of memory from where to load GDTR.
-		207	*/
-		208	static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
-		209	{
-		210	__asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
-		211	}
-		212
-		213	/** Store GDTR register to memory.
-		214	*
-		215	* @param gdtr_reg Address of memory to where to load GDTR.
-		216	*/
-		217	static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
-		218	{
-		219	__asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
-		220	}
-		221
-		222	/** Load IDTR register from memory.
-		223	*
-		224	* @param idtr_reg Address of memory from where to load IDTR.
-		225	*/
-		226	static inline void idtr_load(struct ptr_16_64 *idtr_reg)
-		227	{
-		228	__asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
-		229	}
-		230
-		231	/** Load TR from descriptor table.
-		232	*
-		233	* @param sel Selector specifying descriptor of TSS segment.
-		234	*/
-		235	static inline void tr_load(__u16 sel)
-		236	{
-		237	__asm__ volatile ("ltr %0" : : "r" (sel));
201	}	238	}
202		239
203	#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \	240	#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
204	{ \	241	{ \
205	__native res; \	242	__native res; \
206	__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \	243	__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
207	return res; \	244	return res; \
208	}	245	}
209		246
210	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \	247	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
211	{ \	248	{ \
212	__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \	249	__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
213	}	250	}
214		251
215	GEN_READ_REG(cr0);	252	GEN_READ_REG(cr0);
216	GEN_READ_REG(cr2);	253	GEN_READ_REG(cr2);
217	GEN_READ_REG(cr3);	254	GEN_READ_REG(cr3);
218	GEN_WRITE_REG(cr3);	255	GEN_WRITE_REG(cr3);
219		256
220	GEN_READ_REG(dr0);	257	GEN_READ_REG(dr0);
221	GEN_READ_REG(dr1);	258	GEN_READ_REG(dr1);
222	GEN_READ_REG(dr2);	259	GEN_READ_REG(dr2);
223	GEN_READ_REG(dr3);	260	GEN_READ_REG(dr3);
224	GEN_READ_REG(dr6);	261	GEN_READ_REG(dr6);
225	GEN_READ_REG(dr7);	262	GEN_READ_REG(dr7);
226		263
227	GEN_WRITE_REG(dr0);	264	GEN_WRITE_REG(dr0);
228	GEN_WRITE_REG(dr1);	265	GEN_WRITE_REG(dr1);
229	GEN_WRITE_REG(dr2);	266	GEN_WRITE_REG(dr2);
230	GEN_WRITE_REG(dr3);	267	GEN_WRITE_REG(dr3);
231	GEN_WRITE_REG(dr6);	268	GEN_WRITE_REG(dr6);
232	GEN_WRITE_REG(dr7);	269	GEN_WRITE_REG(dr7);
233		270
234		271
235	extern size_t interrupt_handler_size;	272	extern size_t interrupt_handler_size;
236	extern void interrupt_handlers(void);	273	extern void interrupt_handlers(void);
237		274
238	#endif	275	#endif
239		276

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/include/asm.h @ 1780 – Rev 1072 → 1186