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<?xml version="1.0" encoding="UTF-8"?>
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<?xml version="1.0" encoding="UTF-8"?>
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<appendix id="archspecs">
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<appendix id="archspecs">
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  <?dbhtml filename="arch.html"?>
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  <?dbhtml filename="arch.html"?>
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  <title>Architecture Specific Notes</title>
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  <title>Architecture Specific Notes</title>
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  <section>
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  <section>
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    <title>AMD64/Intel EM64T</title>
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    <title>AMD64/Intel EM64T</title>
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    <para>The amd64 architecture is a 64-bit extension of the older ia32
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    <para>The amd64 architecture is a 64-bit extension of the older ia32
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    architecture. Only 64-bit applications are supported. Creating this port
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    architecture. Only 64-bit applications are supported. Creating this port
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    was relatively easy, because it shares a lot of common code with ia32
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    was relatively easy, because it shares a lot of common code with ia32
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    platform. However, the 64-bit extension has some specifics, which made the
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    platform. However, the 64-bit extension has some specifics, which made the
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    porting interesting.</para>
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    porting interesting.</para>
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    <section>
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    <section>
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      <title>Virtual Memory</title>
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      <title>Virtual Memory</title>
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      <para>The amd64 architecture uses standard processor defined 4-level
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      <para>The amd64 architecture uses standard processor defined 4-level
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      page mapping of 4KB pages. The NX(no-execute) flag on individual pages
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      page mapping of 4KB pages. The NX(no-execute) flag on individual pages
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      is fully supported.</para>
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      is fully supported.</para>
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    </section>
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    </section>
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    <section>
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    <section>
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      <title>TLB-only Paging</title>
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      <title>TLB-only Paging</title>
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      <para>All memory on the amd64 architecture is memory mapped, if the
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      <para>All memory on the amd64 architecture is memory mapped, if the
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      kernel needs to access physical memory, a mapping must be created.
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      kernel needs to access physical memory, a mapping must be created.
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      During boot process the boot loader creates mapping for the first 20MB
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      During boot process the boot loader creates mapping for the first 20MB
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      of physical memory. To correctly initialize the page mapping system, an
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      of physical memory. To correctly initialize the page mapping system, an
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      identity mapping of whole physical memory must be created. However, to
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      identity mapping of whole physical memory must be created. However, to
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      create the mapping it is unavoidable to allocate new - possibly unmapped
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      create the mapping it is unavoidable to allocate new - possibly unmapped
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      - frames from frame allocator. The ia32 solves it by mapping first 2GB
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      - frames from frame allocator. The ia32 solves it by mapping first 2GB
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      memory during boot process. The same solution on 64-bit platform becomes
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      memory during boot process. The same solution on 64-bit platform becomes
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      unfeasible because of the size of the possible address space.</para>
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      unfeasible because of the size of the possible address space.</para>
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      <para>As soon as the exception routines are initialized, a special page
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      <para>As soon as the exception routines are initialized, a special page
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      fault exception handler is installed which provides a complete view of
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      fault exception handler is installed which provides a complete view of
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      physical memory until the real page mapping system is initialized. It
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      physical memory until the real page mapping system is initialized. It
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      dynamically changes the page tables to always contain exactly the
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      dynamically changes the page tables to always contain exactly the
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      faulting address. The page then becomes cached in the TLB and on the
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      faulting address. The page then becomes cached in the TLB and on the
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      next page fault the same tables can be utilized to handle another
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      next page fault the same tables can be utilized to handle another
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      mapping.</para>
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      mapping.</para>
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    </section>
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    </section>
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    <section>
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    <section>
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      <title>Mapping of Physical Memory</title>
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      <title>Mapping of Physical Memory</title>
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      <para>The amd64 ABI document describes several modes of program layout.
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      <para>The amd64 ABI document describes several modes of program layout.
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      The operating system kernel should be compiled in a
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      The operating system kernel should be compiled in a
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      <emphasis>kernel</emphasis> mode - the kernel is located in the negative
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      <emphasis>kernel</emphasis> mode - the kernel is located in the negative
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      2 gigabytes (0xffffffff80000000-0xfffffffffffffffff) and can access data
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      2 gigabytes (0xffffffff80000000-0xfffffffffffffffff) and can access data
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      anywhere in the 64-bit space. This wouldn't allow kernel to see directly
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      anywhere in the 64-bit space. This wouldn't allow kernel to see directly
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      more than 2GB of physical memory. HelenOS duplicates the virtual mapping
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      more than 2GB of physical memory. HelenOS duplicates the virtual mapping
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      of the physical memory starting at 0xffff800000000000 and accesses all
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      of the physical memory starting at 0xffff800000000000 and accesses all
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      external references using this address range.</para>
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      external references using this address range.</para>
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    </section>
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    </section>
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    <section>
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    <section>
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      <title>Thread Local Storage</title>
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      <title>Thread Local Storage</title>
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      <para>The code accessing thread local storage uses a segment register FS
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      <para>The code accessing thread local storage uses a segment register FS
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      as a base. The thread local storage is stored in the hidden 64-bit part
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      as a base. The thread local storage is stored in the hidden 64-bit part
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      of the FS register which must be written using priviledged machine
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      of the FS register which must be written using priviledged machine
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      specific instructions. Special syscall to change this register is
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      specific instructions. Special syscall to change this register is
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      provided to user applications. The TLS address for this platform is
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      provided to user applications. The TLS address for this platform is
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      expected to point just after the end of the thread local data.</para>
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      expected to point just after the end of the thread local data. The
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      application sometimes need to get a real address of the thread local
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      data in its address space but it is impossible to read the base of the
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      FS segmentation register. The solution is to add the self-reference
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      address to the end of thread local data, so that the application can
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      read the address as %gs:0. </para>
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      <figure float="1">
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        <title>IA32 &amp; AMD64</title>
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        <mediaobject id="tldia32">
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          <imageobject role="pdf">
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            <imagedata fileref="images/tld_ia32.pdf" format="PDF" />
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          </imageobject>
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          <imageobject role="html">
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            <imagedata fileref="images/tld_ia32.png" format="PNG" />
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          </imageobject>
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          <imageobject role="fop">
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            <imagedata fileref="images/tld_ia32.svg" format="SVG" />
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          </imageobject>
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        </mediaobject>
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      </figure>
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    </section>
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    </section>
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    <section>
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    <section>
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      <title>Fast SYSCALL/SYSRET Support</title>
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      <title>Fast SYSCALL/SYSRET Support</title>
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      <para>The entry point for system calls was traditionally a speed problem
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      <para>The entry point for system calls was traditionally a speed problem
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      on the ia32 architecture. The amd64 supports SYSCALL/SYSRET
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      on the ia32 architecture. The amd64 supports SYSCALL/SYSRET
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      instructions. Upon encountering the SYSCALL instruction, the processor
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      instructions. Upon encountering the SYSCALL instruction, the processor
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      changes privilege mode and transfers control to an address stored in
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      changes privilege mode and transfers control to an address stored in
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      machine specific register. Unlike other similar instructions it does not
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      machine specific register. Unlike other similar instructions it does not
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      change stack to a known kernel stack, which must be done by the syscall
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      change stack to a known kernel stack, which must be done by the syscall
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      entry routine. A hidden part of a GS register is provided to support the
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      entry routine. A hidden part of a GS register is provided to support the
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      entry routine with data needed for switching to kernel stack.</para>
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      entry routine with data needed for switching to kernel stack.</para>
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    </section>
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    </section>
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    <section>
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    <section>
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      <title>Debugging Support</title>
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      <title>Debugging Support</title>
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      <para>To provide developers tools for finding bugs, hardware breakpoints
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      <para>To provide developers tools for finding bugs, hardware breakpoints
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      and watchpoints are supported. The kernel also supports self-debugging -
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      and watchpoints are supported. The kernel also supports self-debugging -
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      it sets watchpoints on certain data and upon every modification
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      it sets watchpoints on certain data and upon every modification
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      automatically checks whether a correct value was written. It is
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      automatically checks whether a correct value was written. It is
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      worthwhile to mention, that since this feature was implemented, the
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      worthwhile to mention, that since this feature was implemented, the
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      watchpoint was never fired.</para>
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      watchpoint was never fired.</para>
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    </section>
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    </section>
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  </section>
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  </section>
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  <section>
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  <section>
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    <title>Intel IA-32</title>
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    <title>Intel IA-32</title>
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    <para>The ia32 architecture uses 4K pages and processor supported 2-level
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    <para>The ia32 architecture uses 4K pages and processor supported 2-level
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    page tables. Along with amd64 It is one of the 2 architectures that fully
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    page tables. Along with amd64 It is one of the 2 architectures that fully
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    supports SMP configurations. The architecture is mostly similar to amd64,
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    supports SMP configurations. The architecture is mostly similar to amd64,
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    it even shares a lot of code. The debugging support is the same as with
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    it even shares a lot of code. The debugging support is the same as with
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    amd64. The thread local storage uses GS register.</para>
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    amd64. The thread local storage uses GS register.</para>
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  </section>
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  </section>
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  <section>
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  <section>
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    <title>32-bit MIPS</title>
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    <title>32-bit MIPS</title>
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    <para>Both little and big endian kernels are supported. In order to test
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    <para>Both little and big endian kernels are supported. In order to test
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    different page sizes, the mips32 page size was set to 16K. The mips32
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    different page sizes, the mips32 page size was set to 16K. The mips32
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    architecture is TLB-only, the kernel simulates 2-level page tables. On
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    architecture is TLB-only, the kernel simulates 2-level page tables. On
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    processors that support it, lazy FPU context switching is
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    processors that support it, lazy FPU context switching is
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    implemented.</para>
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    implemented.</para>
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    <section>
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    <section>
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      <title>Thread Local Storage</title>
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      <title>Thread Local Storage</title>
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      <para>The thread local storage support in compilers is a relatively
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      <para>The thread local storage support in compilers is a relatively
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      recent phenomena. The standardization of such support for the mips32
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      recent phenomena. The standardization of such support for the mips32
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      platform is very new and even the newest versions of GCC cannot generate
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      platform is very new and even the newest versions of GCC cannot generate
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      100% correct code. Because of some weird MIPS processor variants, it was
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      100% correct code. Because of some weird MIPS processor variants, it was
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      decided, that the TLS pointer will be gathered not from some of the free
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      decided, that the TLS pointer will be gathered not from some of the free
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      registers, but a special instruction was devised and the kernel is
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      registers, but a special instruction was devised and the kernel is
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      supposed to emulate it. HelenOS expects that the TLS pointer is in the
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      supposed to emulate it. HelenOS expects that the TLS pointer is in the
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      K1 register. Upon encountering the reserved instruction exception and
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      K1 register. Upon encountering the reserved instruction exception and
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      checking that the application is requesting a TLS pointer, it returns
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      checking that the application is requesting a TLS pointer, it returns
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      the contents of the K1 register. The K1 register is expected to point
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      the contents of the K1 register. The K1 register is expected to point
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      0x7000 bytes after the beginning of the thread local data.</para>
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      0x7000 bytes after the beginning of the thread local data.</para>
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      <figure float="1">
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        <title>MIPS &amp; PPC</title>
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        <mediaobject id="tldmips">
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          <imageobject role="pdf">
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            <imagedata fileref="images/tld_mips.pdf" format="PDF" />
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          </imageobject>
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          <imageobject role="html">
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            <imagedata fileref="images/tld_mips.png" format="PNG" />
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          </imageobject>
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          <imageobject role="fop">
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            <imagedata fileref="images/tld_mips.svg" format="SVG" />
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          </imageobject>
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        </mediaobject>
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      </figure>
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    </section>
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    </section>
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  </section>
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  </section>
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  <section>
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  <section>
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    <title>Power PC</title>
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    <title>Power PC</title>
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    <para></para>
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    <para></para>
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    <section>
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      <title>Thread Local Storage</title>
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      <para>The Power PC thread local storage uses R2 register to hold an
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      address, that is 0x7000 bytes after the beginning of the thread local
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      data. Overally it is the same as on the MIPS architecture.</para>
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    </section>
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  </section>
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  </section>
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  <section>
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  <section>
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    <title>IA-64</title>
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    <title>IA-64</title>
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    <para></para>
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    <para></para>
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    <figure float="1">
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      <title>IA64</title>
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      <mediaobject id="tldia64">
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        <imageobject role="pdf">
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          <imagedata fileref="images/tld_ia64.pdf" format="PDF" />
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        </imageobject>
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        <imageobject role="html">
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          <imagedata fileref="images/tld_ia64.png" format="PNG" />
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        </imageobject>
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        <imageobject role="fop">
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          <imagedata fileref="images/tld_ia64.svg" format="SVG" />
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        </imageobject>
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      </mediaobject>
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    </figure>
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  </section>
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  </section>
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</appendix>
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</appendix>