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<?xml version="1.0" encoding="UTF-8"?>
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<?xml version="1.0" encoding="UTF-8"?>
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<appendix id="archspecs">
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<appendix id="archspecs">
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  <?dbhtml filename="arch.html"?>
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  <?dbhtml filename="arch.html"?>
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  <title>Architecture Specific Notes</title>
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  <title>Architecture Specific Notes</title>
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  <section>
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  <section>
8 
    <title>AMD64/Intel EM64T</title>
 8 
    <title>AMD64/Intel EM64T</title>
9 
 
 9 
 
10 
    <para>The amd64 architecture is a 64-bit extension of the older ia32
 10 
    <para>The amd64 architecture is a 64-bit extension of the older ia32
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    architecture. Only 64-bit applications are supported. Creating this port
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    architecture. Only 64-bit applications are supported. Creating this port
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    was relatively easy, because it shares a lot of common code with ia32
 12 
    was relatively easy, because it shares a lot of common code with ia32
13 
    platform. However, the 64-bit extension has some specifics, which made the
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    platform. However, the 64-bit extension has some specifics, which made the
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    porting interesting.</para>
 14 
    porting interesting.</para>
15 
 
 15 
 
16 
    <section>
 16 
    <section>
17 
      <title>Virtual Memory</title>
 17 
      <title>Virtual Memory</title>
18 
 
 18 
 
19 
      <para>The amd64 architecture uses standard processor defined 4-level
 19 
      <para>The amd64 architecture uses standard processor defined 4-level
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      page mapping of 4KB pages. The NX(no-execute) flag on individual pages
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      page mapping of 4KB pages. The NX(no-execute) flag on individual pages
21 
      is fully supported.</para>
 21 
      is fully supported.</para>
22 
    </section>
 22 
    </section>
23 
 
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24 
    <section>
 24 
    <section>
25 
      <title>TLB-only Paging</title>
 25 
      <title>TLB-only Paging</title>
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 26 
 
27 
      <para>All memory on the amd64 architecture is memory mapped, if the
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      <para>All memory on the amd64 architecture is memory mapped, if the
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      kernel needs to access physical memory, a mapping must be created.
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      kernel needs to access physical memory, a mapping must be created.
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      During boot process the boot loader creates mapping for the first 20MB
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      During boot process the boot loader creates mapping for the first 20MB
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      of physical memory. To correctly initialize the page mapping system, an
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      of physical memory. To correctly initialize the page mapping system, an
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      identity mapping of whole physical memory must be created. However, to
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      identity mapping of whole physical memory must be created. However, to
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      create the mapping it is unavoidable to allocate new - possibly unmapped
 32 
      create the mapping it is unavoidable to allocate new - possibly unmapped
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      - frames from frame allocator. The ia32 solves it by mapping first 2GB
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      - frames from frame allocator. The ia32 solves it by mapping first 2GB
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      memory during boot process. The same solution on 64-bit platform becomes
 34 
      memory during boot process. The same solution on 64-bit platform becomes
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      unfeasible because of the size of the possible address space.</para>
 35 
      unfeasible because of the size of the possible address space.</para>
36 
 
 36 
 
37 
      <para>As soon as the exception routines are initialized, a special page
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      <para>As soon as the exception routines are initialized, a special page
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      fault exception handler is installed which provides a complete view of
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      fault exception handler is installed which provides a complete view of
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      physical memory until the real page mapping system is initialized. It
 39 
      physical memory until the real page mapping system is initialized. It
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      dynamically changes the page tables to always contain exactly the
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      dynamically changes the page tables to always contain exactly the
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      faulting address. The page then becomes cached in the TLB and on the
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      faulting address. The page then becomes cached in the TLB and on the
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      next page fault the same tables can be utilized to handle another
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      next page fault the same tables can be utilized to handle another
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      mapping.</para>
 43 
      mapping.</para>
44 
    </section>
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    </section>
45 
 
 45 
 
46 
    <section>
 46 
    <section>
47 
      <title>Mapping of Physical Memory</title>
 47 
      <title>Mapping of Physical Memory</title>
48 
 
 48 
 
49 
      <para>The amd64 ABI document describes several modes of program layout.
 49 
      <para>The amd64 ABI document describes several modes of program layout.
50 
      The operating system kernel should be compiled in a
 50 
      The operating system kernel should be compiled in a
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      <emphasis>kernel</emphasis> mode - the kernel is located in the negative
 51 
      <emphasis>kernel</emphasis> mode - the kernel is located in the negative
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      2 gigabytes (0xffffffff80000000-0xfffffffffffffffff) and can access data
 52 
      2 gigabytes (0xffffffff80000000-0xfffffffffffffffff) and can access data
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      anywhere in the 64-bit space. This wouldn't allow kernel to see directly
 53 
      anywhere in the 64-bit space. This wouldn't allow kernel to see directly
54 
      more than 2GB of physical memory. HelenOS duplicates the virtual mapping
 54 
      more than 2GB of physical memory. HelenOS duplicates the virtual mapping
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      of the physical memory starting at 0xffff800000000000 and accesses all
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      of the physical memory starting at 0xffff800000000000 and accesses all
56 
      external references using this address range.</para>
 56 
      external references using this address range.</para>
57 
    </section>
 57 
    </section>
58 
 
 58 
 
59 
    <section>
 59 
    <section>
60 
      <title>Thread Local Storage</title>
 60 
      <title>Thread Local Storage</title>
61 
 
 61 
 
62 
      <para>The code accessing thread local storage uses a segment register FS
 62 
      <para>The code accessing thread local storage uses a segment register FS
63 
      as a base. The thread local storage is stored in the hidden 64-bit part
 63 
      as a base. The thread local storage is stored in the hidden 64-bit part
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      of the FS register which must be written using priviledged machine
 64 
      of the FS register which must be written using priviledged machine
65 
      specific instructions. Special syscall to change this register is
 65 
      specific instructions. Special syscall to change this register is
66 
      provided to user applications. The TLS address for this platform is
 66 
      provided to user applications. The TLS address for this platform is
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      expected to point just after the end of the thread local data. The
 67 
      expected to point just after the end of the thread local data. The
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      application sometimes need to get a real address of the thread local
 68 
      application sometimes need to get a real address of the thread local
69 
      data in its address space but it is impossible to read the base of the
 69 
      data in its address space but it is impossible to read the base of the
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      FS segmentation register. The solution is to add the self-reference
 70 
      FS segmentation register. The solution is to add the self-reference
71 
      address to the end of thread local data, so that the application can
 71 
      address to the end of thread local data, so that the application can
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      read the address as %gs:0. </para>
 72 
      read the address as %gs:0.</para>
73 
 
 73 
 
74 
      <figure float="1">
 74 
      <figure float="1">
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        <title>IA32 &amp; AMD64</title>
 75 
        <title>IA32 &amp; AMD64</title>
76 
 
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        <mediaobject id="tldia32">
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        <mediaobject id="tldia32">
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          <imageobject role="pdf">
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          <imageobject role="pdf">
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            <imagedata fileref="images/tld_ia32.pdf" format="PDF" />
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            <imagedata fileref="images/tld_ia32.pdf" format="PDF" />
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          </imageobject>
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          </imageobject>
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          <imageobject role="html">
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          <imageobject role="html">
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            <imagedata fileref="images/tld_ia32.png" format="PNG" />
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            <imagedata fileref="images/tld_ia32.png" format="PNG" />
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          </imageobject>
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          </imageobject>
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          <imageobject role="fop">
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          <imageobject role="fop">
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            <imagedata fileref="images/tld_ia32.svg" format="SVG" />
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            <imagedata fileref="images/tld_ia32.svg" format="SVG" />
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          </imageobject>
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          </imageobject>
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        </mediaobject>
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        </mediaobject>
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      </figure>
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      </figure>
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    </section>
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    </section>
92 
 
 92 
 
93 
    <section>
 93 
    <section>
94 
      <title>Fast SYSCALL/SYSRET Support</title>
 94 
      <title>Fast SYSCALL/SYSRET Support</title>
95 
 
 95 
 
96 
      <para>The entry point for system calls was traditionally a speed problem
 96 
      <para>The entry point for system calls was traditionally a speed problem
97 
      on the ia32 architecture. The amd64 supports SYSCALL/SYSRET
 97 
      on the ia32 architecture. The amd64 supports SYSCALL/SYSRET
98 
      instructions. Upon encountering the SYSCALL instruction, the processor
 98 
      instructions. Upon encountering the SYSCALL instruction, the processor
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      changes privilege mode and transfers control to an address stored in
 99 
      changes privilege mode and transfers control to an address stored in
100 
      machine specific register. Unlike other similar instructions it does not
 100 
      machine specific register. Unlike other similar instructions it does not
101 
      change stack to a known kernel stack, which must be done by the syscall
 101 
      change stack to a known kernel stack, which must be done by the syscall
102 
      entry routine. A hidden part of a GS register is provided to support the
 102 
      entry routine. A hidden part of a GS register is provided to support the
103 
      entry routine with data needed for switching to kernel stack.</para>
 103 
      entry routine with data needed for switching to kernel stack.</para>
104 
    </section>
 104 
    </section>
105 
 
 105 
 
106 
    <section>
 106 
    <section>
107 
      <title>Debugging Support</title>
 107 
      <title>Debugging Support</title>
108 
 
 108 
 
109 
      <para>To provide developers tools for finding bugs, hardware breakpoints
 109 
      <para>To provide developers tools for finding bugs, hardware breakpoints
110 
      and watchpoints are supported. The kernel also supports self-debugging -
 110 
      and watchpoints are supported. The kernel also supports self-debugging -
111 
      it sets watchpoints on certain data and upon every modification
 111 
      it sets watchpoints on certain data and upon every modification
112 
      automatically checks whether a correct value was written. It is
 112 
      automatically checks whether a correct value was written. It is
113 
      worthwhile to mention, that since this feature was implemented, the
 113 
      worthwhile to mention, that since this feature was implemented, the
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      watchpoint was never fired.</para>
 114 
      watchpoint was never fired.</para>
115 
    </section>
 115 
    </section>
116 
  </section>
 116 
  </section>
117 
 
 117 
 
118 
  <section>
 118 
  <section>
119 
    <title>Intel IA-32</title>
 119 
    <title>Intel IA-32</title>
120 
 
 120 
 
121 
    <para>The ia32 architecture uses 4K pages and processor supported 2-level
 121 
    <para>The ia32 architecture uses 4K pages and processor supported 2-level
122 
    page tables. Along with amd64 It is one of the 2 architectures that fully
 122 
    page tables. Along with amd64 It is one of the 2 architectures that fully
123 
    supports SMP configurations. The architecture is mostly similar to amd64,
 123 
    supports SMP configurations. The architecture is mostly similar to amd64,
124 
    it even shares a lot of code. The debugging support is the same as with
 124 
    it even shares a lot of code. The debugging support is the same as with
125 
    amd64. The thread local storage uses GS register.</para>
 125 
    amd64. The thread local storage uses GS register.</para>
126 
  </section>
 126 
  </section>
127 
 
 127 
 
128 
  <section>
 128 
  <section>
129 
    <title>32-bit MIPS</title>
 129 
    <title>32-bit MIPS</title>
130 
 
 130 
 
131 
    <para>Both little and big endian kernels are supported. In order to test
 131 
    <para>Both little and big endian kernels are supported. In order to test
132 
    different page sizes, the mips32 page size was set to 16K. The mips32
 132 
    different page sizes, the mips32 page size was set to 16K. The mips32
133 
    architecture is TLB-only, the kernel simulates 2-level page tables. On
 133 
    architecture is TLB-only, the kernel simulates 2-level page tables. On
134 
    processors that support it, lazy FPU context switching is
 134 
    processors that support it, lazy FPU context switching is
135 
    implemented.</para>
 135 
    implemented.</para>
136 
 
 136 
 
137 
    <section>
 137 
    <section>
138 
      <title>Thread Local Storage</title>
 138 
      <title>Thread Local Storage</title>
139 
 
 139 
 
140 
      <para>The thread local storage support in compilers is a relatively
 140 
      <para>The thread local storage support in compilers is a relatively
141 
      recent phenomena. The standardization of such support for the mips32
 141 
      recent phenomena. The standardization of such support for the mips32
142 
      platform is very new and even the newest versions of GCC cannot generate
 142 
      platform is very new and even the newest versions of GCC cannot generate
143 
      100% correct code. Because of some weird MIPS processor variants, it was
 143 
      100% correct code. Because of some weird MIPS processor variants, it was
144 
      decided, that the TLS pointer will be gathered not from some of the free
 144 
      decided, that the TLS pointer will be gathered not from some of the free
145 
      registers, but a special instruction was devised and the kernel is
 145 
      registers, but a special instruction was devised and the kernel is
146 
      supposed to emulate it. HelenOS expects that the TLS pointer is in the
 146 
      supposed to emulate it. HelenOS expects that the TLS pointer is in the
147 
      K1 register. Upon encountering the reserved instruction exception and
 147 
      K1 register. Upon encountering the reserved instruction exception and
148 
      checking that the application is requesting a TLS pointer, it returns
 148 
      checking that the application is requesting a TLS pointer, it returns
149 
      the contents of the K1 register. The K1 register is expected to point
 149 
      the contents of the K1 register. The K1 register is expected to point
150 
      0x7000 bytes after the beginning of the thread local data.</para>
 150 
      0x7000 bytes after the beginning of the thread local data.</para>
151 
 
 151 
 
152 
      <figure float="1">
 152 
      <figure float="1">
153 
        <title>MIPS &amp; PPC</title>
 153 
        <title>MIPS &amp; PPC</title>
154 
 
 154 
 
155 
        <mediaobject id="tldmips">
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        <mediaobject id="tldmips">
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          <imageobject role="pdf">
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          <imageobject role="pdf">
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            <imagedata fileref="images/tld_mips.pdf" format="PDF" />
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            <imagedata fileref="images/tld_mips.pdf" format="PDF" />
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          </imageobject>
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          </imageobject>
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          <imageobject role="html">
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          <imageobject role="html">
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            <imagedata fileref="images/tld_mips.png" format="PNG" />
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            <imagedata fileref="images/tld_mips.png" format="PNG" />
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          </imageobject>
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          </imageobject>
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          <imageobject role="fop">
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          <imageobject role="fop">
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            <imagedata fileref="images/tld_mips.svg" format="SVG" />
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            <imagedata fileref="images/tld_mips.svg" format="SVG" />
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          </imageobject>
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          </imageobject>
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        </mediaobject>
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        </mediaobject>
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      </figure>
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      </figure>
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    </section>
 169 
    </section>
- 
 
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- 
 
 171 
    <section>
- 
 
 172 
      <title>Lazy FPU Context Switching</title>
- 
 
 173 
 
- 
 
 174 
      <para>Implementing lazy FPU switching on MIPS architecture is
- 
 
 175 
      straightforward. When coprocessor CP1 is disabled, any FPU intruction
- 
 
 176 
      raises a Coprocessor Unusable exception. The generic lazy FPU context
- 
 
 177 
      switch is then called that takes care of the correct context
- 
 
 178 
      save/restore.</para>
- 
 
 179 
    </section>
170 
  </section>
 180 
  </section>
171 
 
 181 
 
172 
  <section>
 182 
  <section>
173 
    <title>Power PC</title>
 183 
    <title>Power PC</title>
174 
 
 184 
 
- 
 
 185 
    <para>PowerPC allows kernel to enable mode, where data and intruction
- 
 
 186 
    memory reads are not translated through virtual memory mapping
- 
 
 187 
    (<emphasis>real mode</emphasis>). The real mode is automatically enabled
- 
 
 188 
    when an exception occurs. However, the kernel uses the same memory
- 
 
 189 
    structure as on other 32-bit platforms - physical memory is mapped into
- 
 
 190 
    the top 2GB, userspace memory is available in the bottom half of the
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 191 
    32-bit address space.</para>
- 
 
 192 
 
- 
 
 193 
    <section>
- 
 
 194 
      <title>OpenFirmware Boot</title>
- 
 
 195 
 
- 
 
 196 
      <para>The OpenFirmware loads an image of HelenOS operating system and
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 197 
      passes control to the HelenOS specific boot loader. The boot loader then
- 
 
 198 
      performs following tasks:</para>
- 
 
 199 
 
- 
 
 200 
      <itemizedlist>
- 
 
 201 
        <listitem>
- 
 
 202 
          <para>Fetches information from OpenFirmware regarding memory
- 
 
 203 
          structure, device information etc.</para>
- 
 
 204 
        </listitem>
- 
 
 205 
 
- 
 
 206 
        <listitem>
- 
 
 207 
          <para>Switches memory mapping to the real mode.</para>
- 
 
 208 
        </listitem>
- 
 
 209 
 
- 
 
 210 
        <listitem>
- 
 
 211 
          <para>Copies the kernel to proper physical address.</para>
- 
 
 212 
        </listitem>
- 
 
 213 
 
- 
 
 214 
        <listitem>
- 
 
 215 
          <para>Creates basic memory mapping and switches to the new kernel
- 
 
 216 
          mapping, in which the kernel can run.</para>
- 
 
 217 
        </listitem>
- 
 
 218 
 
- 
 
 219 
        <listitem>
- 
 
 220 
          <para>Passes control to the kernel <function>main_bsp</function>
- 
 
 221 
          function.</para>
- 
 
 222 
        </listitem>
- 
 
 223 
      </itemizedlist>
175 
    <para></para>
 224 
    </section>
176 
 
 225 
 
177 
    <section>
 226 
    <section>
178 
      <title>Thread Local Storage</title>
 227 
      <title>Thread Local Storage</title>
179 
 
 228 
 
180 
      <para>The Power PC thread local storage uses R2 register to hold an
 229 
      <para>The Power PC thread local storage uses R2 register to hold an
181 
      address, that is 0x7000 bytes after the beginning of the thread local
 230 
      address, that is 0x7000 bytes after the beginning of the thread local
182 
      data. Overally it is the same as on the MIPS architecture.</para>
 231 
      data. Overally it is the same as on the MIPS architecture.</para>
183 
    </section>
 232 
    </section>
184 
  </section>
 233 
  </section>
185 
 
 234 
 
186 
  <section>
 235 
  <section>
187 
    <title>IA-64</title>
 236 
    <title>IA64</title>
188 
 
 237 
 
189 
    <para></para>
 238 
    <para></para>
190 
 
 239 
 
191 
    <figure float="1">
 240 
    <section>
192 
      <title>IA64</title>
 241 
      <title>Thread Local Storage</title>
193 
 
 242 
 
- 
 
 243 
      <para>Although thread local storage is not officially supported in
- 
 
 244 
      statically linked binaries, GCC supports it without any major obstacles.
- 
 
 245 
      As a thread pointer is designated register r13, the thread local data
- 
 
 246 
      section starts at an address r13+16.</para>
- 
 
 247 
 
- 
 
 248 
      <para><figure float="1">
- 
 
 249 
          <title>IA64</title>
- 
 
 250 
 
194 
      <mediaobject id="tldia64">
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          <mediaobject id="tldia64">
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        <imageobject role="pdf">
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            <imageobject role="pdf">
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          <imagedata fileref="images/tld_ia64.pdf" format="PDF" />
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              <imagedata fileref="images/tld_ia64.pdf" format="PDF" />
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        </imageobject>
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            </imageobject>
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        <imageobject role="html">
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            <imageobject role="html">
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          <imagedata fileref="images/tld_ia64.png" format="PNG" />
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              <imagedata fileref="images/tld_ia64.png" format="PNG" />
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        </imageobject>
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            </imageobject>
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        <imageobject role="fop">
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            <imageobject role="fop">
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          <imagedata fileref="images/tld_ia64.svg" format="SVG" />
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              <imagedata fileref="images/tld_ia64.svg" format="SVG" />
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        </imageobject>
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            </imageobject>
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      </mediaobject>
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          </mediaobject>
- 
 
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        </figure></para>
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    </figure>
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    </section>
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  </section>
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  </section>
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</appendix>
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</appendix>