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1 | <?xml version="1.0" encoding="UTF-8"?> |
1 | <?xml version="1.0" encoding="UTF-8"?> |
2 | <appendix id="archspecs"> |
2 | <appendix id="archspecs"> |
3 | <?dbhtml filename="arch.html"?> |
3 | <?dbhtml filename="arch.html"?> |
4 | 4 | ||
5 | <title>Architecture Specific Notes</title> |
5 | <title>Architecture Specific Notes</title> |
6 | 6 | ||
7 | <section> |
7 | <section> |
8 | <title>AMD64/Intel EM64T</title> |
8 | <title>AMD64/Intel EM64T</title> |
9 | 9 | ||
10 | <para>The amd64 architecture is a 64-bit extension of the older ia32 |
10 | <para>The amd64 architecture is a 64-bit extension of the older ia32 |
11 | architecture. Only 64-bit applications are supported. Creating this port |
11 | architecture. Only 64-bit applications are supported. Creating this port |
12 | was relatively easy, because it shares a lot of common code with ia32 |
12 | was relatively easy, because it shares a lot of common code with ia32 |
13 | platform. However, the 64-bit extension has some specifics, which made the |
13 | platform. However, the 64-bit extension has some specifics, which made the |
14 | porting interesting.</para> |
14 | porting interesting.</para> |
15 | 15 | ||
16 | <section> |
16 | <section> |
17 | <title>Virtual Memory</title> |
17 | <title>Virtual Memory</title> |
18 | 18 | ||
19 | <para>The amd64 architecture uses standard processor defined 4-level |
19 | <para>The amd64 architecture uses standard processor defined 4-level |
20 | page mapping of 4KB pages. The NX(no-execute) flag on individual pages |
20 | page mapping of 4KB pages. The NX(no-execute) flag on individual pages |
21 | is fully supported.</para> |
21 | is fully supported.</para> |
22 | </section> |
22 | </section> |
23 | 23 | ||
24 | <section> |
24 | <section> |
25 | <title>TLB-only Paging</title> |
25 | <title>TLB-only Paging</title> |
26 | 26 | ||
27 | <para>All memory on the amd64 architecture is memory mapped, if the |
27 | <para>All memory on the amd64 architecture is memory mapped, if the |
28 | kernel needs to access physical memory, a mapping must be created. |
28 | kernel needs to access physical memory, a mapping must be created. |
29 | During boot process the boot loader creates mapping for the first 20MB |
29 | During boot process the boot loader creates mapping for the first 20MB |
30 | of physical memory. To correctly initialize the page mapping system, an |
30 | of physical memory. To correctly initialize the page mapping system, an |
31 | identity mapping of whole physical memory must be created. However, to |
31 | identity mapping of whole physical memory must be created. However, to |
32 | create the mapping it is unavoidable to allocate new - possibly unmapped |
32 | create the mapping it is unavoidable to allocate new - possibly unmapped |
33 | - frames from frame allocator. The ia32 solves it by mapping first 2GB |
33 | - frames from frame allocator. The ia32 solves it by mapping first 2GB |
34 | memory during boot process. The same solution on 64-bit platform becomes |
34 | memory during boot process. The same solution on 64-bit platform becomes |
35 | unfeasible because of the size of the possible address space.</para> |
35 | unfeasible because of the size of the possible address space.</para> |
36 | 36 | ||
37 | <para>As soon as the exception routines are initialized, a special page |
37 | <para>As soon as the exception routines are initialized, a special page |
38 | fault exception handler is installed which provides a complete view of |
38 | fault exception handler is installed which provides a complete view of |
39 | physical memory until the real page mapping system is initialized. It |
39 | physical memory until the real page mapping system is initialized. It |
40 | dynamically changes the page tables to always contain exactly the |
40 | dynamically changes the page tables to always contain exactly the |
41 | faulting address. The page then becomes cached in the TLB and on the |
41 | faulting address. The page then becomes cached in the TLB and on the |
42 | next page fault the same tables can be utilized to handle another |
42 | next page fault the same tables can be utilized to handle another |
43 | mapping.</para> |
43 | mapping.</para> |
44 | </section> |
44 | </section> |
45 | 45 | ||
46 | <section> |
46 | <section> |
47 | <title>Mapping of Physical Memory</title> |
47 | <title>Mapping of Physical Memory</title> |
48 | 48 | ||
49 | <para>The amd64 ABI document describes several modes of program layout. |
49 | <para>The amd64 ABI document describes several modes of program layout. |
50 | The operating system kernel should be compiled in a |
50 | The operating system kernel should be compiled in a |
51 | <emphasis>kernel</emphasis> mode - the kernel is located in the negative |
51 | <emphasis>kernel</emphasis> mode - the kernel is located in the negative |
52 | 2 gigabytes (0xffffffff80000000-0xfffffffffffffffff) and can access data |
52 | 2 gigabytes (0xffffffff80000000-0xfffffffffffffffff) and can access data |
53 | anywhere in the 64-bit space. This wouldn't allow kernel to see directly |
53 | anywhere in the 64-bit space. This wouldn't allow kernel to see directly |
54 | more than 2GB of physical memory. HelenOS duplicates the virtual mapping |
54 | more than 2GB of physical memory. HelenOS duplicates the virtual mapping |
55 | of the physical memory starting at 0xffff800000000000 and accesses all |
55 | of the physical memory starting at 0xffff800000000000 and accesses all |
56 | external references using this address range.</para> |
56 | external references using this address range.</para> |
57 | </section> |
57 | </section> |
58 | 58 | ||
59 | <section> |
59 | <section> |
60 | <title>Thread Local Storage</title> |
60 | <title>Thread Local Storage</title> |
61 | 61 | ||
62 | <para>The code accessing thread local storage uses a segment register FS |
62 | <para>The code accessing thread local storage uses a segment register FS |
63 | as a base. The thread local storage is stored in the hidden 64-bit part |
63 | as a base. The thread local storage is stored in the hidden 64-bit part |
64 | of the FS register which must be written using priviledged machine |
64 | of the FS register which must be written using priviledged machine |
65 | specific instructions. Special syscall to change this register is |
65 | specific instructions. Special syscall to change this register is |
66 | provided to user applications. The TLS address for this platform is |
66 | provided to user applications. The TLS address for this platform is |
67 | expected to point just after the end of the thread local data.</para> |
67 | expected to point just after the end of the thread local data. The |
- | 68 | application sometimes need to get a real address of the thread local |
|
- | 69 | data in its address space but it is impossible to read the base of the |
|
- | 70 | FS segmentation register. The solution is to add the self-reference |
|
- | 71 | address to the end of thread local data, so that the application can |
|
- | 72 | read the address as %gs:0. </para> |
|
- | 73 | ||
- | 74 | <figure float="1"> |
|
- | 75 | <title>IA32 & AMD64</title> |
|
- | 76 | ||
- | 77 | <mediaobject id="tldia32"> |
|
- | 78 | <imageobject role="pdf"> |
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- | 79 | <imagedata fileref="images/tld_ia32.pdf" format="PDF" /> |
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- | 80 | </imageobject> |
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- | 81 | ||
- | 82 | <imageobject role="html"> |
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- | 83 | <imagedata fileref="images/tld_ia32.png" format="PNG" /> |
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- | 84 | </imageobject> |
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- | 85 | ||
- | 86 | <imageobject role="fop"> |
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- | 87 | <imagedata fileref="images/tld_ia32.svg" format="SVG" /> |
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- | 88 | </imageobject> |
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- | 89 | </mediaobject> |
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- | 90 | </figure> |
|
68 | </section> |
91 | </section> |
69 | 92 | ||
70 | <section> |
93 | <section> |
71 | <title>Fast SYSCALL/SYSRET Support</title> |
94 | <title>Fast SYSCALL/SYSRET Support</title> |
72 | 95 | ||
73 | <para>The entry point for system calls was traditionally a speed problem |
96 | <para>The entry point for system calls was traditionally a speed problem |
74 | on the ia32 architecture. The amd64 supports SYSCALL/SYSRET |
97 | on the ia32 architecture. The amd64 supports SYSCALL/SYSRET |
75 | instructions. Upon encountering the SYSCALL instruction, the processor |
98 | instructions. Upon encountering the SYSCALL instruction, the processor |
76 | changes privilege mode and transfers control to an address stored in |
99 | changes privilege mode and transfers control to an address stored in |
77 | machine specific register. Unlike other similar instructions it does not |
100 | machine specific register. Unlike other similar instructions it does not |
78 | change stack to a known kernel stack, which must be done by the syscall |
101 | change stack to a known kernel stack, which must be done by the syscall |
79 | entry routine. A hidden part of a GS register is provided to support the |
102 | entry routine. A hidden part of a GS register is provided to support the |
80 | entry routine with data needed for switching to kernel stack.</para> |
103 | entry routine with data needed for switching to kernel stack.</para> |
81 | </section> |
104 | </section> |
82 | 105 | ||
83 | <section> |
106 | <section> |
84 | <title>Debugging Support</title> |
107 | <title>Debugging Support</title> |
85 | 108 | ||
86 | <para>To provide developers tools for finding bugs, hardware breakpoints |
109 | <para>To provide developers tools for finding bugs, hardware breakpoints |
87 | and watchpoints are supported. The kernel also supports self-debugging - |
110 | and watchpoints are supported. The kernel also supports self-debugging - |
88 | it sets watchpoints on certain data and upon every modification |
111 | it sets watchpoints on certain data and upon every modification |
89 | automatically checks whether a correct value was written. It is |
112 | automatically checks whether a correct value was written. It is |
90 | worthwhile to mention, that since this feature was implemented, the |
113 | worthwhile to mention, that since this feature was implemented, the |
91 | watchpoint was never fired.</para> |
114 | watchpoint was never fired.</para> |
92 | </section> |
115 | </section> |
93 | </section> |
116 | </section> |
94 | 117 | ||
95 | <section> |
118 | <section> |
96 | <title>Intel IA-32</title> |
119 | <title>Intel IA-32</title> |
97 | 120 | ||
98 | <para>The ia32 architecture uses 4K pages and processor supported 2-level |
121 | <para>The ia32 architecture uses 4K pages and processor supported 2-level |
99 | page tables. Along with amd64 It is one of the 2 architectures that fully |
122 | page tables. Along with amd64 It is one of the 2 architectures that fully |
100 | supports SMP configurations. The architecture is mostly similar to amd64, |
123 | supports SMP configurations. The architecture is mostly similar to amd64, |
101 | it even shares a lot of code. The debugging support is the same as with |
124 | it even shares a lot of code. The debugging support is the same as with |
102 | amd64. The thread local storage uses GS register.</para> |
125 | amd64. The thread local storage uses GS register.</para> |
103 | </section> |
126 | </section> |
104 | 127 | ||
105 | <section> |
128 | <section> |
106 | <title>32-bit MIPS</title> |
129 | <title>32-bit MIPS</title> |
107 | 130 | ||
108 | <para>Both little and big endian kernels are supported. In order to test |
131 | <para>Both little and big endian kernels are supported. In order to test |
109 | different page sizes, the mips32 page size was set to 16K. The mips32 |
132 | different page sizes, the mips32 page size was set to 16K. The mips32 |
110 | architecture is TLB-only, the kernel simulates 2-level page tables. On |
133 | architecture is TLB-only, the kernel simulates 2-level page tables. On |
111 | processors that support it, lazy FPU context switching is |
134 | processors that support it, lazy FPU context switching is |
112 | implemented.</para> |
135 | implemented.</para> |
113 | 136 | ||
114 | <section> |
137 | <section> |
115 | <title>Thread Local Storage</title> |
138 | <title>Thread Local Storage</title> |
116 | 139 | ||
117 | <para>The thread local storage support in compilers is a relatively |
140 | <para>The thread local storage support in compilers is a relatively |
118 | recent phenomena. The standardization of such support for the mips32 |
141 | recent phenomena. The standardization of such support for the mips32 |
119 | platform is very new and even the newest versions of GCC cannot generate |
142 | platform is very new and even the newest versions of GCC cannot generate |
120 | 100% correct code. Because of some weird MIPS processor variants, it was |
143 | 100% correct code. Because of some weird MIPS processor variants, it was |
121 | decided, that the TLS pointer will be gathered not from some of the free |
144 | decided, that the TLS pointer will be gathered not from some of the free |
122 | registers, but a special instruction was devised and the kernel is |
145 | registers, but a special instruction was devised and the kernel is |
123 | supposed to emulate it. HelenOS expects that the TLS pointer is in the |
146 | supposed to emulate it. HelenOS expects that the TLS pointer is in the |
124 | K1 register. Upon encountering the reserved instruction exception and |
147 | K1 register. Upon encountering the reserved instruction exception and |
125 | checking that the application is requesting a TLS pointer, it returns |
148 | checking that the application is requesting a TLS pointer, it returns |
126 | the contents of the K1 register. The K1 register is expected to point |
149 | the contents of the K1 register. The K1 register is expected to point |
127 | 0x7000 bytes after the beginning of the thread local data.</para> |
150 | 0x7000 bytes after the beginning of the thread local data.</para> |
- | 151 | ||
- | 152 | <figure float="1"> |
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- | 153 | <title>MIPS & PPC</title> |
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- | 154 | ||
- | 155 | <mediaobject id="tldmips"> |
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- | 156 | <imageobject role="pdf"> |
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- | 157 | <imagedata fileref="images/tld_mips.pdf" format="PDF" /> |
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- | 158 | </imageobject> |
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- | 159 | ||
- | 160 | <imageobject role="html"> |
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- | 161 | <imagedata fileref="images/tld_mips.png" format="PNG" /> |
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- | 162 | </imageobject> |
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- | 163 | ||
- | 164 | <imageobject role="fop"> |
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- | 165 | <imagedata fileref="images/tld_mips.svg" format="SVG" /> |
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- | 166 | </imageobject> |
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- | 167 | </mediaobject> |
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- | 168 | </figure> |
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128 | </section> |
169 | </section> |
129 | </section> |
170 | </section> |
130 | 171 | ||
131 | <section> |
172 | <section> |
132 | <title>Power PC</title> |
173 | <title>Power PC</title> |
133 | 174 | ||
134 | <para></para> |
175 | <para></para> |
- | 176 | ||
- | 177 | <section> |
|
- | 178 | <title>Thread Local Storage</title> |
|
- | 179 | ||
- | 180 | <para>The Power PC thread local storage uses R2 register to hold an |
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- | 181 | address, that is 0x7000 bytes after the beginning of the thread local |
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- | 182 | data. Overally it is the same as on the MIPS architecture.</para> |
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- | 183 | </section> |
|
135 | </section> |
184 | </section> |
136 | 185 | ||
137 | <section> |
186 | <section> |
138 | <title>IA-64</title> |
187 | <title>IA-64</title> |
139 | 188 | ||
140 | <para></para> |
189 | <para></para> |
- | 190 | ||
- | 191 | <figure float="1"> |
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- | 192 | <title>IA64</title> |
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- | 193 | ||
- | 194 | <mediaobject id="tldia64"> |
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- | 195 | <imageobject role="pdf"> |
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- | 196 | <imagedata fileref="images/tld_ia64.pdf" format="PDF" /> |
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- | 197 | </imageobject> |
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- | 198 | ||
- | 199 | <imageobject role="html"> |
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- | 200 | <imagedata fileref="images/tld_ia64.png" format="PNG" /> |
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- | 201 | </imageobject> |
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- | 202 | ||
- | 203 | <imageobject role="fop"> |
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- | 204 | <imagedata fileref="images/tld_ia64.svg" format="SVG" /> |
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- | 205 | </imageobject> |
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- | 206 | </mediaobject> |
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- | 207 | </figure> |
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141 | </section> |
208 | </section> |
142 | </appendix> |
209 | </appendix> |