WebSVN – HelenOS – Diff – /branches/tracing/uspace/app/debug/arch/mips32/src/mips32.c


/*
 * Copyright (c) 2008 Jiri Svoboda
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup debug
 * @{
 */
/** @file
 */
 
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <sys/types.h>
#include <errno.h>
#include <udebug.h>
 
#include "../../../cons.h"
#include "../../../main.h"
#include "../../../breakpoint.h"
#include "../../../include/arch.h"
#include "../../../genarch/idec/idec.h"
 
 
 
static istate_t istate;
 
typedef enum {
    /* Branches (conditional) */
    OP_BCzF,
    OP_BCzFL,
    OP_BCzT,
    OP_BCzTL,
    OP_BEQ,
    OP_BEQL,
    OP_BGEZ,
    OP_BGEZAL,
    OP_BGEZALL,
    OP_BGEZL,
    OP_BGTZ,
    OP_BGTZL,
    OP_BLEZ,
    OP_BLEZL,
    OP_BLTZ,
    OP_BLTZAL,
    OP_BLTZALL,
    OP_BLTZL,
    OP_BNE,
    OP_BNEL,
 
    /* Jumps (unconditional) */
    OP_J,
    OP_JAL,
    OP_JALR,
    OP_JR
} op_t;
 
typedef struct {
    uint32_t mask;
    uint32_t value;
    op_t op;
} instr_desc_t;
 
static instr_desc_t decoding_table[] = {
    { 0xf3ff0000, 0x41000000, OP_BCzF },
    { 0xf3ff0000, 0x41020000, OP_BCzFL },
    { 0xf3ff0000, 0x41010000, OP_BCzT },
    { 0xf3ff0000, 0x41030000, OP_BCzTL },
    { 0xfc000000, 0x10000000, OP_BEQ },
    { 0xfc000000, 0x50000000, OP_BEQL },
    { 0xfc1f0000, 0x04010000, OP_BGEZ },
    { 0xfc1f0000, 0x04110000, OP_BGEZAL },
    { 0xfc1f0000, 0x04130000, OP_BGEZALL },
    { 0xfc1f0000, 0x04030000, OP_BGEZL },
    { 0xfc1f0000, 0x1c000000, OP_BGTZ },
    { 0xfc1f0000, 0x5c000000, OP_BGTZL },
    { 0xfc1f0000, 0x18000000, OP_BLEZ },
    { 0xfc1f0000, 0x58000000, OP_BLEZL },
    { 0xfc1f0000, 0x04000000, OP_BLTZ },
    { 0xfc1f0000, 0x04100000, OP_BLTZAL },
    { 0xfc1f0000, 0x04120000, OP_BLTZALL },
    { 0xfc1f0000, 0x04020000, OP_BLTZL },
    { 0xfc000000, 0x14000000, OP_BNE },
    { 0xfc000000, 0x54000000, OP_BNEL },
 
    { 0xfc000000, 0x08000000, OP_J },
    { 0xfc000000, 0x0c000000, OP_JAL },
    { 0xfc1f07ff, 0x00000009, OP_JALR },
    { 0xfc1fffff, 0x00000008, OP_JR },
 
    { 0, 0, -1 }
};
 
void arch_dthread_initialize(dthread_t *dt)
{
    dt->arch.singlestep = false;
 
    bstore_initialize(&dt->arch.cur);
    bstore_initialize(&dt->arch.next[0]);
    bstore_initialize(&dt->arch.next[1]);
}
 
int arch_breakpoint_set(breakpoint_t *b)
{
    return idec_breakpoint_set(b);
}
 
int arch_breakpoint_remove(breakpoint_t *b)
{
    return idec_breakpoint_remove(b);
}
 
static int islot_read(uintptr_t addr, uint32_t *instr)
{
    int rc;
 
    rc = udebug_mem_read(app_phone, instr, addr, sizeof(uint32_t));
    if (rc != EOK) {
        cons_printf("Error reading memory address 0x%zx\n", addr);
    }
 
    return rc;
}
 
static op_t instr_decode(uint32_t instr)
{
    instr_desc_t *idesc;
 
    idesc = &decoding_table[0];
    while (idesc->op >= 0) {
        if ((instr & idesc->mask) == idesc->value)
            return idesc->op;
        ++idesc;
    }
 
    return -1;
}
 
static int get_reg(dthread_t *dt, int reg_no, uint32_t *value)
{
    int rc;
 
    cons_printf("get_reg...\n");
 
    if (reg_no == 0) {
        *value = 0;
        return 0;
    }
 
    rc = udebug_regs_read(app_phone, dt->hash, &istate);
    if (rc < 0) return rc;
 
    /* FIXME: ugly */
    *value = ((uint32_t *)&istate)[reg_no - 1];
    printf("get_reg ok (0x%08x)\n", *value);
 
    return 0;
}
 
/** Get address of the instruction that will be executed after the current one.
 *
 * Assumptions: addr == PC, *addr is not covered by a BREAK.
 *
 * @param dt        Dthread on which to operate.
 * @param addr      Address of an instruction.
 * @param buffer    Buffer for storing up to 2 addresses.
 * @return      Number of stored addresses or negative error code.
 */
int get_next_addr(dthread_t *dt, uintptr_t addr, uintptr_t *buffer)
{
    /* TODO: J[AL]R, branches and delay slots */
    uint32_t instr;
    int32_t offset;
    op_t op;
    int rc;
    int n;
 
    rc = islot_read(addr, &instr);
    if (rc != 0) return rc;
 
    op = instr_decode(instr);
 
    switch (op) {
    case OP_BCzF:
    case OP_BCzFL:
    case OP_BCzT:
    case OP_BCzTL:
    case OP_BEQ:
    case OP_BEQL:
    case OP_BGEZ:
    case OP_BGEZAL:
    case OP_BGEZALL:
    case OP_BGEZL:
    case OP_BGTZ:
    case OP_BGTZL:
    case OP_BLEZ:
    case OP_BLTZ:
    case OP_BLTZAL:
    case OP_BLTZALL:
    case OP_BLTZL:
    case OP_BNE:
    case OP_BNEL:
        /* Branch */
        offset = (int32_t)(int16_t)(instr & 0x0000ffff) << 2;
        buffer[0] = (addr + 4) + offset;    /* taken */
        buffer[1] = addr + 8;           /* not taken */
        n = 2;
        break;
 
    case OP_J:
    case OP_JAL:
        /* Immediate jump */
        buffer[0] =
            ((addr + 4) & 0xf0000000) |
            ((instr & 0x03ffffff) << 2);
        n = 1;
        break;
    case OP_JR:
    case OP_JALR:
        /* Register jump */
        rc = get_reg(dt, (instr >> 21) & 0x1f, &buffer[0]);
        n = 1;
        break;
    default:
        /* Regular instruction */  
        buffer[0] = addr + 4;
        n = 1;
        break;
    }
 
    return n;
}
 
void arch_event_breakpoint(thash_t thread_hash)
{
    idec_event_breakpoint(thread_hash);
}
 
void arch_event_trap(dthread_t *dt)
{
    /* Unused */
    (void)dt;
}
 
void arch_dump_regs(thash_t thash)
{
    /* TODO */
}
 
void arch_singlestep(dthread_t *dt)
{
    idec_singlestep(dt);
}
 
/** @}
 */
 

Rev 3108	Rev 3121
1	/*	1	/*
2	* Copyright (c) 2008 Jiri Svoboda	2	* Copyright (c) 2008 Jiri Svoboda
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup debug	29	/** @addtogroup debug
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <stdio.h>	35	#include <stdio.h>
36	#include <stdlib.h>	36	#include <stdlib.h>
37	#include <assert.h>	37	#include <assert.h>
38	#include <sys/types.h>	38	#include <sys/types.h>
39	#include <errno.h>	39	#include <errno.h>
40	#include <udebug.h>	40	#include <udebug.h>
41		41
42	#include "../../../cons.h"	42	#include "../../../cons.h"
43	#include "../../../main.h"	43	#include "../../../main.h"
44	#include "../../../breakpoint.h"	44	#include "../../../breakpoint.h"
45	#include "../../../include/arch.h"	45	#include "../../../include/arch.h"
46	#include "../../../genarch/idec/idec.h"	46	#include "../../../genarch/idec/idec.h"
47		47
48	#define OPCODE_BREAK 0x0000000d	-
49		-
50	static istate_t istate;	48	static istate_t istate;
51		49
52	typedef enum {	50	typedef enum {
53	/* Branches (conditional) */	51	/* Branches (conditional) */
54	OP_BCzF,	52	OP_BCzF,
55	OP_BCzFL,	53	OP_BCzFL,
56	OP_BCzT,	54	OP_BCzT,
57	OP_BCzTL,	55	OP_BCzTL,
58	OP_BEQ,	56	OP_BEQ,
59	OP_BEQL,	57	OP_BEQL,
60	OP_BGEZ,	58	OP_BGEZ,
61	OP_BGEZAL,	59	OP_BGEZAL,
62	OP_BGEZALL,	60	OP_BGEZALL,
63	OP_BGEZL,	61	OP_BGEZL,
64	OP_BGTZ,	62	OP_BGTZ,
65	OP_BGTZL,	63	OP_BGTZL,
66	OP_BLEZ,	64	OP_BLEZ,
67	OP_BLEZL,	65	OP_BLEZL,
68	OP_BLTZ,	66	OP_BLTZ,
69	OP_BLTZAL,	67	OP_BLTZAL,
70	OP_BLTZALL,	68	OP_BLTZALL,
71	OP_BLTZL,	69	OP_BLTZL,
72	OP_BNE,	70	OP_BNE,
73	OP_BNEL,	71	OP_BNEL,
74		72
75	/* Jumps (unconditional) */	73	/* Jumps (unconditional) */
76	OP_J,	74	OP_J,
77	OP_JAL,	75	OP_JAL,
78	OP_JALR,	76	OP_JALR,
79	OP_JR	77	OP_JR
80	} op_t;	78	} op_t;
81		79
82	typedef struct {	80	typedef struct {
83	uint32_t mask;	81	uint32_t mask;
84	uint32_t value;	82	uint32_t value;
85	op_t op;	83	op_t op;
86	} instr_desc_t;	84	} instr_desc_t;
87		85
88	static instr_desc_t decoding_table[] = {	86	static instr_desc_t decoding_table[] = {
89	{ 0xf3ff0000, 0x41000000, OP_BCzF },	87	{ 0xf3ff0000, 0x41000000, OP_BCzF },
90	{ 0xf3ff0000, 0x41020000, OP_BCzFL },	88	{ 0xf3ff0000, 0x41020000, OP_BCzFL },
91	{ 0xf3ff0000, 0x41010000, OP_BCzT },	89	{ 0xf3ff0000, 0x41010000, OP_BCzT },
92	{ 0xf3ff0000, 0x41030000, OP_BCzTL },	90	{ 0xf3ff0000, 0x41030000, OP_BCzTL },
93	{ 0xfc000000, 0x10000000, OP_BEQ },	91	{ 0xfc000000, 0x10000000, OP_BEQ },
94	{ 0xfc000000, 0x50000000, OP_BEQL },	92	{ 0xfc000000, 0x50000000, OP_BEQL },
95	{ 0xfc1f0000, 0x04010000, OP_BGEZ },	93	{ 0xfc1f0000, 0x04010000, OP_BGEZ },
96	{ 0xfc1f0000, 0x04110000, OP_BGEZAL },	94	{ 0xfc1f0000, 0x04110000, OP_BGEZAL },
97	{ 0xfc1f0000, 0x04130000, OP_BGEZALL },	95	{ 0xfc1f0000, 0x04130000, OP_BGEZALL },
98	{ 0xfc1f0000, 0x04030000, OP_BGEZL },	96	{ 0xfc1f0000, 0x04030000, OP_BGEZL },
99	{ 0xfc1f0000, 0x1c000000, OP_BGTZ },	97	{ 0xfc1f0000, 0x1c000000, OP_BGTZ },
100	{ 0xfc1f0000, 0x5c000000, OP_BGTZL },	98	{ 0xfc1f0000, 0x5c000000, OP_BGTZL },
101	{ 0xfc1f0000, 0x18000000, OP_BLEZ },	99	{ 0xfc1f0000, 0x18000000, OP_BLEZ },
102	{ 0xfc1f0000, 0x58000000, OP_BLEZL },	100	{ 0xfc1f0000, 0x58000000, OP_BLEZL },
103	{ 0xfc1f0000, 0x04000000, OP_BLTZ },	101	{ 0xfc1f0000, 0x04000000, OP_BLTZ },
104	{ 0xfc1f0000, 0x04100000, OP_BLTZAL },	102	{ 0xfc1f0000, 0x04100000, OP_BLTZAL },
105	{ 0xfc1f0000, 0x04120000, OP_BLTZALL },	103	{ 0xfc1f0000, 0x04120000, OP_BLTZALL },
106	{ 0xfc1f0000, 0x04020000, OP_BLTZL },	104	{ 0xfc1f0000, 0x04020000, OP_BLTZL },
107	{ 0xfc000000, 0x14000000, OP_BNE },	105	{ 0xfc000000, 0x14000000, OP_BNE },
108	{ 0xfc000000, 0x54000000, OP_BNEL },	106	{ 0xfc000000, 0x54000000, OP_BNEL },
109		107
110	{ 0xfc000000, 0x08000000, OP_J },	108	{ 0xfc000000, 0x08000000, OP_J },
111	{ 0xfc000000, 0x0c000000, OP_JAL },	109	{ 0xfc000000, 0x0c000000, OP_JAL },
112	{ 0xfc1f07ff, 0x00000009, OP_JALR },	110	{ 0xfc1f07ff, 0x00000009, OP_JALR },
113	{ 0xfc1fffff, 0x00000008, OP_JR },	111	{ 0xfc1fffff, 0x00000008, OP_JR },
114		112
115	{ 0, 0, -1 }	113	{ 0, 0, -1 }
116	};	114	};
117		115
118	void arch_dthread_initialize(dthread_t *dt)	116	void arch_dthread_initialize(dthread_t *dt)
119	{	117	{
120	dt->arch.singlestep = false;	118	dt->arch.singlestep = false;
121		119
122	bstore_initialize(&dt->arch.cur);	120	bstore_initialize(&dt->arch.cur);
123	bstore_initialize(&dt->arch.next[0]);	121	bstore_initialize(&dt->arch.next[0]);
124	bstore_initialize(&dt->arch.next[1]);	122	bstore_initialize(&dt->arch.next[1]);
125	}	123	}
126		124
127	int arch_breakpoint_set(breakpoint_t *b)	125	int arch_breakpoint_set(breakpoint_t *b)
128	{	126	{
129	return idec_breakpoint_set(b);	127	return idec_breakpoint_set(b);
130	}	128	}
131		129
132	int arch_breakpoint_remove(breakpoint_t *b)	130	int arch_breakpoint_remove(breakpoint_t *b)
133	{	131	{
134	return idec_breakpoint_remove(b);	132	return idec_breakpoint_remove(b);
135	}	133	}
136		134
137	static int islot_read(uintptr_t addr, uint32_t *instr)	135	static int islot_read(uintptr_t addr, uint32_t *instr)
138	{	136	{
139	int rc;	137	int rc;
140		138
141	rc = udebug_mem_read(app_phone, instr, addr, sizeof(uint32_t));	139	rc = udebug_mem_read(app_phone, instr, addr, sizeof(uint32_t));
142	if (rc != EOK) {	140	if (rc != EOK) {
143	cons_printf("Error reading memory address 0x%zx\n", addr);	141	cons_printf("Error reading memory address 0x%zx\n", addr);
144	}	142	}
145		143
146	return rc;	144	return rc;
147	}	145	}
148		146
149	static op_t instr_decode(uint32_t instr)	147	static op_t instr_decode(uint32_t instr)
150	{	148	{
151	instr_desc_t *idesc;	149	instr_desc_t *idesc;
152		150
153	idesc = &decoding_table[0];	151	idesc = &decoding_table[0];
154	while (idesc->op >= 0) {	152	while (idesc->op >= 0) {
155	if ((instr & idesc->mask) == idesc->value)	153	if ((instr & idesc->mask) == idesc->value)
156	return idesc->op;	154	return idesc->op;
157	++idesc;	155	++idesc;
158	}	156	}
159		157
160	return -1;	158	return -1;
161	}	159	}
162		160
163	static int get_reg(dthread_t dt, int reg_no, uint32_t value)	161	static int get_reg(dthread_t dt, int reg_no, uint32_t value)
164	{	162	{
165	int rc;	163	int rc;
166		164
167	cons_printf("get_reg...\n");	165	cons_printf("get_reg...\n");
168		166
169	if (reg_no == 0) {	167	if (reg_no == 0) {
170	*value = 0;	168	*value = 0;
171	return 0;	169	return 0;
172	}	170	}
173		171
174	rc = udebug_regs_read(app_phone, dt->hash, &istate);	172	rc = udebug_regs_read(app_phone, dt->hash, &istate);
175	if (rc < 0) return rc;	173	if (rc < 0) return rc;
176		174
177	/* FIXME: ugly */	175	/* FIXME: ugly */
178	value = ((uint32_t )&istate)[reg_no - 1];	176	value = ((uint32_t )&istate)[reg_no - 1];
179	printf("get_reg ok (0x%08x)\n", *value);	177	printf("get_reg ok (0x%08x)\n", *value);
180		178
181	return 0;	179	return 0;
182	}	180	}
183		181
184	/** Get address of the instruction that will be executed after the current one.	182	/** Get address of the instruction that will be executed after the current one.
185	*	183	*
186	* Assumptions: addr == PC, *addr is not covered by a BREAK.	184	* Assumptions: addr == PC, *addr is not covered by a BREAK.
187	*	185	*
188	* @param dt Dthread on which to operate.	186	* @param dt Dthread on which to operate.
189	* @param addr Address of an instruction.	187	* @param addr Address of an instruction.
190	* @param buffer Buffer for storing up to 2 addresses.	188	* @param buffer Buffer for storing up to 2 addresses.
191	* @return Number of stored addresses or negative error code.	189	* @return Number of stored addresses or negative error code.
192	*/	190	*/
193	int get_next_addr(dthread_t dt, uintptr_t addr, uintptr_t buffer)	191	int get_next_addr(dthread_t dt, uintptr_t addr, uintptr_t buffer)
194	{	192	{
195	/* TODO: J[AL]R, branches and delay slots */	193	/* TODO: J[AL]R, branches and delay slots */
196	uint32_t instr;	194	uint32_t instr;
197	int32_t offset;	195	int32_t offset;
198	op_t op;	196	op_t op;
199	int rc;	197	int rc;
200	int n;	198	int n;
201		199
202	rc = islot_read(addr, &instr);	200	rc = islot_read(addr, &instr);
203	if (rc != 0) return rc;	201	if (rc != 0) return rc;
204		202
205	op = instr_decode(instr);	203	op = instr_decode(instr);
206		204
207	switch (op) {	205	switch (op) {
208	case OP_BCzF:	206	case OP_BCzF:
209	case OP_BCzFL:	207	case OP_BCzFL:
210	case OP_BCzT:	208	case OP_BCzT:
211	case OP_BCzTL:	209	case OP_BCzTL:
212	case OP_BEQ:	210	case OP_BEQ:
213	case OP_BEQL:	211	case OP_BEQL:
214	case OP_BGEZ:	212	case OP_BGEZ:
215	case OP_BGEZAL:	213	case OP_BGEZAL:
216	case OP_BGEZALL:	214	case OP_BGEZALL:
217	case OP_BGEZL:	215	case OP_BGEZL:
218	case OP_BGTZ:	216	case OP_BGTZ:
219	case OP_BGTZL:	217	case OP_BGTZL:
220	case OP_BLEZ:	218	case OP_BLEZ:
221	case OP_BLTZ:	219	case OP_BLTZ:
222	case OP_BLTZAL:	220	case OP_BLTZAL:
223	case OP_BLTZALL:	221	case OP_BLTZALL:
224	case OP_BLTZL:	222	case OP_BLTZL:
225	case OP_BNE:	223	case OP_BNE:
226	case OP_BNEL:	224	case OP_BNEL:
227	/* Branch */	225	/* Branch */
228	offset = (int32_t)(int16_t)(instr & 0x0000ffff) << 2;	226	offset = (int32_t)(int16_t)(instr & 0x0000ffff) << 2;
229	buffer[0] = (addr + 4) + offset; /* taken */	227	buffer[0] = (addr + 4) + offset; /* taken */
230	buffer[1] = addr + 8; /* not taken */	228	buffer[1] = addr + 8; /* not taken */
231	n = 2;	229	n = 2;
232	break;	230	break;
233		231
234	case OP_J:	232	case OP_J:
235	case OP_JAL:	233	case OP_JAL:
236	/* Immediate jump */	234	/* Immediate jump */
237	buffer[0] =	235	buffer[0] =
238	((addr + 4) & 0xf0000000) \|	236	((addr + 4) & 0xf0000000) \|
239	((instr & 0x03ffffff) << 2);	237	((instr & 0x03ffffff) << 2);
240	n = 1;	238	n = 1;
241	break;	239	break;
242	case OP_JR:	240	case OP_JR:
243	case OP_JALR:	241	case OP_JALR:
244	/* Register jump */	242	/* Register jump */
245	rc = get_reg(dt, (instr >> 21) & 0x1f, &buffer[0]);	243	rc = get_reg(dt, (instr >> 21) & 0x1f, &buffer[0]);
246	n = 1;	244	n = 1;
247	break;	245	break;
248	default:	246	default:
249	/* Regular instruction */	247	/* Regular instruction */
250	buffer[0] = addr + 4;	248	buffer[0] = addr + 4;
251	n = 1;	249	n = 1;
252	break;	250	break;
253	}	251	}
254		252
255	return n;	253	return n;
256	}	254	}
257		255
258	void arch_event_breakpoint(thash_t thread_hash)	256	void arch_event_breakpoint(thash_t thread_hash)
259	{	257	{
260	idec_event_breakpoint(thread_hash);	258	idec_event_breakpoint(thread_hash);
261	}	259	}
262		260
263	void arch_event_trap(dthread_t *dt)	261	void arch_event_trap(dthread_t *dt)
264	{	262	{
265	/* Unused */	263	/* Unused */
266	(void)dt;	264	(void)dt;
267	}	265	}
268		266
269	void arch_dump_regs(thash_t thash)	267	void arch_dump_regs(thash_t thash)
270	{	268	{
271	/* TODO */	269	/* TODO */
272	}	270	}
273		271
274	void arch_singlestep(dthread_t *dt)	272	void arch_singlestep(dthread_t *dt)
275	{	273	{
276	idec_singlestep(dt);	274	idec_singlestep(dt);
277	}	275	}
278		276
279	/** @}	277	/** @}
280	*/	278	*/
281		279

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(root)/branches/tracing/uspace/app/debug/arch/mips32/src/mips32.c – Rev 3108 → 3121