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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | */ |
33 | */ |
| 34 | 34 | ||
| 35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
| 36 | #include <mm/tlb.h> |
36 | #include <mm/tlb.h> |
| 37 | #include <mm/as.h> |
37 | #include <mm/as.h> |
| 38 | #include <mm/asid.h> |
38 | #include <mm/asid.h> |
| 39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
| 40 | #include <arch/mm/page.h> |
40 | #include <arch/mm/page.h> |
| 41 | #include <arch/mm/mmu.h> |
41 | #include <arch/mm/mmu.h> |
| 42 | #include <arch/interrupt.h> |
42 | #include <arch/interrupt.h> |
| 43 | #include <interrupt.h> |
43 | #include <interrupt.h> |
| 44 | #include <arch.h> |
44 | #include <arch.h> |
| 45 | #include <print.h> |
45 | #include <print.h> |
| 46 | #include <arch/types.h> |
46 | #include <arch/types.h> |
| 47 | #include <config.h> |
47 | #include <config.h> |
| 48 | #include <arch/trap/trap.h> |
48 | #include <arch/trap/trap.h> |
| 49 | #include <arch/trap/exception.h> |
49 | #include <arch/trap/exception.h> |
| 50 | #include <panic.h> |
50 | #include <panic.h> |
| 51 | #include <arch/asm.h> |
51 | #include <arch/asm.h> |
| 52 | 52 | ||
| 53 | #ifdef CONFIG_TSB |
53 | #ifdef CONFIG_TSB |
| 54 | #include <arch/mm/tsb.h> |
54 | #include <arch/mm/tsb.h> |
| 55 | #endif |
55 | #endif |
| 56 | 56 | ||
| 57 | static void dtlb_pte_copy(pte_t *, index_t, bool); |
57 | static void dtlb_pte_copy(pte_t *, index_t, bool); |
| 58 | static void itlb_pte_copy(pte_t *, index_t); |
58 | static void itlb_pte_copy(pte_t *, index_t); |
| 59 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *); |
59 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *); |
| 60 | static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t, |
60 | static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t, |
| 61 | const char *); |
61 | const char *); |
| 62 | static void do_fast_data_access_protection_fault(istate_t *, |
62 | static void do_fast_data_access_protection_fault(istate_t *, |
| 63 | tlb_tag_access_reg_t, const char *); |
63 | tlb_tag_access_reg_t, const char *); |
| 64 | 64 | ||
| 65 | char *context_encoding[] = { |
65 | char *context_encoding[] = { |
| 66 | "Primary", |
66 | "Primary", |
| 67 | "Secondary", |
67 | "Secondary", |
| 68 | "Nucleus", |
68 | "Nucleus", |
| 69 | "Reserved" |
69 | "Reserved" |
| 70 | }; |
70 | }; |
| 71 | 71 | ||
| 72 | void tlb_arch_init(void) |
72 | void tlb_arch_init(void) |
| 73 | { |
73 | { |
| 74 | /* |
74 | /* |
| 75 | * Invalidate all non-locked DTLB and ITLB entries. |
75 | * Invalidate all non-locked DTLB and ITLB entries. |
| 76 | */ |
76 | */ |
| 77 | tlb_invalidate_all(); |
77 | tlb_invalidate_all(); |
| 78 | 78 | ||
| 79 | /* |
79 | /* |
| 80 | * Clear both SFSRs. |
80 | * Clear both SFSRs. |
| 81 | */ |
81 | */ |
| 82 | dtlb_sfsr_write(0); |
82 | dtlb_sfsr_write(0); |
| 83 | itlb_sfsr_write(0); |
83 | itlb_sfsr_write(0); |
| 84 | } |
84 | } |
| 85 | 85 | ||
| 86 | /** Insert privileged mapping into DMMU TLB. |
86 | /** Insert privileged mapping into DMMU TLB. |
| 87 | * |
87 | * |
| 88 | * @param page Virtual page address. |
88 | * @param page Virtual page address. |
| 89 | * @param frame Physical frame address. |
89 | * @param frame Physical frame address. |
| 90 | * @param pagesize Page size. |
90 | * @param pagesize Page size. |
| 91 | * @param locked True for permanent mappings, false otherwise. |
91 | * @param locked True for permanent mappings, false otherwise. |
| 92 | * @param cacheable True if the mapping is cacheable, false otherwise. |
92 | * @param cacheable True if the mapping is cacheable, false otherwise. |
| 93 | */ |
93 | */ |
| 94 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, |
94 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, |
| 95 | bool locked, bool cacheable) |
95 | bool locked, bool cacheable) |
| 96 | { |
96 | { |
| 97 | tlb_tag_access_reg_t tag; |
97 | tlb_tag_access_reg_t tag; |
| 98 | tlb_data_t data; |
98 | tlb_data_t data; |
| 99 | page_address_t pg; |
99 | page_address_t pg; |
| 100 | frame_address_t fr; |
100 | frame_address_t fr; |
| 101 | 101 | ||
| 102 | pg.address = page; |
102 | pg.address = page; |
| 103 | fr.address = frame; |
103 | fr.address = frame; |
| 104 | 104 | ||
| 105 | tag.context = ASID_KERNEL; |
105 | tag.context = ASID_KERNEL; |
| 106 | tag.vpn = pg.vpn; |
106 | tag.vpn = pg.vpn; |
| 107 | 107 | ||
| 108 | dtlb_tag_access_write(tag.value); |
108 | dtlb_tag_access_write(tag.value); |
| 109 | 109 | ||
| 110 | data.value = 0; |
110 | data.value = 0; |
| 111 | data.v = true; |
111 | data.v = true; |
| 112 | data.size = pagesize; |
112 | data.size = pagesize; |
| 113 | data.pfn = fr.pfn; |
113 | data.pfn = fr.pfn; |
| 114 | data.l = locked; |
114 | data.l = locked; |
| 115 | data.cp = cacheable; |
115 | data.cp = cacheable; |
| 116 | #ifdef CONFIG_VIRT_IDX_DCACHE |
116 | #ifdef CONFIG_VIRT_IDX_DCACHE |
| 117 | data.cv = cacheable; |
117 | data.cv = cacheable; |
| 118 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
118 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
| 119 | data.p = true; |
119 | data.p = true; |
| 120 | data.w = true; |
120 | data.w = true; |
| 121 | data.g = false; |
121 | data.g = false; |
| 122 | 122 | ||
| 123 | dtlb_data_in_write(data.value); |
123 | dtlb_data_in_write(data.value); |
| 124 | } |
124 | } |
| 125 | 125 | ||
| 126 | /** Copy PTE to TLB. |
126 | /** Copy PTE to TLB. |
| 127 | * |
127 | * |
| 128 | * @param t Page Table Entry to be copied. |
128 | * @param t Page Table Entry to be copied. |
| 129 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
129 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
| 130 | * @param ro If true, the entry will be created read-only, regardless |
130 | * @param ro If true, the entry will be created read-only, regardless |
| 131 | * of its w field. |
131 | * of its w field. |
| 132 | */ |
132 | */ |
| 133 | void dtlb_pte_copy(pte_t *t, index_t index, bool ro) |
133 | void dtlb_pte_copy(pte_t *t, index_t index, bool ro) |
| 134 | { |
134 | { |
| 135 | tlb_tag_access_reg_t tag; |
135 | tlb_tag_access_reg_t tag; |
| 136 | tlb_data_t data; |
136 | tlb_data_t data; |
| 137 | page_address_t pg; |
137 | page_address_t pg; |
| 138 | frame_address_t fr; |
138 | frame_address_t fr; |
| 139 | 139 | ||
| 140 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
140 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
| 141 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
141 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
| 142 | 142 | ||
| 143 | tag.value = 0; |
143 | tag.value = 0; |
| 144 | tag.context = t->as->asid; |
144 | tag.context = t->as->asid; |
| 145 | tag.vpn = pg.vpn; |
145 | tag.vpn = pg.vpn; |
| 146 | 146 | ||
| 147 | dtlb_tag_access_write(tag.value); |
147 | dtlb_tag_access_write(tag.value); |
| 148 | 148 | ||
| 149 | data.value = 0; |
149 | data.value = 0; |
| 150 | data.v = true; |
150 | data.v = true; |
| 151 | data.size = PAGESIZE_8K; |
151 | data.size = PAGESIZE_8K; |
| 152 | data.pfn = fr.pfn; |
152 | data.pfn = fr.pfn; |
| 153 | data.l = false; |
153 | data.l = false; |
| 154 | data.cp = t->c; |
154 | data.cp = t->c; |
| 155 | #ifdef CONFIG_VIRT_IDX_DCACHE |
155 | #ifdef CONFIG_VIRT_IDX_DCACHE |
| 156 | data.cv = t->c; |
156 | data.cv = t->c; |
| 157 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
157 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
| 158 | data.p = t->k; /* p like privileged */ |
158 | data.p = t->k; /* p like privileged */ |
| 159 | data.w = ro ? false : t->w; |
159 | data.w = ro ? false : t->w; |
| 160 | data.g = t->g; |
160 | data.g = t->g; |
| 161 | 161 | ||
| 162 | dtlb_data_in_write(data.value); |
162 | dtlb_data_in_write(data.value); |
| 163 | } |
163 | } |
| 164 | 164 | ||
| 165 | /** Copy PTE to ITLB. |
165 | /** Copy PTE to ITLB. |
| 166 | * |
166 | * |
| 167 | * @param t Page Table Entry to be copied. |
167 | * @param t Page Table Entry to be copied. |
| 168 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
168 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
| 169 | */ |
169 | */ |
| 170 | void itlb_pte_copy(pte_t *t, index_t index) |
170 | void itlb_pte_copy(pte_t *t, index_t index) |
| 171 | { |
171 | { |
| 172 | tlb_tag_access_reg_t tag; |
172 | tlb_tag_access_reg_t tag; |
| 173 | tlb_data_t data; |
173 | tlb_data_t data; |
| 174 | page_address_t pg; |
174 | page_address_t pg; |
| 175 | frame_address_t fr; |
175 | frame_address_t fr; |
| 176 | 176 | ||
| 177 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
177 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
| 178 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
178 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
| 179 | 179 | ||
| 180 | tag.value = 0; |
180 | tag.value = 0; |
| 181 | tag.context = t->as->asid; |
181 | tag.context = t->as->asid; |
| 182 | tag.vpn = pg.vpn; |
182 | tag.vpn = pg.vpn; |
| 183 | 183 | ||
| 184 | itlb_tag_access_write(tag.value); |
184 | itlb_tag_access_write(tag.value); |
| 185 | 185 | ||
| 186 | data.value = 0; |
186 | data.value = 0; |
| 187 | data.v = true; |
187 | data.v = true; |
| 188 | data.size = PAGESIZE_8K; |
188 | data.size = PAGESIZE_8K; |
| 189 | data.pfn = fr.pfn; |
189 | data.pfn = fr.pfn; |
| 190 | data.l = false; |
190 | data.l = false; |
| 191 | data.cp = t->c; |
191 | data.cp = t->c; |
| 192 | data.p = t->k; /* p like privileged */ |
192 | data.p = t->k; /* p like privileged */ |
| 193 | data.w = false; |
193 | data.w = false; |
| 194 | data.g = t->g; |
194 | data.g = t->g; |
| 195 | 195 | ||
| 196 | itlb_data_in_write(data.value); |
196 | itlb_data_in_write(data.value); |
| 197 | } |
197 | } |
| 198 | 198 | ||
| 199 | /** ITLB miss handler. */ |
199 | /** ITLB miss handler. */ |
| 200 | void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
200 | void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
| 201 | { |
201 | { |
| 202 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
202 | uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
| 203 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
203 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
| 204 | pte_t *t; |
204 | pte_t *t; |
| 205 | 205 | ||
| 206 | page_table_lock(AS, true); |
206 | page_table_lock(AS, true); |
| 207 | t = page_mapping_find(AS, va); |
207 | t = page_mapping_find(AS, page_16k); |
| 208 | if (t && PTE_EXECUTABLE(t)) { |
208 | if (t && PTE_EXECUTABLE(t)) { |
| 209 | /* |
209 | /* |
| 210 | * The mapping was found in the software page hash table. |
210 | * The mapping was found in the software page hash table. |
| 211 | * Insert it into ITLB. |
211 | * Insert it into ITLB. |
| 212 | */ |
212 | */ |
| 213 | t->a = true; |
213 | t->a = true; |
| 214 | itlb_pte_copy(t, index); |
214 | itlb_pte_copy(t, index); |
| 215 | #ifdef CONFIG_TSB |
215 | #ifdef CONFIG_TSB |
| 216 | itsb_pte_copy(t, index); |
216 | itsb_pte_copy(t, index); |
| 217 | #endif |
217 | #endif |
| 218 | page_table_unlock(AS, true); |
218 | page_table_unlock(AS, true); |
| 219 | } else { |
219 | } else { |
| 220 | /* |
220 | /* |
| 221 | * Forward the page fault to the address space page fault |
221 | * Forward the page fault to the address space page fault |
| 222 | * handler. |
222 | * handler. |
| 223 | */ |
223 | */ |
| 224 | page_table_unlock(AS, true); |
224 | page_table_unlock(AS, true); |
| 225 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
225 | if (as_page_fault(page_16k, PF_ACCESS_EXEC, istate) == |
| - | 226 | AS_PF_FAULT) { |
|
| 226 | do_fast_instruction_access_mmu_miss_fault(istate, |
227 | do_fast_instruction_access_mmu_miss_fault(istate, |
| 227 | __func__); |
228 | __func__); |
| 228 | } |
229 | } |
| 229 | } |
230 | } |
| 230 | } |
231 | } |
| 231 | 232 | ||
| 232 | /** DTLB miss handler. |
233 | /** DTLB miss handler. |
| 233 | * |
234 | * |
| 234 | * Note that some faults (e.g. kernel faults) were already resolved by the |
235 | * Note that some faults (e.g. kernel faults) were already resolved by the |
| 235 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
236 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
| 236 | * |
237 | * |
| 237 | * @param tag Content of the TLB Tag Access register as it existed |
238 | * @param tag Content of the TLB Tag Access register as it existed |
| 238 | * when the trap happened. This is to prevent confusion |
239 | * when the trap happened. This is to prevent confusion |
| 239 | * created by clobbered Tag Access register during a nested |
240 | * created by clobbered Tag Access register during a nested |
| 240 | * DTLB miss. |
241 | * DTLB miss. |
| 241 | * @param istate Interrupted state saved on the stack. |
242 | * @param istate Interrupted state saved on the stack. |
| 242 | */ |
243 | */ |
| 243 | void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
244 | void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
| 244 | { |
245 | { |
| 245 | uintptr_t va; |
246 | uintptr_t page_8k; |
| - | 247 | uintptr_t page_16k; |
|
| 246 | index_t index; |
248 | index_t index; |
| 247 | pte_t *t; |
249 | pte_t *t; |
| 248 | 250 | ||
| 249 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
251 | page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH; |
| - | 252 | page_16k = ALIGN_DOWN(page_8k, PAGE_SIZE); |
|
| 250 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
253 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
| 251 | 254 | ||
| 252 | if (tag.context == ASID_KERNEL) { |
255 | if (tag.context == ASID_KERNEL) { |
| 253 | if (!tag.vpn) { |
256 | if (!tag.vpn) { |
| 254 | /* NULL access in kernel */ |
257 | /* NULL access in kernel */ |
| 255 | do_fast_data_access_mmu_miss_fault(istate, tag, |
258 | do_fast_data_access_mmu_miss_fault(istate, tag, |
| 256 | __func__); |
259 | __func__); |
| - | 260 | } else if (page_8k >= end_of_identity) { |
|
| - | 261 | /* |
|
| - | 262 | * The kernel is accessing the I/O space. |
|
| - | 263 | * We still do identity mapping for I/O, |
|
| - | 264 | * but without caching. |
|
| - | 265 | */ |
|
| - | 266 | dtlb_insert_mapping(page_8k, KA2PA(page_8k), |
|
| - | 267 | PAGESIZE_8K, false, false); |
|
| - | 268 | return; |
|
| 257 | } |
269 | } |
| 258 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
270 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
| 259 | "kernel page fault."); |
271 | "kernel page fault."); |
| 260 | } |
272 | } |
| 261 | 273 | ||
| 262 | page_table_lock(AS, true); |
274 | page_table_lock(AS, true); |
| 263 | t = page_mapping_find(AS, va); |
275 | t = page_mapping_find(AS, page_16k); |
| 264 | if (t) { |
276 | if (t) { |
| 265 | /* |
277 | /* |
| 266 | * The mapping was found in the software page hash table. |
278 | * The mapping was found in the software page hash table. |
| 267 | * Insert it into DTLB. |
279 | * Insert it into DTLB. |
| 268 | */ |
280 | */ |
| 269 | t->a = true; |
281 | t->a = true; |
| 270 | dtlb_pte_copy(t, index, true); |
282 | dtlb_pte_copy(t, index, true); |
| 271 | #ifdef CONFIG_TSB |
283 | #ifdef CONFIG_TSB |
| 272 | dtsb_pte_copy(t, index, true); |
284 | dtsb_pte_copy(t, index, true); |
| 273 | #endif |
285 | #endif |
| 274 | page_table_unlock(AS, true); |
286 | page_table_unlock(AS, true); |
| 275 | } else { |
287 | } else { |
| 276 | /* |
288 | /* |
| 277 | * Forward the page fault to the address space page fault |
289 | * Forward the page fault to the address space page fault |
| 278 | * handler. |
290 | * handler. |
| 279 | */ |
291 | */ |
| 280 | page_table_unlock(AS, true); |
292 | page_table_unlock(AS, true); |
| 281 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
293 | if (as_page_fault(page_16k, PF_ACCESS_READ, istate) == |
| - | 294 | AS_PF_FAULT) { |
|
| 282 | do_fast_data_access_mmu_miss_fault(istate, tag, |
295 | do_fast_data_access_mmu_miss_fault(istate, tag, |
| 283 | __func__); |
296 | __func__); |
| 284 | } |
297 | } |
| 285 | } |
298 | } |
| 286 | } |
299 | } |
| 287 | 300 | ||
| 288 | /** DTLB protection fault handler. |
301 | /** DTLB protection fault handler. |
| 289 | * |
302 | * |
| 290 | * @param tag Content of the TLB Tag Access register as it existed |
303 | * @param tag Content of the TLB Tag Access register as it existed |
| 291 | * when the trap happened. This is to prevent confusion |
304 | * when the trap happened. This is to prevent confusion |
| 292 | * created by clobbered Tag Access register during a nested |
305 | * created by clobbered Tag Access register during a nested |
| 293 | * DTLB miss. |
306 | * DTLB miss. |
| 294 | * @param istate Interrupted state saved on the stack. |
307 | * @param istate Interrupted state saved on the stack. |
| 295 | */ |
308 | */ |
| 296 | void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
309 | void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
| 297 | { |
310 | { |
| 298 | uintptr_t va; |
311 | uintptr_t page_16k; |
| 299 | index_t index; |
312 | index_t index; |
| 300 | pte_t *t; |
313 | pte_t *t; |
| 301 | 314 | ||
| 302 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
315 | page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
| 303 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
316 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
| 304 | 317 | ||
| 305 | page_table_lock(AS, true); |
318 | page_table_lock(AS, true); |
| 306 | t = page_mapping_find(AS, va); |
319 | t = page_mapping_find(AS, page_16k); |
| 307 | if (t && PTE_WRITABLE(t)) { |
320 | if (t && PTE_WRITABLE(t)) { |
| 308 | /* |
321 | /* |
| 309 | * The mapping was found in the software page hash table and is |
322 | * The mapping was found in the software page hash table and is |
| 310 | * writable. Demap the old mapping and insert an updated mapping |
323 | * writable. Demap the old mapping and insert an updated mapping |
| 311 | * into DTLB. |
324 | * into DTLB. |
| 312 | */ |
325 | */ |
| 313 | t->a = true; |
326 | t->a = true; |
| 314 | t->d = true; |
327 | t->d = true; |
| 315 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, |
328 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, |
| 316 | va + index * MMU_PAGE_SIZE); |
329 | page_16k + index * MMU_PAGE_SIZE); |
| 317 | dtlb_pte_copy(t, index, false); |
330 | dtlb_pte_copy(t, index, false); |
| 318 | #ifdef CONFIG_TSB |
331 | #ifdef CONFIG_TSB |
| 319 | dtsb_pte_copy(t, index, false); |
332 | dtsb_pte_copy(t, index, false); |
| 320 | #endif |
333 | #endif |
| 321 | page_table_unlock(AS, true); |
334 | page_table_unlock(AS, true); |
| 322 | } else { |
335 | } else { |
| 323 | /* |
336 | /* |
| 324 | * Forward the page fault to the address space page fault |
337 | * Forward the page fault to the address space page fault |
| 325 | * handler. |
338 | * handler. |
| 326 | */ |
339 | */ |
| 327 | page_table_unlock(AS, true); |
340 | page_table_unlock(AS, true); |
| 328 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
341 | if (as_page_fault(page_16k, PF_ACCESS_WRITE, istate) == |
| - | 342 | AS_PF_FAULT) { |
|
| 329 | do_fast_data_access_protection_fault(istate, tag, |
343 | do_fast_data_access_protection_fault(istate, tag, |
| 330 | __func__); |
344 | __func__); |
| 331 | } |
345 | } |
| 332 | } |
346 | } |
| 333 | } |
347 | } |
| 334 | 348 | ||
| 335 | /** Print TLB entry (for debugging purposes). |
349 | /** Print TLB entry (for debugging purposes). |
| 336 | * |
350 | * |
| 337 | * The diag field has been left out in order to make this function more generic |
351 | * The diag field has been left out in order to make this function more generic |
| 338 | * (there is no diag field in US3 architeture). |
352 | * (there is no diag field in US3 architeture). |
| 339 | * |
353 | * |
| 340 | * @param i TLB entry number |
354 | * @param i TLB entry number |
| 341 | * @param t TLB entry tag |
355 | * @param t TLB entry tag |
| 342 | * @param d TLB entry data |
356 | * @param d TLB entry data |
| 343 | */ |
357 | */ |
| 344 | static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d) |
358 | static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d) |
| 345 | { |
359 | { |
| 346 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
360 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
| 347 | "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, " |
361 | "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, " |
| 348 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
362 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
| 349 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, |
363 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, |
| 350 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
364 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
| 351 | } |
365 | } |
| 352 | 366 | ||
| 353 | #if defined (US) |
367 | #if defined (US) |
| 354 | 368 | ||
| 355 | /** Print contents of both TLBs. */ |
369 | /** Print contents of both TLBs. */ |
| 356 | void tlb_print(void) |
370 | void tlb_print(void) |
| 357 | { |
371 | { |
| 358 | int i; |
372 | int i; |
| 359 | tlb_data_t d; |
373 | tlb_data_t d; |
| 360 | tlb_tag_read_reg_t t; |
374 | tlb_tag_read_reg_t t; |
| 361 | 375 | ||
| 362 | printf("I-TLB contents:\n"); |
376 | printf("I-TLB contents:\n"); |
| 363 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
377 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
| 364 | d.value = itlb_data_access_read(i); |
378 | d.value = itlb_data_access_read(i); |
| 365 | t.value = itlb_tag_read_read(i); |
379 | t.value = itlb_tag_read_read(i); |
| 366 | print_tlb_entry(i, t, d); |
380 | print_tlb_entry(i, t, d); |
| 367 | } |
381 | } |
| 368 | 382 | ||
| 369 | printf("D-TLB contents:\n"); |
383 | printf("D-TLB contents:\n"); |
| 370 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
384 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
| 371 | d.value = dtlb_data_access_read(i); |
385 | d.value = dtlb_data_access_read(i); |
| 372 | t.value = dtlb_tag_read_read(i); |
386 | t.value = dtlb_tag_read_read(i); |
| 373 | print_tlb_entry(i, t, d); |
387 | print_tlb_entry(i, t, d); |
| 374 | } |
388 | } |
| 375 | } |
389 | } |
| 376 | 390 | ||
| 377 | #elif defined (US3) |
391 | #elif defined (US3) |
| 378 | 392 | ||
| 379 | /** Print contents of all TLBs. */ |
393 | /** Print contents of all TLBs. */ |
| 380 | void tlb_print(void) |
394 | void tlb_print(void) |
| 381 | { |
395 | { |
| 382 | int i; |
396 | int i; |
| 383 | tlb_data_t d; |
397 | tlb_data_t d; |
| 384 | tlb_tag_read_reg_t t; |
398 | tlb_tag_read_reg_t t; |
| 385 | 399 | ||
| 386 | printf("TLB_ISMALL contents:\n"); |
400 | printf("TLB_ISMALL contents:\n"); |
| 387 | for (i = 0; i < tlb_ismall_size(); i++) { |
401 | for (i = 0; i < tlb_ismall_size(); i++) { |
| 388 | d.value = dtlb_data_access_read(TLB_ISMALL, i); |
402 | d.value = dtlb_data_access_read(TLB_ISMALL, i); |
| 389 | t.value = dtlb_tag_read_read(TLB_ISMALL, i); |
403 | t.value = dtlb_tag_read_read(TLB_ISMALL, i); |
| 390 | print_tlb_entry(i, t, d); |
404 | print_tlb_entry(i, t, d); |
| 391 | } |
405 | } |
| 392 | 406 | ||
| 393 | printf("TLB_IBIG contents:\n"); |
407 | printf("TLB_IBIG contents:\n"); |
| 394 | for (i = 0; i < tlb_ibig_size(); i++) { |
408 | for (i = 0; i < tlb_ibig_size(); i++) { |
| 395 | d.value = dtlb_data_access_read(TLB_IBIG, i); |
409 | d.value = dtlb_data_access_read(TLB_IBIG, i); |
| 396 | t.value = dtlb_tag_read_read(TLB_IBIG, i); |
410 | t.value = dtlb_tag_read_read(TLB_IBIG, i); |
| 397 | print_tlb_entry(i, t, d); |
411 | print_tlb_entry(i, t, d); |
| 398 | } |
412 | } |
| 399 | 413 | ||
| 400 | printf("TLB_DSMALL contents:\n"); |
414 | printf("TLB_DSMALL contents:\n"); |
| 401 | for (i = 0; i < tlb_dsmall_size(); i++) { |
415 | for (i = 0; i < tlb_dsmall_size(); i++) { |
| 402 | d.value = dtlb_data_access_read(TLB_DSMALL, i); |
416 | d.value = dtlb_data_access_read(TLB_DSMALL, i); |
| 403 | t.value = dtlb_tag_read_read(TLB_DSMALL, i); |
417 | t.value = dtlb_tag_read_read(TLB_DSMALL, i); |
| 404 | print_tlb_entry(i, t, d); |
418 | print_tlb_entry(i, t, d); |
| 405 | } |
419 | } |
| 406 | 420 | ||
| 407 | printf("TLB_DBIG_1 contents:\n"); |
421 | printf("TLB_DBIG_1 contents:\n"); |
| 408 | for (i = 0; i < tlb_dbig_size(); i++) { |
422 | for (i = 0; i < tlb_dbig_size(); i++) { |
| 409 | d.value = dtlb_data_access_read(TLB_DBIG_0, i); |
423 | d.value = dtlb_data_access_read(TLB_DBIG_0, i); |
| 410 | t.value = dtlb_tag_read_read(TLB_DBIG_0, i); |
424 | t.value = dtlb_tag_read_read(TLB_DBIG_0, i); |
| 411 | print_tlb_entry(i, t, d); |
425 | print_tlb_entry(i, t, d); |
| 412 | } |
426 | } |
| 413 | 427 | ||
| 414 | printf("TLB_DBIG_2 contents:\n"); |
428 | printf("TLB_DBIG_2 contents:\n"); |
| 415 | for (i = 0; i < tlb_dbig_size(); i++) { |
429 | for (i = 0; i < tlb_dbig_size(); i++) { |
| 416 | d.value = dtlb_data_access_read(TLB_DBIG_1, i); |
430 | d.value = dtlb_data_access_read(TLB_DBIG_1, i); |
| 417 | t.value = dtlb_tag_read_read(TLB_DBIG_1, i); |
431 | t.value = dtlb_tag_read_read(TLB_DBIG_1, i); |
| 418 | print_tlb_entry(i, t, d); |
432 | print_tlb_entry(i, t, d); |
| 419 | } |
433 | } |
| 420 | } |
434 | } |
| 421 | 435 | ||
| 422 | #endif |
436 | #endif |
| 423 | 437 | ||
| 424 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
438 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
| 425 | const char *str) |
439 | const char *str) |
| 426 | { |
440 | { |
| 427 | fault_if_from_uspace(istate, "%s\n", str); |
441 | fault_if_from_uspace(istate, "%s.", str); |
| 428 | dump_istate(istate); |
442 | dump_istate(istate); |
| 429 | panic("%s\n", str); |
443 | panic("%s.", str); |
| 430 | } |
444 | } |
| 431 | 445 | ||
| 432 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
446 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
| 433 | tlb_tag_access_reg_t tag, const char *str) |
447 | tlb_tag_access_reg_t tag, const char *str) |
| 434 | { |
448 | { |
| 435 | uintptr_t va; |
449 | uintptr_t va; |
| 436 | 450 | ||
| 437 | va = tag.vpn << MMU_PAGE_WIDTH; |
451 | va = tag.vpn << MMU_PAGE_WIDTH; |
| 438 | if (tag.context) { |
452 | if (tag.context) { |
| 439 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
453 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va, |
| 440 | tag.context); |
454 | tag.context); |
| 441 | } |
455 | } |
| 442 | dump_istate(istate); |
456 | dump_istate(istate); |
| 443 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
457 | printf("Faulting page: %p, ASID=%d.\n", va, tag.context); |
| 444 | panic("%s\n", str); |
458 | panic("%s.", str); |
| 445 | } |
459 | } |
| 446 | 460 | ||
| 447 | void do_fast_data_access_protection_fault(istate_t *istate, |
461 | void do_fast_data_access_protection_fault(istate_t *istate, |
| 448 | tlb_tag_access_reg_t tag, const char *str) |
462 | tlb_tag_access_reg_t tag, const char *str) |
| 449 | { |
463 | { |
| 450 | uintptr_t va; |
464 | uintptr_t va; |
| 451 | 465 | ||
| 452 | va = tag.vpn << MMU_PAGE_WIDTH; |
466 | va = tag.vpn << MMU_PAGE_WIDTH; |
| 453 | 467 | ||
| 454 | if (tag.context) { |
468 | if (tag.context) { |
| 455 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
469 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va, |
| 456 | tag.context); |
470 | tag.context); |
| 457 | } |
471 | } |
| 458 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
472 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
| 459 | dump_istate(istate); |
473 | dump_istate(istate); |
| 460 | panic("%s\n", str); |
474 | panic("%s.", str); |
| 461 | } |
475 | } |
| 462 | 476 | ||
| 463 | void dump_sfsr_and_sfar(void) |
477 | void dump_sfsr_and_sfar(void) |
| 464 | { |
478 | { |
| 465 | tlb_sfsr_reg_t sfsr; |
479 | tlb_sfsr_reg_t sfsr; |
| 466 | uintptr_t sfar; |
480 | uintptr_t sfar; |
| 467 | 481 | ||
| 468 | sfsr.value = dtlb_sfsr_read(); |
482 | sfsr.value = dtlb_sfsr_read(); |
| 469 | sfar = dtlb_sfar_read(); |
483 | sfar = dtlb_sfar_read(); |
| 470 | 484 | ||
| 471 | #if defined (US) |
485 | #if defined (US) |
| 472 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
486 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
| 473 | "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
487 | "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
| 474 | sfsr.ow, sfsr.fv); |
488 | sfsr.ow, sfsr.fv); |
| 475 | #elif defined (US3) |
489 | #elif defined (US3) |
| 476 | printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, " |
490 | printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, " |
| 477 | "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, |
491 | "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, |
| 478 | sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv); |
492 | sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv); |
| 479 | #endif |
493 | #endif |
| 480 | 494 | ||
| 481 | printf("DTLB SFAR: address=%p\n", sfar); |
495 | printf("DTLB SFAR: address=%p\n", sfar); |
| 482 | 496 | ||
| 483 | dtlb_sfsr_write(0); |
497 | dtlb_sfsr_write(0); |
| 484 | } |
498 | } |
| 485 | 499 | ||
| 486 | #if defined (US3) |
500 | #if defined (US3) |
| 487 | /** Invalidates given TLB entry if and only if it is non-locked or global. |
501 | /** Invalidates given TLB entry if and only if it is non-locked or global. |
| 488 | * |
502 | * |
| 489 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1, |
503 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1, |
| 490 | * TLB_ISMALL, TLB_IBIG). |
504 | * TLB_ISMALL, TLB_IBIG). |
| 491 | * @param entry Entry index within the given TLB. |
505 | * @param entry Entry index within the given TLB. |
| 492 | */ |
506 | */ |
| 493 | static void tlb_invalidate_entry(int tlb, index_t entry) |
507 | static void tlb_invalidate_entry(int tlb, index_t entry) |
| 494 | { |
508 | { |
| 495 | tlb_data_t d; |
509 | tlb_data_t d; |
| 496 | tlb_tag_read_reg_t t; |
510 | tlb_tag_read_reg_t t; |
| 497 | 511 | ||
| 498 | if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) { |
512 | if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) { |
| 499 | d.value = dtlb_data_access_read(tlb, entry); |
513 | d.value = dtlb_data_access_read(tlb, entry); |
| 500 | if (!d.l || d.g) { |
514 | if (!d.l || d.g) { |
| 501 | t.value = dtlb_tag_read_read(tlb, entry); |
515 | t.value = dtlb_tag_read_read(tlb, entry); |
| 502 | d.v = false; |
516 | d.v = false; |
| 503 | dtlb_tag_access_write(t.value); |
517 | dtlb_tag_access_write(t.value); |
| 504 | dtlb_data_access_write(tlb, entry, d.value); |
518 | dtlb_data_access_write(tlb, entry, d.value); |
| 505 | } |
519 | } |
| 506 | } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) { |
520 | } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) { |
| 507 | d.value = itlb_data_access_read(tlb, entry); |
521 | d.value = itlb_data_access_read(tlb, entry); |
| 508 | if (!d.l || d.g) { |
522 | if (!d.l || d.g) { |
| 509 | t.value = itlb_tag_read_read(tlb, entry); |
523 | t.value = itlb_tag_read_read(tlb, entry); |
| 510 | d.v = false; |
524 | d.v = false; |
| 511 | itlb_tag_access_write(t.value); |
525 | itlb_tag_access_write(t.value); |
| 512 | itlb_data_access_write(tlb, entry, d.value); |
526 | itlb_data_access_write(tlb, entry, d.value); |
| 513 | } |
527 | } |
| 514 | } |
528 | } |
| 515 | } |
529 | } |
| 516 | #endif |
530 | #endif |
| 517 | 531 | ||
| 518 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
532 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
| 519 | void tlb_invalidate_all(void) |
533 | void tlb_invalidate_all(void) |
| 520 | { |
534 | { |
| 521 | int i; |
535 | int i; |
| 522 | 536 | ||
| 523 | /* |
537 | /* |
| 524 | * Walk all ITLB and DTLB entries and remove all unlocked mappings. |
538 | * Walk all ITLB and DTLB entries and remove all unlocked mappings. |
| 525 | * |
539 | * |
| 526 | * The kernel doesn't use global mappings so any locked global mappings |
540 | * The kernel doesn't use global mappings so any locked global mappings |
| 527 | * found must have been created by someone else. Their only purpose now |
541 | * found must have been created by someone else. Their only purpose now |
| 528 | * is to collide with proper mappings. Invalidate immediately. It should |
542 | * is to collide with proper mappings. Invalidate immediately. It should |
| 529 | * be safe to invalidate them as late as now. |
543 | * be safe to invalidate them as late as now. |
| 530 | */ |
544 | */ |
| 531 | 545 | ||
| 532 | #if defined (US) |
546 | #if defined (US) |
| 533 | tlb_data_t d; |
547 | tlb_data_t d; |
| 534 | tlb_tag_read_reg_t t; |
548 | tlb_tag_read_reg_t t; |
| 535 | 549 | ||
| 536 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
550 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
| 537 | d.value = itlb_data_access_read(i); |
551 | d.value = itlb_data_access_read(i); |
| 538 | if (!d.l || d.g) { |
552 | if (!d.l || d.g) { |
| 539 | t.value = itlb_tag_read_read(i); |
553 | t.value = itlb_tag_read_read(i); |
| 540 | d.v = false; |
554 | d.v = false; |
| 541 | itlb_tag_access_write(t.value); |
555 | itlb_tag_access_write(t.value); |
| 542 | itlb_data_access_write(i, d.value); |
556 | itlb_data_access_write(i, d.value); |
| 543 | } |
557 | } |
| 544 | } |
558 | } |
| 545 | 559 | ||
| 546 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
560 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
| 547 | d.value = dtlb_data_access_read(i); |
561 | d.value = dtlb_data_access_read(i); |
| 548 | if (!d.l || d.g) { |
562 | if (!d.l || d.g) { |
| 549 | t.value = dtlb_tag_read_read(i); |
563 | t.value = dtlb_tag_read_read(i); |
| 550 | d.v = false; |
564 | d.v = false; |
| 551 | dtlb_tag_access_write(t.value); |
565 | dtlb_tag_access_write(t.value); |
| 552 | dtlb_data_access_write(i, d.value); |
566 | dtlb_data_access_write(i, d.value); |
| 553 | } |
567 | } |
| 554 | } |
568 | } |
| 555 | 569 | ||
| 556 | #elif defined (US3) |
570 | #elif defined (US3) |
| 557 | 571 | ||
| 558 | for (i = 0; i < tlb_ismall_size(); i++) |
572 | for (i = 0; i < tlb_ismall_size(); i++) |
| 559 | tlb_invalidate_entry(TLB_ISMALL, i); |
573 | tlb_invalidate_entry(TLB_ISMALL, i); |
| 560 | for (i = 0; i < tlb_ibig_size(); i++) |
574 | for (i = 0; i < tlb_ibig_size(); i++) |
| 561 | tlb_invalidate_entry(TLB_IBIG, i); |
575 | tlb_invalidate_entry(TLB_IBIG, i); |
| 562 | for (i = 0; i < tlb_dsmall_size(); i++) |
576 | for (i = 0; i < tlb_dsmall_size(); i++) |
| 563 | tlb_invalidate_entry(TLB_DSMALL, i); |
577 | tlb_invalidate_entry(TLB_DSMALL, i); |
| 564 | for (i = 0; i < tlb_dbig_size(); i++) |
578 | for (i = 0; i < tlb_dbig_size(); i++) |
| 565 | tlb_invalidate_entry(TLB_DBIG_0, i); |
579 | tlb_invalidate_entry(TLB_DBIG_0, i); |
| 566 | for (i = 0; i < tlb_dbig_size(); i++) |
580 | for (i = 0; i < tlb_dbig_size(); i++) |
| 567 | tlb_invalidate_entry(TLB_DBIG_1, i); |
581 | tlb_invalidate_entry(TLB_DBIG_1, i); |
| 568 | #endif |
582 | #endif |
| 569 | 583 | ||
| 570 | } |
584 | } |
| 571 | 585 | ||
| 572 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
586 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
| 573 | * (Context). |
587 | * (Context). |
| 574 | * |
588 | * |
| 575 | * @param asid Address Space ID. |
589 | * @param asid Address Space ID. |
| 576 | */ |
590 | */ |
| 577 | void tlb_invalidate_asid(asid_t asid) |
591 | void tlb_invalidate_asid(asid_t asid) |
| 578 | { |
592 | { |
| 579 | tlb_context_reg_t pc_save, ctx; |
593 | tlb_context_reg_t pc_save, ctx; |
| 580 | 594 | ||
| 581 | /* switch to nucleus because we are mapped by the primary context */ |
595 | /* switch to nucleus because we are mapped by the primary context */ |
| 582 | nucleus_enter(); |
596 | nucleus_enter(); |
| 583 | 597 | ||
| 584 | ctx.v = pc_save.v = mmu_primary_context_read(); |
598 | ctx.v = pc_save.v = mmu_primary_context_read(); |
| 585 | ctx.context = asid; |
599 | ctx.context = asid; |
| 586 | mmu_primary_context_write(ctx.v); |
600 | mmu_primary_context_write(ctx.v); |
| 587 | 601 | ||
| 588 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
602 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
| 589 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
603 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
| 590 | 604 | ||
| 591 | mmu_primary_context_write(pc_save.v); |
605 | mmu_primary_context_write(pc_save.v); |
| 592 | 606 | ||
| 593 | nucleus_leave(); |
607 | nucleus_leave(); |
| 594 | } |
608 | } |
| 595 | 609 | ||
| 596 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
610 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
| 597 | * address space. |
611 | * address space. |
| 598 | * |
612 | * |
| 599 | * @param asid Address Space ID. |
613 | * @param asid Address Space ID. |
| 600 | * @param page First page which to sweep out from ITLB and DTLB. |
614 | * @param page First page which to sweep out from ITLB and DTLB. |
| 601 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
615 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
| 602 | */ |
616 | */ |
| 603 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
617 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
| 604 | { |
618 | { |
| 605 | unsigned int i; |
619 | unsigned int i; |
| 606 | tlb_context_reg_t pc_save, ctx; |
620 | tlb_context_reg_t pc_save, ctx; |
| 607 | 621 | ||
| 608 | /* switch to nucleus because we are mapped by the primary context */ |
622 | /* switch to nucleus because we are mapped by the primary context */ |
| 609 | nucleus_enter(); |
623 | nucleus_enter(); |
| 610 | 624 | ||
| 611 | ctx.v = pc_save.v = mmu_primary_context_read(); |
625 | ctx.v = pc_save.v = mmu_primary_context_read(); |
| 612 | ctx.context = asid; |
626 | ctx.context = asid; |
| 613 | mmu_primary_context_write(ctx.v); |
627 | mmu_primary_context_write(ctx.v); |
| 614 | 628 | ||
| 615 | for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) { |
629 | for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) { |
| 616 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
630 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
| 617 | page + i * MMU_PAGE_SIZE); |
631 | page + i * MMU_PAGE_SIZE); |
| 618 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
632 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
| 619 | page + i * MMU_PAGE_SIZE); |
633 | page + i * MMU_PAGE_SIZE); |
| 620 | } |
634 | } |
| 621 | 635 | ||
| 622 | mmu_primary_context_write(pc_save.v); |
636 | mmu_primary_context_write(pc_save.v); |
| 623 | 637 | ||
| 624 | nucleus_leave(); |
638 | nucleus_leave(); |
| 625 | } |
639 | } |
| 626 | 640 | ||
| 627 | /** @} |
641 | /** @} |
| 628 | */ |
642 | */ |
| 629 | 643 | ||