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/*
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/*
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 * Copyright (C) 2006 Jakub Jermar
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 * Copyright (C) 2006 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup sparc64interrupt
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/** @addtogroup sparc64interrupt
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 * @{
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 * @{
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 */
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 */
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/**
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/**
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 * @file
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 * @file
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 * @brief This file contains fast MMU trap handlers.
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 * @brief This file contains fast MMU trap handlers.
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 */
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 */
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#ifndef KERN_sparc64_MMU_TRAP_H_
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#ifndef KERN_sparc64_MMU_TRAP_H_
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#define KERN_sparc64_MMU_TRAP_H_
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#define KERN_sparc64_MMU_TRAP_H_
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#include <arch/stack.h>
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#include <arch/stack.h>
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#include <arch/regdef.h>
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#include <arch/regdef.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/tte.h>
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#include <arch/mm/tte.h>
- 
 
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#include <arch/trap/regwin.h>
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#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
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#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
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#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
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#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
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#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
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#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
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#define FAST_MMU_HANDLER_SIZE           128
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#define FAST_MMU_HANDLER_SIZE           128
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#ifdef __ASM__
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#ifdef __ASM__
- 
 
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.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
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.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
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    /*
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    !
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     * First, try to refill TLB from TSB.
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    ! First, try to refill TLB from TSB.
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     */
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    !
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    ! TODO
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    ! TODO
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
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    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
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.endm
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.endm
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.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
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.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
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    /*
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    /*
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     * First, try to refill TLB from TSB.
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     * First, try to refill TLB from TSB.
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     */
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     */
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    ! TODO
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    ! TODO
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    /*
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    /*
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     * Second, test if it is the portion of the kernel address space
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     * Second, test if it is the portion of the kernel address space
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     * which is faulting. If that is the case, immediately create
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     * which is faulting. If that is the case, immediately create
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     * identity mapping for that page in DTLB. VPN 0 is excluded from
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     * identity mapping for that page in DTLB. VPN 0 is excluded from
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     * this treatment.
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     * this treatment.
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     *
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     *
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     * Note that branch-delay slots are used in order to save space.
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     * Note that branch-delay slots are used in order to save space.
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     */
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     */
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0:
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    mov VA_DMMU_TAG_ACCESS, %g1
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    mov VA_DMMU_TAG_ACCESS, %g1
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    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
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    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
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    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
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    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
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    andcc %g1, %g2, %g3             ! get Context
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    andcc %g1, %g2, %g3             ! get Context
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    bnz 0f                      ! Context is non-zero
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    bnz 0f                      ! Context is non-zero
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    andncc %g1, %g2, %g3                ! get page address into %g3
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    andncc %g1, %g2, %g3                ! get page address into %g3
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    bz 0f                       ! page address is zero
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    bz 0f                       ! page address is zero
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    or %g3, (TTE_CP|TTE_P|TTE_W), %g2       ! 8K pages are the default (encoded as 0)
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    or %g3, (TTE_CP|TTE_P|TTE_W), %g2       ! 8K pages are the default (encoded as 0)
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        set 1, %g3
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    mov 1, %g3
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        sllx %g3, TTE_V_SHIFT, %g3
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    sllx %g3, TTE_V_SHIFT, %g3
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        or %g2, %g3, %g2
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    or %g2, %g3, %g2
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    stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG        ! identity map the kernel page
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    stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG        ! identity map the kernel page
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    retry
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    retry
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    /*
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    /*
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     * Third, catch and handle special cases when the trap is caused by
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     * Third, catch and handle special cases when the trap is caused by
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     * some register window trap handler.
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     * the userspace register window spill or fill handler. In case
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     * one of these two traps caused this trap, we just lower the trap
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     * level and service the DTLB miss. In the end, we restart
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     * the offending SAVE or RESTORE.
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     */
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     */
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0:
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0:
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    ! TODO
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    HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
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0:
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
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    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
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.endm
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.endm
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.macro FAST_DATA_ACCESS_PROTECTION_HANDLER
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.macro FAST_DATA_ACCESS_PROTECTION_HANDLER
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    /*
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     * First, try to refill TLB from TSB.
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     */
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    ! TODO
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- 
 
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    /*
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     * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
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     */
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    HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    PREEMPTIBLE_HANDLER fast_data_access_protection
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    PREEMPTIBLE_HANDLER fast_data_access_protection
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.endm
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.endm
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/*
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 * Macro used to lower TL when a MMU trap is caused by
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 * the userspace register window spill or fill handler.
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 */
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.macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
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    rdpr %tl, %g1
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    dec %g1
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    brz %g1, 0f         ! if TL was 1, skip
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    nop
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    wrpr %g1, 0, %tl        ! TL--
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    rdpr %tt, %g2
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    cmp %g2, TT_SPILL_1_NORMAL
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    be 0f               ! trap from spill_1_normal
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    cmp %g2, TT_FILL_1_NORMAL
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    be 0f               ! trap from fill_1_normal
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    inc %g1
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    wrpr %g1, 0, %tl        ! another trap, TL++
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0:
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.endm
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#endif /* __ASM__ */
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#endif /* __ASM__ */
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */
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