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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_sparc64_ASM_H_ |
35 | #ifndef KERN_sparc64_ASM_H_ |
36 | #define KERN_sparc64_ASM_H_ |
36 | #define KERN_sparc64_ASM_H_ |
37 | 37 | ||
38 | #include <arch.h> |
38 | #include <arch/arch.h> |
39 | #include <typedefs.h> |
- | |
40 | #include <arch/types.h> |
39 | #include <arch/types.h> |
- | 40 | #include <align.h> |
|
41 | #include <arch/register.h> |
41 | #include <arch/register.h> |
42 | #include <config.h> |
42 | #include <config.h> |
43 | #include <time/clock.h> |
- | |
44 | #include <arch/stack.h> |
43 | #include <arch/stack.h> |
45 | 44 | ||
46 | /** Read Processor State register. |
45 | /** Read Processor State register. |
47 | * |
46 | * |
48 | * @return Value of PSTATE register. |
47 | * @return Value of PSTATE register. |
49 | */ |
48 | */ |
50 | static inline uint64_t pstate_read(void) |
49 | static inline uint64_t pstate_read(void) |
51 | { |
50 | { |
52 | uint64_t v; |
51 | uint64_t v; |
53 | 52 | ||
54 | asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
53 | asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
55 | 54 | ||
56 | return v; |
55 | return v; |
57 | } |
56 | } |
58 | 57 | ||
59 | /** Write Processor State register. |
58 | /** Write Processor State register. |
60 | * |
59 | * |
61 | * @param v New value of PSTATE register. |
60 | * @param v New value of PSTATE register. |
62 | */ |
61 | */ |
63 | static inline void pstate_write(uint64_t v) |
62 | static inline void pstate_write(uint64_t v) |
64 | { |
63 | { |
65 | asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
64 | asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
66 | } |
65 | } |
67 | 66 | ||
68 | /** Read TICK_compare Register. |
67 | /** Read TICK_compare Register. |
69 | * |
68 | * |
70 | * @return Value of TICK_comapre register. |
69 | * @return Value of TICK_comapre register. |
71 | */ |
70 | */ |
72 | static inline uint64_t tick_compare_read(void) |
71 | static inline uint64_t tick_compare_read(void) |
73 | { |
72 | { |
74 | uint64_t v; |
73 | uint64_t v; |
75 | 74 | ||
76 | asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
75 | asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
77 | 76 | ||
78 | return v; |
77 | return v; |
79 | } |
78 | } |
80 | 79 | ||
81 | /** Write TICK_compare Register. |
80 | /** Write TICK_compare Register. |
82 | * |
81 | * |
83 | * @param v New value of TICK_comapre register. |
82 | * @param v New value of TICK_comapre register. |
84 | */ |
83 | */ |
85 | static inline void tick_compare_write(uint64_t v) |
84 | static inline void tick_compare_write(uint64_t v) |
86 | { |
85 | { |
87 | asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
86 | asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
88 | } |
87 | } |
89 | 88 | ||
90 | /** Read TICK Register. |
89 | /** Read TICK Register. |
91 | * |
90 | * |
92 | * @return Value of TICK register. |
91 | * @return Value of TICK register. |
93 | */ |
92 | */ |
94 | static inline uint64_t tick_read(void) |
93 | static inline uint64_t tick_read(void) |
95 | { |
94 | { |
96 | uint64_t v; |
95 | uint64_t v; |
97 | 96 | ||
98 | asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
97 | asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
99 | 98 | ||
100 | return v; |
99 | return v; |
101 | } |
100 | } |
102 | 101 | ||
103 | /** Write TICK Register. |
102 | /** Write TICK Register. |
104 | * |
103 | * |
105 | * @param v New value of TICK register. |
104 | * @param v New value of TICK register. |
106 | */ |
105 | */ |
107 | static inline void tick_write(uint64_t v) |
106 | static inline void tick_write(uint64_t v) |
108 | { |
107 | { |
109 | asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
108 | asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
110 | } |
109 | } |
111 | 110 | ||
112 | /** Read FPRS Register. |
111 | /** Read FPRS Register. |
113 | * |
112 | * |
114 | * @return Value of FPRS register. |
113 | * @return Value of FPRS register. |
115 | */ |
114 | */ |
116 | static inline uint64_t fprs_read(void) |
115 | static inline uint64_t fprs_read(void) |
117 | { |
116 | { |
118 | uint64_t v; |
117 | uint64_t v; |
119 | 118 | ||
120 | asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
119 | asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
121 | 120 | ||
122 | return v; |
121 | return v; |
123 | } |
122 | } |
124 | 123 | ||
125 | /** Write FPRS Register. |
124 | /** Write FPRS Register. |
126 | * |
125 | * |
127 | * @param v New value of FPRS register. |
126 | * @param v New value of FPRS register. |
128 | */ |
127 | */ |
129 | static inline void fprs_write(uint64_t v) |
128 | static inline void fprs_write(uint64_t v) |
130 | { |
129 | { |
131 | asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
130 | asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
132 | } |
131 | } |
133 | 132 | ||
134 | /** Read SOFTINT Register. |
133 | /** Read SOFTINT Register. |
135 | * |
134 | * |
136 | * @return Value of SOFTINT register. |
135 | * @return Value of SOFTINT register. |
137 | */ |
136 | */ |
138 | static inline uint64_t softint_read(void) |
137 | static inline uint64_t softint_read(void) |
139 | { |
138 | { |
140 | uint64_t v; |
139 | uint64_t v; |
141 | 140 | ||
142 | asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
141 | asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
143 | 142 | ||
144 | return v; |
143 | return v; |
145 | } |
144 | } |
146 | 145 | ||
147 | /** Write SOFTINT Register. |
146 | /** Write SOFTINT Register. |
148 | * |
147 | * |
149 | * @param v New value of SOFTINT register. |
148 | * @param v New value of SOFTINT register. |
150 | */ |
149 | */ |
151 | static inline void softint_write(uint64_t v) |
150 | static inline void softint_write(uint64_t v) |
152 | { |
151 | { |
153 | asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
152 | asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
154 | } |
153 | } |
155 | 154 | ||
156 | /** Write CLEAR_SOFTINT Register. |
155 | /** Write CLEAR_SOFTINT Register. |
157 | * |
156 | * |
158 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
157 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
159 | * |
158 | * |
160 | * @param v New value of CLEAR_SOFTINT register. |
159 | * @param v New value of CLEAR_SOFTINT register. |
161 | */ |
160 | */ |
162 | static inline void clear_softint_write(uint64_t v) |
161 | static inline void clear_softint_write(uint64_t v) |
163 | { |
162 | { |
164 | asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
163 | asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
165 | } |
164 | } |
166 | 165 | ||
167 | /** Write SET_SOFTINT Register. |
166 | /** Write SET_SOFTINT Register. |
168 | * |
167 | * |
169 | * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
168 | * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
170 | * |
169 | * |
171 | * @param v New value of SET_SOFTINT register. |
170 | * @param v New value of SET_SOFTINT register. |
172 | */ |
171 | */ |
173 | static inline void set_softint_write(uint64_t v) |
172 | static inline void set_softint_write(uint64_t v) |
174 | { |
173 | { |
175 | asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
174 | asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
176 | } |
175 | } |
177 | 176 | ||
178 | /** Enable interrupts. |
177 | /** Enable interrupts. |
179 | * |
178 | * |
180 | * Enable interrupts and return previous |
179 | * Enable interrupts and return previous |
181 | * value of IPL. |
180 | * value of IPL. |
182 | * |
181 | * |
183 | * @return Old interrupt priority level. |
182 | * @return Old interrupt priority level. |
184 | */ |
183 | */ |
185 | static inline ipl_t interrupts_enable(void) { |
184 | static inline ipl_t interrupts_enable(void) { |
186 | pstate_reg_t pstate; |
185 | pstate_reg_t pstate; |
187 | uint64_t value; |
186 | uint64_t value; |
188 | 187 | ||
189 | value = pstate_read(); |
188 | value = pstate_read(); |
190 | pstate.value = value; |
189 | pstate.value = value; |
191 | pstate.ie = true; |
190 | pstate.ie = true; |
192 | pstate_write(pstate.value); |
191 | pstate_write(pstate.value); |
193 | 192 | ||
194 | return (ipl_t) value; |
193 | return (ipl_t) value; |
195 | } |
194 | } |
196 | 195 | ||
197 | /** Disable interrupts. |
196 | /** Disable interrupts. |
198 | * |
197 | * |
199 | * Disable interrupts and return previous |
198 | * Disable interrupts and return previous |
200 | * value of IPL. |
199 | * value of IPL. |
201 | * |
200 | * |
202 | * @return Old interrupt priority level. |
201 | * @return Old interrupt priority level. |
203 | */ |
202 | */ |
204 | static inline ipl_t interrupts_disable(void) { |
203 | static inline ipl_t interrupts_disable(void) { |
205 | pstate_reg_t pstate; |
204 | pstate_reg_t pstate; |
206 | uint64_t value; |
205 | uint64_t value; |
207 | 206 | ||
208 | value = pstate_read(); |
207 | value = pstate_read(); |
209 | pstate.value = value; |
208 | pstate.value = value; |
210 | pstate.ie = false; |
209 | pstate.ie = false; |
211 | pstate_write(pstate.value); |
210 | pstate_write(pstate.value); |
212 | 211 | ||
213 | return (ipl_t) value; |
212 | return (ipl_t) value; |
214 | } |
213 | } |
215 | 214 | ||
216 | /** Restore interrupt priority level. |
215 | /** Restore interrupt priority level. |
217 | * |
216 | * |
218 | * Restore IPL. |
217 | * Restore IPL. |
219 | * |
218 | * |
220 | * @param ipl Saved interrupt priority level. |
219 | * @param ipl Saved interrupt priority level. |
221 | */ |
220 | */ |
222 | static inline void interrupts_restore(ipl_t ipl) { |
221 | static inline void interrupts_restore(ipl_t ipl) { |
223 | pstate_reg_t pstate; |
222 | pstate_reg_t pstate; |
224 | 223 | ||
225 | pstate.value = pstate_read(); |
224 | pstate.value = pstate_read(); |
226 | pstate.ie = ((pstate_reg_t) ipl).ie; |
225 | pstate.ie = ((pstate_reg_t) ipl).ie; |
227 | pstate_write(pstate.value); |
226 | pstate_write(pstate.value); |
228 | } |
227 | } |
229 | 228 | ||
230 | /** Return interrupt priority level. |
229 | /** Return interrupt priority level. |
231 | * |
230 | * |
232 | * Return IPL. |
231 | * Return IPL. |
233 | * |
232 | * |
234 | * @return Current interrupt priority level. |
233 | * @return Current interrupt priority level. |
235 | */ |
234 | */ |
236 | static inline ipl_t interrupts_read(void) { |
235 | static inline ipl_t interrupts_read(void) { |
237 | return (ipl_t) pstate_read(); |
236 | return (ipl_t) pstate_read(); |
238 | } |
237 | } |
239 | 238 | ||
240 | /** Return base address of current stack. |
239 | /** Return base address of current stack. |
241 | * |
240 | * |
242 | * Return the base address of the current stack. |
241 | * Return the base address of the current stack. |
243 | * The stack is assumed to be STACK_SIZE bytes long. |
242 | * The stack is assumed to be STACK_SIZE bytes long. |
244 | * The stack must start on page boundary. |
243 | * The stack must start on page boundary. |
245 | */ |
244 | */ |
246 | static inline uintptr_t get_stack_base(void) |
245 | static inline uintptr_t get_stack_base(void) |
247 | { |
246 | { |
248 | uintptr_t unbiased_sp; |
247 | uintptr_t unbiased_sp; |
249 | 248 | ||
250 | asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
249 | asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
251 | 250 | ||
252 | return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
251 | return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
253 | } |
252 | } |
254 | 253 | ||
255 | /** Read Version Register. |
254 | /** Read Version Register. |
256 | * |
255 | * |
257 | * @return Value of VER register. |
256 | * @return Value of VER register. |
258 | */ |
257 | */ |
259 | static inline uint64_t ver_read(void) |
258 | static inline uint64_t ver_read(void) |
260 | { |
259 | { |
261 | uint64_t v; |
260 | uint64_t v; |
262 | 261 | ||
263 | asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
262 | asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
264 | 263 | ||
265 | return v; |
264 | return v; |
266 | } |
265 | } |
267 | 266 | ||
268 | /** Read Trap Program Counter register. |
267 | /** Read Trap Program Counter register. |
269 | * |
268 | * |
270 | * @return Current value in TPC. |
269 | * @return Current value in TPC. |
271 | */ |
270 | */ |
272 | static inline uint64_t tpc_read(void) |
271 | static inline uint64_t tpc_read(void) |
273 | { |
272 | { |
274 | uint64_t v; |
273 | uint64_t v; |
275 | 274 | ||
276 | asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
275 | asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
277 | 276 | ||
278 | return v; |
277 | return v; |
279 | } |
278 | } |
280 | 279 | ||
281 | /** Read Trap Level register. |
280 | /** Read Trap Level register. |
282 | * |
281 | * |
283 | * @return Current value in TL. |
282 | * @return Current value in TL. |
284 | */ |
283 | */ |
285 | static inline uint64_t tl_read(void) |
284 | static inline uint64_t tl_read(void) |
286 | { |
285 | { |
287 | uint64_t v; |
286 | uint64_t v; |
288 | 287 | ||
289 | asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
288 | asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
290 | 289 | ||
291 | return v; |
290 | return v; |
292 | } |
291 | } |
293 | 292 | ||
294 | /** Read Trap Base Address register. |
293 | /** Read Trap Base Address register. |
295 | * |
294 | * |
296 | * @return Current value in TBA. |
295 | * @return Current value in TBA. |
297 | */ |
296 | */ |
298 | static inline uint64_t tba_read(void) |
297 | static inline uint64_t tba_read(void) |
299 | { |
298 | { |
300 | uint64_t v; |
299 | uint64_t v; |
301 | 300 | ||
302 | asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
301 | asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
303 | 302 | ||
304 | return v; |
303 | return v; |
305 | } |
304 | } |
306 | 305 | ||
307 | /** Write Trap Base Address register. |
306 | /** Write Trap Base Address register. |
308 | * |
307 | * |
309 | * @param v New value of TBA. |
308 | * @param v New value of TBA. |
310 | */ |
309 | */ |
311 | static inline void tba_write(uint64_t v) |
310 | static inline void tba_write(uint64_t v) |
312 | { |
311 | { |
313 | asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
312 | asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
314 | } |
313 | } |
315 | 314 | ||
316 | /** Load uint64_t from alternate space. |
315 | /** Load uint64_t from alternate space. |
317 | * |
316 | * |
318 | * @param asi ASI determining the alternate space. |
317 | * @param asi ASI determining the alternate space. |
319 | * @param va Virtual address within the ASI. |
318 | * @param va Virtual address within the ASI. |
320 | * |
319 | * |
321 | * @return Value read from the virtual address in the specified address space. |
320 | * @return Value read from the virtual address in the specified address space. |
322 | */ |
321 | */ |
323 | static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
322 | static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
324 | { |
323 | { |
325 | uint64_t v; |
324 | uint64_t v; |
326 | 325 | ||
327 | asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
326 | asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
328 | 327 | ||
329 | return v; |
328 | return v; |
330 | } |
329 | } |
331 | 330 | ||
332 | /** Store uint64_t to alternate space. |
331 | /** Store uint64_t to alternate space. |
333 | * |
332 | * |
334 | * @param asi ASI determining the alternate space. |
333 | * @param asi ASI determining the alternate space. |
335 | * @param va Virtual address within the ASI. |
334 | * @param va Virtual address within the ASI. |
336 | * @param v Value to be written. |
335 | * @param v Value to be written. |
337 | */ |
336 | */ |
338 | static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
337 | static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
339 | { |
338 | { |
340 | asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
339 | asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
341 | } |
340 | } |
342 | 341 | ||
343 | /** Flush all valid register windows to memory. */ |
342 | /** Flush all valid register windows to memory. */ |
344 | static inline void flushw(void) |
343 | static inline void flushw(void) |
345 | { |
344 | { |
346 | asm volatile ("flushw\n"); |
345 | asm volatile ("flushw\n"); |
347 | } |
346 | } |
348 | 347 | ||
349 | /** Switch to nucleus by setting TL to 1. */ |
348 | /** Switch to nucleus by setting TL to 1. */ |
350 | static inline void nucleus_enter(void) |
349 | static inline void nucleus_enter(void) |
351 | { |
350 | { |
352 | asm volatile ("wrpr %g0, 1, %tl\n"); |
351 | asm volatile ("wrpr %g0, 1, %tl\n"); |
353 | } |
352 | } |
354 | 353 | ||
355 | /** Switch from nucleus by setting TL to 0. */ |
354 | /** Switch from nucleus by setting TL to 0. */ |
356 | static inline void nucleus_leave(void) |
355 | static inline void nucleus_leave(void) |
357 | { |
356 | { |
358 | asm volatile ("wrpr %g0, %g0, %tl\n"); |
357 | asm volatile ("wrpr %g0, %g0, %tl\n"); |
359 | } |
358 | } |
360 | 359 | ||
361 | /** Read UPA_CONFIG register. |
360 | /** Read UPA_CONFIG register. |
362 | * |
361 | * |
363 | * @return Value of the UPA_CONFIG register. |
362 | * @return Value of the UPA_CONFIG register. |
364 | */ |
363 | */ |
365 | static inline uint64_t upa_config_read(void) |
364 | static inline uint64_t upa_config_read(void) |
366 | { |
365 | { |
367 | return asi_u64_read(ASI_UPA_CONFIG, 0); |
366 | return asi_u64_read(ASI_UPA_CONFIG, 0); |
368 | } |
367 | } |
369 | 368 | ||
370 | extern void cpu_halt(void); |
369 | extern void cpu_halt(void); |
371 | extern void cpu_sleep(void); |
370 | extern void cpu_sleep(void); |
372 | extern void asm_delay_loop(const uint32_t usec); |
371 | extern void asm_delay_loop(const uint32_t usec); |
373 | 372 | ||
374 | extern uint64_t read_from_ag_g7(void); |
373 | extern uint64_t read_from_ag_g7(void); |
375 | extern void write_to_ag_g6(uint64_t val); |
374 | extern void write_to_ag_g6(uint64_t val); |
376 | extern void write_to_ag_g7(uint64_t val); |
375 | extern void write_to_ag_g7(uint64_t val); |
377 | extern void write_to_ig_g6(uint64_t val); |
376 | extern void write_to_ig_g6(uint64_t val); |
378 | 377 | ||
379 | extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
378 | extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
380 | 379 | ||
381 | #endif |
380 | #endif |
382 | 381 | ||
383 | /** @} |
382 | /** @} |
384 | */ |
383 | */ |
385 | 384 |