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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Martin Decky |
2 | * Copyright (c) 2006 Martin Decky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ppc32mm |
29 | /** @addtogroup ppc32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <mm/tlb.h> |
35 | #include <mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
38 | #include <interrupt.h> |
38 | #include <interrupt.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <print.h> |
41 | #include <print.h> |
- | 42 | #include <macros.h> |
|
42 | #include <symtab.h> |
43 | #include <symtab.h> |
43 | 44 | ||
- | 45 | static unsigned int seed = 10; |
|
- | 46 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
|
- | 47 | ||
- | 48 | ||
- | 49 | #define TLB_FLUSH \ |
|
- | 50 | "tlbie %0\n" \ |
|
- | 51 | "addi %0, %0, 0x1000\n" |
|
- | 52 | ||
44 | 53 | ||
45 | /** Try to find PTE for faulting address |
54 | /** Try to find PTE for faulting address |
46 | * |
55 | * |
47 | * Try to find PTE for faulting address. |
56 | * Try to find PTE for faulting address. |
48 | * The as->lock must be held on entry to this function |
57 | * The as->lock must be held on entry to this function |
49 | * if lock is true. |
58 | * if lock is true. |
50 | * |
59 | * |
51 | * @param as Address space. |
60 | * @param as Address space. |
52 | * @param lock Lock/unlock the address space. |
61 | * @param lock Lock/unlock the address space. |
53 | * @param badvaddr Faulting virtual address. |
62 | * @param badvaddr Faulting virtual address. |
54 | * @param access Access mode that caused the fault. |
63 | * @param access Access mode that caused the fault. |
55 | * @param istate Pointer to interrupted state. |
64 | * @param istate Pointer to interrupted state. |
56 | * @param pfrc Pointer to variable where as_page_fault() return code |
65 | * @param pfrc Pointer to variable where as_page_fault() return code |
57 | * will be stored. |
66 | * will be stored. |
58 | * @return PTE on success, NULL otherwise. |
67 | * @return PTE on success, NULL otherwise. |
59 | * |
68 | * |
60 | */ |
69 | */ |
61 | static pte_t * |
70 | static pte_t * |
62 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
71 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
63 | istate_t *istate, int *pfrc) |
72 | istate_t *istate, int *pfrc) |
64 | { |
73 | { |
65 | /* |
74 | /* |
66 | * Check if the mapping exists in page tables. |
75 | * Check if the mapping exists in page tables. |
67 | */ |
76 | */ |
68 | pte_t *pte = page_mapping_find(as, badvaddr); |
77 | pte_t *pte = page_mapping_find(as, badvaddr); |
69 | if ((pte) && (pte->p)) { |
78 | if ((pte) && (pte->present)) { |
70 | /* |
79 | /* |
71 | * Mapping found in page tables. |
80 | * Mapping found in page tables. |
72 | * Immediately succeed. |
81 | * Immediately succeed. |
73 | */ |
82 | */ |
74 | return pte; |
83 | return pte; |
75 | } else { |
84 | } else { |
76 | int rc; |
85 | int rc; |
77 | 86 | ||
78 | /* |
87 | /* |
79 | * Mapping not found in page tables. |
88 | * Mapping not found in page tables. |
80 | * Resort to higher-level page fault handler. |
89 | * Resort to higher-level page fault handler. |
81 | */ |
90 | */ |
82 | page_table_unlock(as, lock); |
91 | page_table_unlock(as, lock); |
83 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
92 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
84 | case AS_PF_OK: |
93 | case AS_PF_OK: |
85 | /* |
94 | /* |
86 | * The higher-level page fault handler succeeded, |
95 | * The higher-level page fault handler succeeded, |
87 | * The mapping ought to be in place. |
96 | * The mapping ought to be in place. |
88 | */ |
97 | */ |
89 | page_table_lock(as, lock); |
98 | page_table_lock(as, lock); |
90 | pte = page_mapping_find(as, badvaddr); |
99 | pte = page_mapping_find(as, badvaddr); |
91 | ASSERT((pte) && (pte->p)); |
100 | ASSERT((pte) && (pte->present)); |
92 | *pfrc = 0; |
101 | *pfrc = 0; |
93 | return pte; |
102 | return pte; |
94 | case AS_PF_DEFER: |
103 | case AS_PF_DEFER: |
95 | page_table_lock(as, lock); |
104 | page_table_lock(as, lock); |
96 | *pfrc = rc; |
105 | *pfrc = rc; |
97 | return NULL; |
106 | return NULL; |
98 | case AS_PF_FAULT: |
107 | case AS_PF_FAULT: |
99 | page_table_lock(as, lock); |
108 | page_table_lock(as, lock); |
100 | *pfrc = rc; |
109 | *pfrc = rc; |
101 | return NULL; |
110 | return NULL; |
102 | default: |
111 | default: |
103 | panic("unexpected rc (%d)\n", rc); |
112 | panic("Unexpected rc (%d).", rc); |
104 | } |
113 | } |
105 | } |
114 | } |
106 | } |
115 | } |
107 | 116 | ||
108 | 117 | ||
109 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
118 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
110 | { |
119 | { |
111 | char *symbol = ""; |
120 | char *symbol; |
112 | char *sym2 = ""; |
121 | char *sym2; |
113 | 122 | ||
114 | char *s = get_symtab_entry(istate->pc); |
123 | symbol = symtab_fmt_name_lookup(istate->pc); |
115 | if (s) |
- | |
116 | symbol = s; |
- | |
117 | s = get_symtab_entry(istate->lr); |
124 | sym2 = symtab_fmt_name_lookup(istate->lr); |
118 | if (s) |
- | |
119 | sym2 = s; |
- | |
120 | 125 | ||
121 | fault_if_from_uspace(istate, |
126 | fault_if_from_uspace(istate, |
122 | "%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, |
127 | "PHT Refill Exception on %p.", badvaddr); |
123 | istate->pc, symbol, sym2); |
- | |
124 | panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, |
128 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
125 | istate->pc, symbol, sym2); |
129 | istate->pc, symbol, sym2); |
126 | } |
130 | } |
127 | 131 | ||
128 | 132 | ||
129 | static void pht_insert(const uintptr_t vaddr, const pfn_t pfn) |
133 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
130 | { |
134 | { |
131 | uint32_t page = (vaddr >> 12) & 0xffff; |
135 | uint32_t page = (vaddr >> 12) & 0xffff; |
132 | uint32_t api = (vaddr >> 22) & 0x3f; |
136 | uint32_t api = (vaddr >> 22) & 0x3f; |
133 | 137 | ||
134 | uint32_t vsid; |
138 | uint32_t vsid; |
135 | asm volatile ( |
139 | asm volatile ( |
136 | "mfsrin %0, %1\n" |
140 | "mfsrin %0, %1\n" |
137 | : "=r" (vsid) |
141 | : "=r" (vsid) |
138 | : "r" (vaddr) |
142 | : "r" (vaddr) |
139 | ); |
143 | ); |
140 | 144 | ||
141 | uint32_t sdr1; |
145 | uint32_t sdr1; |
142 | asm volatile ( |
146 | asm volatile ( |
143 | "mfsdr1 %0\n" |
147 | "mfsdr1 %0\n" |
144 | : "=r" (sdr1) |
148 | : "=r" (sdr1) |
145 | ); |
149 | ); |
146 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
150 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
147 | 151 | ||
148 | /* Primary hash (xor) */ |
152 | /* Primary hash (xor) */ |
149 | uint32_t h = 0; |
153 | uint32_t h = 0; |
150 | uint32_t hash = vsid ^ page; |
154 | uint32_t hash = vsid ^ page; |
151 | uint32_t base = (hash & 0x3ff) << 3; |
155 | uint32_t base = (hash & 0x3ff) << 3; |
152 | uint32_t i; |
156 | uint32_t i; |
153 | bool found = false; |
157 | bool found = false; |
154 | 158 | ||
155 | /* Find unused or colliding |
- | |
156 | PTE in PTEG */ |
159 | /* Find colliding PTE in PTEG */ |
157 | for (i = 0; i < 8; i++) { |
160 | for (i = 0; i < 8; i++) { |
- | 161 | if ((phte[base + i].v) |
|
158 | if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && |
162 | && (phte[base + i].vsid == vsid) |
159 | (phte[base + i].api == api))) { |
163 | && (phte[base + i].api == api) |
- | 164 | && (phte[base + i].h == 0)) { |
|
160 | found = true; |
165 | found = true; |
161 | break; |
166 | break; |
162 | } |
167 | } |
163 | } |
168 | } |
164 | 169 | ||
165 | if (!found) { |
170 | if (!found) { |
166 | /* Secondary hash (not) */ |
- | |
167 | uint32_t base2 = (~hash & 0x3ff) << 3; |
- | |
168 | - | ||
169 | /* Find unused or colliding |
171 | /* Find unused PTE in PTEG */ |
170 | PTE in PTEG */ |
- | |
171 | for (i = 0; i < 8; i++) { |
172 | for (i = 0; i < 8; i++) { |
172 | if ((!phte[base2 + i].v) || |
173 | if (!phte[base + i].v) { |
173 | ((phte[base2 + i].vsid == vsid) && |
- | |
174 | (phte[base2 + i].api == api))) { |
- | |
175 | found = true; |
174 | found = true; |
176 | base = base2; |
- | |
177 | h = 1; |
- | |
178 | break; |
175 | break; |
179 | } |
176 | } |
180 | } |
177 | } |
181 | - | ||
182 | if (!found) { |
- | |
183 | // TODO: A/C precedence groups |
- | |
184 | i = page % 8; |
- | |
185 | } |
- | |
186 | } |
- | |
187 | - | ||
188 | phte[base + i].v = 1; |
- | |
189 | phte[base + i].vsid = vsid; |
- | |
190 | phte[base + i].h = h; |
- | |
191 | phte[base + i].api = api; |
- | |
192 | phte[base + i].rpn = pfn; |
- | |
193 | phte[base + i].r = 0; |
- | |
194 | phte[base + i].c = 0; |
- | |
195 | phte[base + i].pp = 2; // FIXME |
- | |
196 | } |
- | |
197 | - | ||
198 | - | ||
199 | static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn) |
- | |
200 | { |
- | |
201 | uint32_t page = (vaddr >> 12) & 0xffff; |
- | |
202 | uint32_t api = (vaddr >> 22) & 0x3f; |
- | |
203 | - | ||
204 | uint32_t vsid; |
- | |
205 | asm volatile ( |
- | |
206 | "mfsrin %0, %1\n" |
- | |
207 | : "=r" (vsid) |
- | |
208 | : "r" (vaddr) |
- | |
209 | ); |
- | |
210 | - | ||
211 | uint32_t sdr1; |
- | |
212 | asm volatile ( |
- | |
213 | "mfsdr1 %0\n" |
- | |
214 | : "=r" (sdr1) |
- | |
215 | ); |
- | |
216 | phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000); |
- | |
217 | - | ||
218 | /* Primary hash (xor) */ |
- | |
219 | uint32_t h = 0; |
- | |
220 | uint32_t hash = vsid ^ page; |
- | |
221 | uint32_t base = (hash & 0x3ff) << 3; |
- | |
222 | uint32_t i; |
- | |
223 | bool found = false; |
- | |
224 | - | ||
225 | /* Find unused or colliding |
- | |
226 | PTE in PTEG */ |
- | |
227 | for (i = 0; i < 8; i++) { |
- | |
228 | if ((!phte_physical[base + i].v) || |
- | |
229 | ((phte_physical[base + i].vsid == vsid) && |
- | |
230 | (phte_physical[base + i].api == api))) { |
- | |
231 | found = true; |
- | |
232 | break; |
- | |
233 | } |
- | |
234 | } |
178 | } |
235 | 179 | ||
236 | if (!found) { |
180 | if (!found) { |
237 | /* Secondary hash (not) */ |
181 | /* Secondary hash (not) */ |
238 | uint32_t base2 = (~hash & 0x3ff) << 3; |
182 | uint32_t base2 = (~hash & 0x3ff) << 3; |
239 | 183 | ||
240 | /* Find unused or colliding |
- | |
241 | PTE in PTEG */ |
184 | /* Find colliding PTE in PTEG */ |
242 | for (i = 0; i < 8; i++) { |
185 | for (i = 0; i < 8; i++) { |
243 | if ((!phte_physical[base2 + i].v) || |
186 | if ((phte[base2 + i].v) |
244 | ((phte_physical[base2 + i].vsid == vsid) && |
187 | && (phte[base2 + i].vsid == vsid) |
245 | (phte_physical[base2 + i].api == api))) { |
188 | && (phte[base2 + i].api == api) |
- | 189 | && (phte[base2 + i].h == 1)) { |
|
246 | found = true; |
190 | found = true; |
247 | base = base2; |
191 | base = base2; |
248 | h = 1; |
192 | h = 1; |
249 | break; |
193 | break; |
250 | } |
194 | } |
251 | } |
195 | } |
252 | 196 | ||
253 | if (!found) { |
197 | if (!found) { |
254 | // TODO: A/C precedence groups |
198 | /* Find unused PTE in PTEG */ |
- | 199 | for (i = 0; i < 8; i++) { |
|
- | 200 | if (!phte[base2 + i].v) { |
|
- | 201 | found = true; |
|
255 | i = page % 8; |
202 | base = base2; |
- | 203 | h = 1; |
|
- | 204 | break; |
|
- | 205 | } |
|
- | 206 | } |
|
256 | } |
207 | } |
- | 208 | ||
- | 209 | if (!found) |
|
- | 210 | i = RANDI(seed) % 8; |
|
257 | } |
211 | } |
258 | 212 | ||
259 | phte_physical[base + i].v = 1; |
213 | phte[base + i].v = 1; |
260 | phte_physical[base + i].vsid = vsid; |
214 | phte[base + i].vsid = vsid; |
261 | phte_physical[base + i].h = h; |
215 | phte[base + i].h = h; |
262 | phte_physical[base + i].api = api; |
216 | phte[base + i].api = api; |
263 | phte_physical[base + i].rpn = pfn; |
217 | phte[base + i].rpn = pte->pfn; |
264 | phte_physical[base + i].r = 0; |
218 | phte[base + i].r = 0; |
265 | phte_physical[base + i].c = 0; |
219 | phte[base + i].c = 0; |
- | 220 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
|
266 | phte_physical[base + i].pp = 2; // FIXME |
221 | phte[base + i].pp = 2; // FIXME |
267 | } |
222 | } |
268 | 223 | ||
269 | 224 | ||
270 | /** Process Instruction/Data Storage Interrupt |
225 | /** Process Instruction/Data Storage Exception |
271 | * |
226 | * |
272 | * @param n Interrupt vector number. |
227 | * @param n Exception vector number. |
273 | * @param istate Interrupted register context. |
228 | * @param istate Interrupted register context. |
274 | * |
229 | * |
275 | */ |
230 | */ |
276 | void pht_refill(int n, istate_t *istate) |
231 | void pht_refill(int n, istate_t *istate) |
277 | { |
232 | { |
278 | uintptr_t badvaddr; |
233 | uintptr_t badvaddr; |
279 | pte_t *pte; |
234 | pte_t *pte; |
280 | int pfrc; |
235 | int pfrc; |
281 | as_t *as; |
236 | as_t *as; |
282 | bool lock; |
237 | bool lock; |
283 | 238 | ||
284 | if (AS == NULL) { |
239 | if (AS == NULL) { |
285 | as = AS_KERNEL; |
240 | as = AS_KERNEL; |
286 | lock = false; |
241 | lock = false; |
287 | } else { |
242 | } else { |
288 | as = AS; |
243 | as = AS; |
289 | lock = true; |
244 | lock = true; |
290 | } |
245 | } |
291 | 246 | ||
292 | if (n == VECTOR_DATA_STORAGE) { |
247 | if (n == VECTOR_DATA_STORAGE) |
293 | asm volatile ( |
- | |
294 | "mfdar %0\n" |
- | |
295 | : "=r" (badvaddr) |
248 | badvaddr = istate->dar; |
296 | ); |
- | |
297 | } else |
249 | else |
298 | badvaddr = istate->pc; |
250 | badvaddr = istate->pc; |
299 | 251 | ||
300 | page_table_lock(as, lock); |
252 | page_table_lock(as, lock); |
301 | 253 | ||
302 | pte = find_mapping_and_check(as, lock, badvaddr, |
254 | pte = find_mapping_and_check(as, lock, badvaddr, |
303 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
255 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
304 | if (!pte) { |
256 | if (!pte) { |
305 | switch (pfrc) { |
257 | switch (pfrc) { |
306 | case AS_PF_FAULT: |
258 | case AS_PF_FAULT: |
307 | goto fail; |
259 | goto fail; |
308 | break; |
260 | break; |
309 | case AS_PF_DEFER: |
261 | case AS_PF_DEFER: |
310 | /* |
262 | /* |
311 | * The page fault came during copy_from_uspace() |
263 | * The page fault came during copy_from_uspace() |
312 | * or copy_to_uspace(). |
264 | * or copy_to_uspace(). |
313 | */ |
265 | */ |
314 | page_table_unlock(as, lock); |
266 | page_table_unlock(as, lock); |
315 | return; |
267 | return; |
316 | default: |
268 | default: |
317 | panic("Unexpected pfrc (%d)\n", pfrc); |
269 | panic("Unexpected pfrc (%d).", pfrc); |
318 | } |
270 | } |
319 | } |
271 | } |
320 | 272 | ||
321 | pte->a = 1; /* Record access to PTE */ |
273 | pte->accessed = 1; /* Record access to PTE */ |
322 | pht_insert(badvaddr, pte->pfn); |
274 | pht_insert(badvaddr, pte); |
323 | 275 | ||
324 | page_table_unlock(as, lock); |
276 | page_table_unlock(as, lock); |
325 | return; |
277 | return; |
326 | 278 | ||
327 | fail: |
279 | fail: |
328 | page_table_unlock(as, lock); |
280 | page_table_unlock(as, lock); |
329 | pht_refill_fail(badvaddr, istate); |
281 | pht_refill_fail(badvaddr, istate); |
330 | } |
282 | } |
331 | 283 | ||
332 | 284 | ||
333 | /** Process Instruction/Data Storage Interrupt in Real Mode |
285 | /** Process Instruction/Data Storage Exception in Real Mode |
334 | * |
286 | * |
335 | * @param n Interrupt vector number. |
287 | * @param n Exception vector number. |
336 | * @param istate Interrupted register context. |
288 | * @param istate Interrupted register context. |
337 | * |
289 | * |
338 | */ |
290 | */ |
339 | bool pht_real_refill(int n, istate_t *istate) |
291 | bool pht_refill_real(int n, istate_t *istate) |
340 | { |
292 | { |
341 | uintptr_t badvaddr; |
293 | uintptr_t badvaddr; |
342 | 294 | ||
343 | if (n == VECTOR_DATA_STORAGE) { |
295 | if (n == VECTOR_DATA_STORAGE) |
344 | asm volatile ( |
- | |
345 | "mfdar %0\n" |
- | |
346 | : "=r" (badvaddr) |
296 | badvaddr = istate->dar; |
347 | ); |
- | |
348 | } else |
297 | else |
349 | badvaddr = istate->pc; |
298 | badvaddr = istate->pc; |
350 | 299 | ||
351 | uint32_t physmem; |
300 | uint32_t physmem; |
352 | asm volatile ( |
301 | asm volatile ( |
353 | "mfsprg3 %0\n" |
302 | "mfsprg3 %0\n" |
354 | : "=r" (physmem) |
303 | : "=r" (physmem) |
355 | ); |
304 | ); |
356 | 305 | ||
357 | if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) { |
306 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
- | 307 | return false; |
|
- | 308 | ||
- | 309 | uint32_t page = (badvaddr >> 12) & 0xffff; |
|
358 | pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12); |
310 | uint32_t api = (badvaddr >> 22) & 0x3f; |
- | 311 | ||
- | 312 | uint32_t vsid; |
|
- | 313 | asm volatile ( |
|
- | 314 | "mfsrin %0, %1\n" |
|
- | 315 | : "=r" (vsid) |
|
- | 316 | : "r" (badvaddr) |
|
- | 317 | ); |
|
- | 318 | ||
- | 319 | uint32_t sdr1; |
|
- | 320 | asm volatile ( |
|
- | 321 | "mfsdr1 %0\n" |
|
- | 322 | : "=r" (sdr1) |
|
- | 323 | ); |
|
- | 324 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
|
- | 325 | ||
- | 326 | /* Primary hash (xor) */ |
|
- | 327 | uint32_t h = 0; |
|
- | 328 | uint32_t hash = vsid ^ page; |
|
- | 329 | uint32_t base = (hash & 0x3ff) << 3; |
|
- | 330 | uint32_t i; |
|
- | 331 | bool found = false; |
|
- | 332 | ||
- | 333 | /* Find colliding PTE in PTEG */ |
|
- | 334 | for (i = 0; i < 8; i++) { |
|
- | 335 | if ((phte_real[base + i].v) |
|
- | 336 | && (phte_real[base + i].vsid == vsid) |
|
- | 337 | && (phte_real[base + i].api == api) |
|
- | 338 | && (phte_real[base + i].h == 0)) { |
|
359 | return true; |
339 | found = true; |
- | 340 | break; |
|
- | 341 | } |
|
360 | } |
342 | } |
361 | 343 | ||
- | 344 | if (!found) { |
|
- | 345 | /* Find unused PTE in PTEG */ |
|
- | 346 | for (i = 0; i < 8; i++) { |
|
- | 347 | if (!phte_real[base + i].v) { |
|
- | 348 | found = true; |
|
- | 349 | break; |
|
- | 350 | } |
|
- | 351 | } |
|
- | 352 | } |
|
- | 353 | ||
- | 354 | if (!found) { |
|
- | 355 | /* Secondary hash (not) */ |
|
- | 356 | uint32_t base2 = (~hash & 0x3ff) << 3; |
|
- | 357 | ||
- | 358 | /* Find colliding PTE in PTEG */ |
|
- | 359 | for (i = 0; i < 8; i++) { |
|
- | 360 | if ((phte_real[base2 + i].v) |
|
- | 361 | && (phte_real[base2 + i].vsid == vsid) |
|
- | 362 | && (phte_real[base2 + i].api == api) |
|
- | 363 | && (phte_real[base2 + i].h == 1)) { |
|
- | 364 | found = true; |
|
- | 365 | base = base2; |
|
- | 366 | h = 1; |
|
- | 367 | break; |
|
- | 368 | } |
|
- | 369 | } |
|
- | 370 | ||
- | 371 | if (!found) { |
|
- | 372 | /* Find unused PTE in PTEG */ |
|
- | 373 | for (i = 0; i < 8; i++) { |
|
- | 374 | if (!phte_real[base2 + i].v) { |
|
- | 375 | found = true; |
|
- | 376 | base = base2; |
|
- | 377 | h = 1; |
|
- | 378 | break; |
|
- | 379 | } |
|
- | 380 | } |
|
- | 381 | } |
|
- | 382 | ||
- | 383 | if (!found) { |
|
- | 384 | /* Use secondary hash to avoid collisions |
|
- | 385 | with usual PHT refill handler. */ |
|
- | 386 | i = RANDI(seed_real) % 8; |
|
- | 387 | base = base2; |
|
- | 388 | h = 1; |
|
- | 389 | } |
|
- | 390 | } |
|
- | 391 | ||
- | 392 | phte_real[base + i].v = 1; |
|
- | 393 | phte_real[base + i].vsid = vsid; |
|
- | 394 | phte_real[base + i].h = h; |
|
- | 395 | phte_real[base + i].api = api; |
|
- | 396 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
|
- | 397 | phte_real[base + i].r = 0; |
|
- | 398 | phte_real[base + i].c = 0; |
|
- | 399 | phte_real[base + i].wimg = 0; |
|
- | 400 | phte_real[base + i].pp = 2; // FIXME |
|
- | 401 | ||
362 | return false; |
402 | return true; |
- | 403 | } |
|
- | 404 | ||
- | 405 | ||
- | 406 | /** Process ITLB/DTLB Miss Exception in Real Mode |
|
- | 407 | * |
|
- | 408 | * |
|
- | 409 | */ |
|
- | 410 | void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) |
|
- | 411 | { |
|
- | 412 | uint32_t badvaddr = tlbmiss & 0xfffffffc; |
|
- | 413 | ||
- | 414 | uint32_t physmem; |
|
- | 415 | asm volatile ( |
|
- | 416 | "mfsprg3 %0\n" |
|
- | 417 | : "=r" (physmem) |
|
- | 418 | ); |
|
- | 419 | ||
- | 420 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
|
- | 421 | return; // FIXME |
|
- | 422 | ||
- | 423 | ptelo.rpn = KA2PA(badvaddr) >> 12; |
|
- | 424 | ptelo.wimg = 0; |
|
- | 425 | ptelo.pp = 2; // FIXME |
|
- | 426 | ||
- | 427 | uint32_t index = 0; |
|
- | 428 | asm volatile ( |
|
- | 429 | "mtspr 981, %0\n" |
|
- | 430 | "mtspr 982, %1\n" |
|
- | 431 | "tlbld %2\n" |
|
- | 432 | "tlbli %2\n" |
|
- | 433 | : "=r" (index) |
|
- | 434 | : "r" (ptehi), |
|
- | 435 | "r" (ptelo) |
|
- | 436 | ); |
|
363 | } |
437 | } |
364 | 438 | ||
365 | 439 | ||
366 | void tlb_arch_init(void) |
440 | void tlb_arch_init(void) |
367 | { |
441 | { |
368 | tlb_invalidate_all(); |
442 | tlb_invalidate_all(); |
369 | } |
443 | } |
370 | 444 | ||
371 | 445 | ||
372 | void tlb_invalidate_all(void) |
446 | void tlb_invalidate_all(void) |
373 | { |
447 | { |
- | 448 | uint32_t index; |
|
374 | asm volatile ( |
449 | asm volatile ( |
- | 450 | "li %0, 0\n" |
|
- | 451 | "sync\n" |
|
- | 452 | ||
- | 453 | TLB_FLUSH |
|
- | 454 | TLB_FLUSH |
|
- | 455 | TLB_FLUSH |
|
- | 456 | TLB_FLUSH |
|
- | 457 | TLB_FLUSH |
|
- | 458 | TLB_FLUSH |
|
- | 459 | TLB_FLUSH |
|
- | 460 | TLB_FLUSH |
|
- | 461 | ||
- | 462 | TLB_FLUSH |
|
- | 463 | TLB_FLUSH |
|
- | 464 | TLB_FLUSH |
|
- | 465 | TLB_FLUSH |
|
- | 466 | TLB_FLUSH |
|
- | 467 | TLB_FLUSH |
|
- | 468 | TLB_FLUSH |
|
- | 469 | TLB_FLUSH |
|
- | 470 | ||
- | 471 | TLB_FLUSH |
|
- | 472 | TLB_FLUSH |
|
- | 473 | TLB_FLUSH |
|
- | 474 | TLB_FLUSH |
|
- | 475 | TLB_FLUSH |
|
- | 476 | TLB_FLUSH |
|
- | 477 | TLB_FLUSH |
|
- | 478 | TLB_FLUSH |
|
- | 479 | ||
- | 480 | TLB_FLUSH |
|
- | 481 | TLB_FLUSH |
|
- | 482 | TLB_FLUSH |
|
- | 483 | TLB_FLUSH |
|
- | 484 | TLB_FLUSH |
|
- | 485 | TLB_FLUSH |
|
- | 486 | TLB_FLUSH |
|
- | 487 | TLB_FLUSH |
|
- | 488 | ||
- | 489 | TLB_FLUSH |
|
- | 490 | TLB_FLUSH |
|
- | 491 | TLB_FLUSH |
|
- | 492 | TLB_FLUSH |
|
- | 493 | TLB_FLUSH |
|
- | 494 | TLB_FLUSH |
|
- | 495 | TLB_FLUSH |
|
- | 496 | TLB_FLUSH |
|
- | 497 | ||
- | 498 | TLB_FLUSH |
|
- | 499 | TLB_FLUSH |
|
- | 500 | TLB_FLUSH |
|
- | 501 | TLB_FLUSH |
|
- | 502 | TLB_FLUSH |
|
- | 503 | TLB_FLUSH |
|
- | 504 | TLB_FLUSH |
|
- | 505 | TLB_FLUSH |
|
- | 506 | ||
- | 507 | TLB_FLUSH |
|
- | 508 | TLB_FLUSH |
|
- | 509 | TLB_FLUSH |
|
- | 510 | TLB_FLUSH |
|
- | 511 | TLB_FLUSH |
|
- | 512 | TLB_FLUSH |
|
- | 513 | TLB_FLUSH |
|
- | 514 | TLB_FLUSH |
|
- | 515 | ||
- | 516 | TLB_FLUSH |
|
- | 517 | TLB_FLUSH |
|
- | 518 | TLB_FLUSH |
|
- | 519 | TLB_FLUSH |
|
- | 520 | TLB_FLUSH |
|
- | 521 | TLB_FLUSH |
|
- | 522 | TLB_FLUSH |
|
- | 523 | TLB_FLUSH |
|
- | 524 | ||
375 | "tlbia\n" |
525 | "eieio\n" |
376 | "tlbsync\n" |
526 | "tlbsync\n" |
- | 527 | "sync\n" |
|
- | 528 | : "=r" (index) |
|
377 | ); |
529 | ); |
378 | } |
530 | } |
379 | 531 | ||
380 | 532 | ||
381 | void tlb_invalidate_asid(asid_t asid) |
533 | void tlb_invalidate_asid(asid_t asid) |
382 | { |
534 | { |
383 | uint32_t sdr1; |
535 | uint32_t sdr1; |
384 | asm volatile ( |
536 | asm volatile ( |
385 | "mfsdr1 %0\n" |
537 | "mfsdr1 %0\n" |
386 | : "=r" (sdr1) |
538 | : "=r" (sdr1) |
387 | ); |
539 | ); |
388 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
540 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
389 | 541 | ||
390 | uint32_t i; |
542 | uint32_t i; |
391 | for (i = 0; i < 8192; i++) { |
543 | for (i = 0; i < 8192; i++) { |
392 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
544 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
393 | (phte[i].vsid < ((asid << 4) + 16))) |
545 | (phte[i].vsid < ((asid << 4) + 16))) |
394 | phte[i].v = 0; |
546 | phte[i].v = 0; |
395 | } |
547 | } |
396 | tlb_invalidate_all(); |
548 | tlb_invalidate_all(); |
397 | } |
549 | } |
398 | 550 | ||
399 | 551 | ||
400 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
552 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
401 | { |
553 | { |
402 | // TODO |
554 | // TODO |
403 | tlb_invalidate_all(); |
555 | tlb_invalidate_all(); |
404 | } |
556 | } |
405 | 557 | ||
406 | 558 | ||
407 | #define PRINT_BAT(name, ureg, lreg) \ |
559 | #define PRINT_BAT(name, ureg, lreg) \ |
408 | asm volatile ( \ |
560 | asm volatile ( \ |
409 | "mfspr %0," #ureg "\n" \ |
561 | "mfspr %0," #ureg "\n" \ |
410 | "mfspr %1," #lreg "\n" \ |
562 | "mfspr %1," #lreg "\n" \ |
411 | : "=r" (upper), "=r" (lower) \ |
563 | : "=r" (upper), "=r" (lower) \ |
412 | ); \ |
564 | ); \ |
413 | mask = (upper & 0x1ffc) >> 2; \ |
565 | mask = (upper & 0x1ffc) >> 2; \ |
414 | if (upper & 3) { \ |
566 | if (upper & 3) { \ |
415 | uint32_t tmp = mask; \ |
567 | uint32_t tmp = mask; \ |
416 | length = 128; \ |
568 | length = 128; \ |
417 | while (tmp) { \ |
569 | while (tmp) { \ |
418 | if ((tmp & 1) == 0) { \ |
570 | if ((tmp & 1) == 0) { \ |
419 | printf("ibat[0]: error in mask\n"); \ |
571 | printf("ibat[0]: error in mask\n"); \ |
420 | break; \ |
572 | break; \ |
421 | } \ |
573 | } \ |
422 | length <<= 1; \ |
574 | length <<= 1; \ |
423 | tmp >>= 1; \ |
575 | tmp >>= 1; \ |
424 | } \ |
576 | } \ |
425 | } else \ |
577 | } else \ |
426 | length = 0; \ |
578 | length = 0; \ |
427 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
579 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
428 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
580 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
429 | lower & 0xffff0000, length, mask, \ |
581 | lower & 0xffff0000, length, mask, \ |
430 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
582 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
431 | (upper & 1) ? " user" : ""); |
583 | (upper & 1) ? " user" : ""); |
432 | 584 | ||
433 | 585 | ||
434 | void tlb_print(void) |
586 | void tlb_print(void) |
435 | { |
587 | { |
436 | uint32_t sr; |
588 | uint32_t sr; |
437 | 589 | ||
438 | for (sr = 0; sr < 16; sr++) { |
590 | for (sr = 0; sr < 16; sr++) { |
439 | uint32_t vsid; |
591 | uint32_t vsid; |
440 | asm volatile ( |
592 | asm volatile ( |
441 | "mfsrin %0, %1\n" |
593 | "mfsrin %0, %1\n" |
442 | : "=r" (vsid) |
594 | : "=r" (vsid) |
443 | : "r" (sr << 28) |
595 | : "r" (sr << 28) |
444 | ); |
596 | ); |
445 | printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, |
597 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
446 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
598 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
447 | ((vsid >> 30) & 1) ? " supervisor" : "", |
599 | ((vsid >> 30) & 1) ? " supervisor" : "", |
448 | ((vsid >> 29) & 1) ? " user" : ""); |
600 | ((vsid >> 29) & 1) ? " user" : ""); |
449 | } |
601 | } |
450 | 602 | ||
451 | uint32_t upper; |
603 | uint32_t upper; |
452 | uint32_t lower; |
604 | uint32_t lower; |
453 | uint32_t mask; |
605 | uint32_t mask; |
454 | uint32_t length; |
606 | uint32_t length; |
455 | 607 | ||
456 | PRINT_BAT("ibat[0]", 528, 529); |
608 | PRINT_BAT("ibat[0]", 528, 529); |
457 | PRINT_BAT("ibat[1]", 530, 531); |
609 | PRINT_BAT("ibat[1]", 530, 531); |
458 | PRINT_BAT("ibat[2]", 532, 533); |
610 | PRINT_BAT("ibat[2]", 532, 533); |
459 | PRINT_BAT("ibat[3]", 534, 535); |
611 | PRINT_BAT("ibat[3]", 534, 535); |
460 | 612 | ||
461 | PRINT_BAT("dbat[0]", 536, 537); |
613 | PRINT_BAT("dbat[0]", 536, 537); |
462 | PRINT_BAT("dbat[1]", 538, 539); |
614 | PRINT_BAT("dbat[1]", 538, 539); |
463 | PRINT_BAT("dbat[2]", 540, 541); |
615 | PRINT_BAT("dbat[2]", 540, 541); |
464 | PRINT_BAT("dbat[3]", 542, 543); |
616 | PRINT_BAT("dbat[3]", 542, 543); |
465 | } |
617 | } |
466 | 618 | ||
467 | /** @} |
619 | /** @} |
468 | */ |
620 | */ |
469 | 621 |