WebSVN – HelenOS – Diff – /branches/tracing/kernel/arch/ppc32/src/mm/tlb.c


/*
 * Copyright (c) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32mm
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <mm/as.h>
#include <arch.h>
#include <print.h>
#include <symtab.h>
 
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The as->lock must be held on entry to this function
 * if lock is true.
 *
 * @param as        Address space.
 * @param lock      Lock/unlock the address space.
 * @param badvaddr  Faulting virtual address.
 * @param access    Access mode that caused the fault.
 * @param istate    Pointer to interrupted state.
 * @param pfrc      Pointer to variable where as_page_fault() return code
 *          will be stored.
 * @return      PTE on success, NULL otherwise.
 *
 */
static pte_t *
find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
    istate_t *istate, int *pfrc)
{
    /*
     * Check if the mapping exists in page tables.
     */
    pte_t *pte = page_mapping_find(as, badvaddr);
    if ((pte) && (pte->p)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
   
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(as, lock);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(as, lock);
            pte = page_mapping_find(as, badvaddr);
            ASSERT((pte) && (pte->p));
            *pfrc = 0;
            return pte;
        case AS_PF_DEFER:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        case AS_PF_FAULT:
            page_table_lock(as, lock);
            printf("Page fault.\n");
            *pfrc = rc;
            return NULL;
        default:
            panic("unexpected rc (%d)\n", rc);
        }  
    }
}
 
 
static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->pc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->lr);
    if (s)
        sym2 = s;
    panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr,
        istate->pc, symbol, sym2);
}
 
 
static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) &&
            (phte[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte[base2 + i].v) ||
                ((phte[base2 + i].vsid == vsid) &&
                (phte[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte[base + i].v = 1;
    phte[base + i].vsid = vsid;
    phte[base + i].h = h;
    phte[base + i].api = api;
    phte[base + i].rpn = pfn;
    phte[base + i].r = 0;
    phte[base + i].c = 0;
    phte[base + i].pp = 2; // FIXME
}
 
 
static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte_physical[base + i].v) ||
            ((phte_physical[base + i].vsid == vsid) &&
            (phte_physical[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte_physical[base2 + i].v) ||
                ((phte_physical[base2 + i].vsid == vsid) &&
                (phte_physical[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte_physical[base + i].v = 1;
    phte_physical[base + i].vsid = vsid;
    phte_physical[base + i].h = h;
    phte_physical[base + i].api = api;
    phte_physical[base + i].rpn = pfn;
    phte_physical[base + i].r = 0;
    phte_physical[base + i].c = 0;
    phte_physical[base + i].pp = 2; // FIXME
}
 
 
/** Process Instruction/Data Storage Interrupt
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
void pht_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
    as_t *as;
    bool lock;
   
    if (AS == NULL) {
        as = AS_KERNEL;
        lock = false;
    } else {
        as = AS;
        lock = true;
    }
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
       
    page_table_lock(as, lock);
   
    pte = find_mapping_and_check(as, lock, badvaddr,
        PF_ACCESS_READ /* FIXME */, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(as, lock);
            return;
        default:
            panic("Unexpected pfrc (%d)\n", pfrc);
        }
    }
   
    pte->a = 1; /* Record access to PTE */
    pht_insert(badvaddr, pte->pfn);
   
    page_table_unlock(as, lock);
    return;
   
fail:
    page_table_unlock(as, lock);
    pht_refill_fail(badvaddr, istate);
}
 
 
/** Process Instruction/Data Storage Interrupt in Real Mode
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
bool pht_real_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
   
    uint32_t physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
        pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
        return true;
    }
   
    return false;
}
 
 
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_all(void)
{
    asm volatile (
        "tlbia\n"
        "tlbsync\n"
    );
}
 
 
void tlb_invalidate_asid(asid_t asid)
{
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    uint32_t i;
    for (i = 0; i < 8192; i++) {
        if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
            (phte[i].vsid < ((asid << 4) + 16)))
            phte[i].v = 0;
    }
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    // TODO
    tlb_invalidate_all();
}
 
 
#define PRINT_BAT(name, ureg, lreg) \
    asm volatile ( \
        "mfspr %0," #ureg "\n" \
        "mfspr %1," #lreg "\n" \
        : "=r" (upper), "=r" (lower) \
    ); \
    mask = (upper & 0x1ffc) >> 2; \
    if (upper & 3) { \
        uint32_t tmp = mask; \
        length = 128; \
        while (tmp) { \
            if ((tmp & 1) == 0) { \
                printf("ibat[0]: error in mask\n"); \
                break; \
            } \
            length <<= 1; \
            tmp >>= 1; \
        } \
    } else \
        length = 0; \
    printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
        sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
        lower & 0xffff0000, length, mask, \
        ((upper >> 1) & 1) ? " supervisor" : "", \
        (upper & 1) ? " user" : "");
 
 
void tlb_print(void)
{
    uint32_t sr;
   
    for (sr = 0; sr < 16; sr++) {
        uint32_t vsid;
        asm volatile (
            "mfsrin %0, %1\n"
            : "=r" (vsid)
            : "r" (sr << 28)
        );
        printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
            sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
            ((vsid >> 30) & 1) ? " supervisor" : "",
            ((vsid >> 29) & 1) ? " user" : "");
    }
   
    uint32_t upper;
    uint32_t lower;
    uint32_t mask;
    uint32_t length;
   
    PRINT_BAT("ibat[0]", 528, 529);
    PRINT_BAT("ibat[1]", 530, 531);
    PRINT_BAT("ibat[2]", 532, 533);
    PRINT_BAT("ibat[3]", 534, 535);
   
    PRINT_BAT("dbat[0]", 536, 537);
    PRINT_BAT("dbat[1]", 538, 539);
    PRINT_BAT("dbat[2]", 540, 541);
    PRINT_BAT("dbat[3]", 542, 543);
}
 
/** @}
 */
 

Rev 2787	Rev 3425
1	/*	1	/*
2	* Copyright (c) 2006 Martin Decky	2	* Copyright (c) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32mm	29	/** @addtogroup ppc32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <mm/tlb.h>	35	#include <mm/tlb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <mm/as.h>	38	#include <mm/as.h>
39	#include <arch.h>	39	#include <arch.h>
40	#include <print.h>	40	#include <print.h>
41	#include <symtab.h>	41	#include <symtab.h>
42		42
43		43
44	/** Try to find PTE for faulting address	44	/** Try to find PTE for faulting address
45	*	45	*
46	* Try to find PTE for faulting address.	46	* Try to find PTE for faulting address.
47	* The as->lock must be held on entry to this function	47	* The as->lock must be held on entry to this function
48	* if lock is true.	48	* if lock is true.
49	*	49	*
50	* @param as Address space.	50	* @param as Address space.
51	* @param lock Lock/unlock the address space.	51	* @param lock Lock/unlock the address space.
52	* @param badvaddr Faulting virtual address.	52	* @param badvaddr Faulting virtual address.
53	* @param access Access mode that caused the fault.	53	* @param access Access mode that caused the fault.
54	* @param istate Pointer to interrupted state.	54	* @param istate Pointer to interrupted state.
55	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	55	* @param pfrc Pointer to variable where as_page_fault() return code
-		56	* will be stored.
56	* @return PTE on success, NULL otherwise.	57	* @return PTE on success, NULL otherwise.
57	*	58	*
58	*/	59	*/
-		60	static pte_t *
59	static pte_t find_mapping_and_check(as_t as, bool lock, uintptr_t badvaddr, int access, istate_t istate, int pfrc)	61	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
-		62	istate_t istate, int pfrc)
60	{	63	{
61	/*	64	/*
62	* Check if the mapping exists in page tables.	65	* Check if the mapping exists in page tables.
63	*/	66	*/
64	pte_t *pte = page_mapping_find(as, badvaddr);	67	pte_t *pte = page_mapping_find(as, badvaddr);
65	if ((pte) && (pte->p)) {	68	if ((pte) && (pte->p)) {
66	/*	69	/*
67	* Mapping found in page tables.	70	* Mapping found in page tables.
68	* Immediately succeed.	71	* Immediately succeed.
69	*/	72	*/
70	return pte;	73	return pte;
71	} else {	74	} else {
72	int rc;	75	int rc;
73		76
74	/*	77	/*
75	* Mapping not found in page tables.	78	* Mapping not found in page tables.
76	* Resort to higher-level page fault handler.	79	* Resort to higher-level page fault handler.
77	*/	80	*/
78	page_table_unlock(as, lock);	81	page_table_unlock(as, lock);
79	switch (rc = as_page_fault(badvaddr, access, istate)) {	82	switch (rc = as_page_fault(badvaddr, access, istate)) {
80	case AS_PF_OK:	83	case AS_PF_OK:
81	/*	84	/*
82	* The higher-level page fault handler succeeded,	85	* The higher-level page fault handler succeeded,
83	* The mapping ought to be in place.	86	* The mapping ought to be in place.
84	*/	87	*/
85	page_table_lock(as, lock);	88	page_table_lock(as, lock);
86	pte = page_mapping_find(as, badvaddr);	89	pte = page_mapping_find(as, badvaddr);
87	ASSERT((pte) && (pte->p));	90	ASSERT((pte) && (pte->p));
88	*pfrc = 0;	91	*pfrc = 0;
89	return pte;	92	return pte;
90	case AS_PF_DEFER:	93	case AS_PF_DEFER:
91	page_table_lock(as, lock);	94	page_table_lock(as, lock);
92	*pfrc = rc;	95	*pfrc = rc;
93	return NULL;	96	return NULL;
94	case AS_PF_FAULT:	97	case AS_PF_FAULT:
95	page_table_lock(as, lock);	98	page_table_lock(as, lock);
96	printf("Page fault.\n");	99	printf("Page fault.\n");
97	*pfrc = rc;	100	*pfrc = rc;
98	return NULL;	101	return NULL;
99	default:	102	default:
100	panic("unexpected rc (%d)\n", rc);	103	panic("unexpected rc (%d)\n", rc);
101	}	104	}
102	}	105	}
103	}	106	}
104		107
105		108
106	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)	109	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
107	{	110	{
108	char *symbol = "";	111	char *symbol = "";
109	char *sym2 = "";	112	char *sym2 = "";
110		113
111	char *s = get_symtab_entry(istate->pc);	114	char *s = get_symtab_entry(istate->pc);
112	if (s)	115	if (s)
113	symbol = s;	116	symbol = s;
114	s = get_symtab_entry(istate->lr);	117	s = get_symtab_entry(istate->lr);
115	if (s)	118	if (s)
116	sym2 = s;	119	sym2 = s;
117	panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);	120	panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr,
-		121	istate->pc, symbol, sym2);
118	}	122	}
119		123
120		124
121	static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)	125	static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)
122	{	126	{
123	uint32_t page = (vaddr >> 12) & 0xffff;	127	uint32_t page = (vaddr >> 12) & 0xffff;
124	uint32_t api = (vaddr >> 22) & 0x3f;	128	uint32_t api = (vaddr >> 22) & 0x3f;
125		129
126	uint32_t vsid;	130	uint32_t vsid;
127	asm volatile (	131	asm volatile (
128	"mfsrin %0, %1\n"	132	"mfsrin %0, %1\n"
129	: "=r" (vsid)	133	: "=r" (vsid)
130	: "r" (vaddr)	134	: "r" (vaddr)
131	);	135	);
132		136
133	uint32_t sdr1;	137	uint32_t sdr1;
134	asm volatile (	138	asm volatile (
135	"mfsdr1 %0\n"	139	"mfsdr1 %0\n"
136	: "=r" (sdr1)	140	: "=r" (sdr1)
137	);	141	);
138	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	142	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
139		143
140	/* Primary hash (xor) */	144	/* Primary hash (xor) */
141	uint32_t h = 0;	145	uint32_t h = 0;
142	uint32_t hash = vsid ^ page;	146	uint32_t hash = vsid ^ page;
143	uint32_t base = (hash & 0x3ff) << 3;	147	uint32_t base = (hash & 0x3ff) << 3;
144	uint32_t i;	148	uint32_t i;
145	bool found = false;	149	bool found = false;
146		150
147	/* Find unused or colliding	151	/* Find unused or colliding
148	PTE in PTEG */	152	PTE in PTEG */
149	for (i = 0; i < 8; i++) {	153	for (i = 0; i < 8; i++) {
150	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {	154	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) &&
-		155	(phte[base + i].api == api))) {
151	found = true;	156	found = true;
152	break;	157	break;
153	}	158	}
154	}	159	}
155		160
156	if (!found) {	161	if (!found) {
157	/* Secondary hash (not) */	162	/* Secondary hash (not) */
158	uint32_t base2 = (~hash & 0x3ff) << 3;	163	uint32_t base2 = (~hash & 0x3ff) << 3;
159		164
160	/* Find unused or colliding	165	/* Find unused or colliding
161	PTE in PTEG */	166	PTE in PTEG */
162	for (i = 0; i < 8; i++) {	167	for (i = 0; i < 8; i++) {
-		168	if ((!phte[base2 + i].v) \|\|
163	if ((!phte[base2 + i].v) \|\| ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {	169	((phte[base2 + i].vsid == vsid) &&
-		170	(phte[base2 + i].api == api))) {
164	found = true;	171	found = true;
165	base = base2;	172	base = base2;
166	h = 1;	173	h = 1;
167	break;	174	break;
168	}	175	}
169	}	176	}
170		177
171	if (!found) {	178	if (!found) {
172	// TODO: A/C precedence groups	179	// TODO: A/C precedence groups
173	i = page % 8;	180	i = page % 8;
174	}	181	}
175	}	182	}
176		183
177	phte[base + i].v = 1;	184	phte[base + i].v = 1;
178	phte[base + i].vsid = vsid;	185	phte[base + i].vsid = vsid;
179	phte[base + i].h = h;	186	phte[base + i].h = h;
180	phte[base + i].api = api;	187	phte[base + i].api = api;
181	phte[base + i].rpn = pfn;	188	phte[base + i].rpn = pfn;
182	phte[base + i].r = 0;	189	phte[base + i].r = 0;
183	phte[base + i].c = 0;	190	phte[base + i].c = 0;
184	phte[base + i].pp = 2; // FIXME	191	phte[base + i].pp = 2; // FIXME
185	}	192	}
186		193
187		194
188	static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)	195	static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
189	{	196	{
190	uint32_t page = (vaddr >> 12) & 0xffff;	197	uint32_t page = (vaddr >> 12) & 0xffff;
191	uint32_t api = (vaddr >> 22) & 0x3f;	198	uint32_t api = (vaddr >> 22) & 0x3f;
192		199
193	uint32_t vsid;	200	uint32_t vsid;
194	asm volatile (	201	asm volatile (
195	"mfsrin %0, %1\n"	202	"mfsrin %0, %1\n"
196	: "=r" (vsid)	203	: "=r" (vsid)
197	: "r" (vaddr)	204	: "r" (vaddr)
198	);	205	);
199		206
200	uint32_t sdr1;	207	uint32_t sdr1;
201	asm volatile (	208	asm volatile (
202	"mfsdr1 %0\n"	209	"mfsdr1 %0\n"
203	: "=r" (sdr1)	210	: "=r" (sdr1)
204	);	211	);
205	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);	212	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);
206		213
207	/* Primary hash (xor) */	214	/* Primary hash (xor) */
208	uint32_t h = 0;	215	uint32_t h = 0;
209	uint32_t hash = vsid ^ page;	216	uint32_t hash = vsid ^ page;
210	uint32_t base = (hash & 0x3ff) << 3;	217	uint32_t base = (hash & 0x3ff) << 3;
211	uint32_t i;	218	uint32_t i;
212	bool found = false;	219	bool found = false;
213		220
214	/* Find unused or colliding	221	/* Find unused or colliding
215	PTE in PTEG */	222	PTE in PTEG */
216	for (i = 0; i < 8; i++) {	223	for (i = 0; i < 8; i++) {
-		224	if ((!phte_physical[base + i].v) \|\|
217	if ((!phte_physical[base + i].v) \|\| ((phte_physical[base + i].vsid == vsid) && (phte_physical[base + i].api == api))) {	225	((phte_physical[base + i].vsid == vsid) &&
-		226	(phte_physical[base + i].api == api))) {
218	found = true;	227	found = true;
219	break;	228	break;
220	}	229	}
221	}	230	}
222		231
223	if (!found) {	232	if (!found) {
224	/* Secondary hash (not) */	233	/* Secondary hash (not) */
225	uint32_t base2 = (~hash & 0x3ff) << 3;	234	uint32_t base2 = (~hash & 0x3ff) << 3;
226		235
227	/* Find unused or colliding	236	/* Find unused or colliding
228	PTE in PTEG */	237	PTE in PTEG */
229	for (i = 0; i < 8; i++) {	238	for (i = 0; i < 8; i++) {
-		239	if ((!phte_physical[base2 + i].v) \|\|
230	if ((!phte_physical[base2 + i].v) \|\| ((phte_physical[base2 + i].vsid == vsid) && (phte_physical[base2 + i].api == api))) {	240	((phte_physical[base2 + i].vsid == vsid) &&
-		241	(phte_physical[base2 + i].api == api))) {
231	found = true;	242	found = true;
232	base = base2;	243	base = base2;
233	h = 1;	244	h = 1;
234	break;	245	break;
235	}	246	}
236	}	247	}
237		248
238	if (!found) {	249	if (!found) {
239	// TODO: A/C precedence groups	250	// TODO: A/C precedence groups
240	i = page % 8;	251	i = page % 8;
241	}	252	}
242	}	253	}
243		254
244	phte_physical[base + i].v = 1;	255	phte_physical[base + i].v = 1;
245	phte_physical[base + i].vsid = vsid;	256	phte_physical[base + i].vsid = vsid;
246	phte_physical[base + i].h = h;	257	phte_physical[base + i].h = h;
247	phte_physical[base + i].api = api;	258	phte_physical[base + i].api = api;
248	phte_physical[base + i].rpn = pfn;	259	phte_physical[base + i].rpn = pfn;
249	phte_physical[base + i].r = 0;	260	phte_physical[base + i].r = 0;
250	phte_physical[base + i].c = 0;	261	phte_physical[base + i].c = 0;
251	phte_physical[base + i].pp = 2; // FIXME	262	phte_physical[base + i].pp = 2; // FIXME
252	}	263	}
253		264
254		265
255	/** Process Instruction/Data Storage Interrupt	266	/** Process Instruction/Data Storage Interrupt
256	*	267	*
257	* @param n Interrupt vector number.	268	* @param n Interrupt vector number.
258	* @param istate Interrupted register context.	269	* @param istate Interrupted register context.
259	*	270	*
260	*/	271	*/
261	void pht_refill(int n, istate_t *istate)	272	void pht_refill(int n, istate_t *istate)
262	{	273	{
263	uintptr_t badvaddr;	274	uintptr_t badvaddr;
264	pte_t *pte;	275	pte_t *pte;
265	int pfrc;	276	int pfrc;
266	as_t *as;	277	as_t *as;
267	bool lock;	278	bool lock;
268		279
269	if (AS == NULL) {	280	if (AS == NULL) {
270	as = AS_KERNEL;	281	as = AS_KERNEL;
271	lock = false;	282	lock = false;
272	} else {	283	} else {
273	as = AS;	284	as = AS;
274	lock = true;	285	lock = true;
275	}	286	}
276		287
277	if (n == VECTOR_DATA_STORAGE) {	288	if (n == VECTOR_DATA_STORAGE) {
278	asm volatile (	289	asm volatile (
279	"mfdar %0\n"	290	"mfdar %0\n"
280	: "=r" (badvaddr)	291	: "=r" (badvaddr)
281	);	292	);
282	} else	293	} else
283	badvaddr = istate->pc;	294	badvaddr = istate->pc;
284		295
285	page_table_lock(as, lock);	296	page_table_lock(as, lock);
286		297
287	pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);	298	pte = find_mapping_and_check(as, lock, badvaddr,
-		299	PF_ACCESS_READ /* FIXME */, istate, &pfrc);
288	if (!pte) {	300	if (!pte) {
289	switch (pfrc) {	301	switch (pfrc) {
290	case AS_PF_FAULT:	302	case AS_PF_FAULT:
291	goto fail;	303	goto fail;
292	break;	304	break;
293	case AS_PF_DEFER:	305	case AS_PF_DEFER:
294	/*	306	/*
295	* The page fault came during copy_from_uspace()	307	* The page fault came during copy_from_uspace()
296	* or copy_to_uspace().	308	* or copy_to_uspace().
297	*/	309	*/
298	page_table_unlock(as, lock);	310	page_table_unlock(as, lock);
299	return;	311	return;
300	default:	312	default:
301	panic("Unexpected pfrc (%d)\n", pfrc);	313	panic("Unexpected pfrc (%d)\n", pfrc);
302	}	314	}
303	}	315	}
304		316
305	pte->a = 1; /* Record access to PTE */	317	pte->a = 1; /* Record access to PTE */
306	pht_insert(badvaddr, pte->pfn);	318	pht_insert(badvaddr, pte->pfn);
307		319
308	page_table_unlock(as, lock);	320	page_table_unlock(as, lock);
309	return;	321	return;
310		322
311	fail:	323	fail:
312	page_table_unlock(as, lock);	324	page_table_unlock(as, lock);
313	pht_refill_fail(badvaddr, istate);	325	pht_refill_fail(badvaddr, istate);
314	}	326	}
315		327
316		328
317	/** Process Instruction/Data Storage Interrupt in Real Mode	329	/** Process Instruction/Data Storage Interrupt in Real Mode
318	*	330	*
319	* @param n Interrupt vector number.	331	* @param n Interrupt vector number.
320	* @param istate Interrupted register context.	332	* @param istate Interrupted register context.
321	*	333	*
322	*/	334	*/
323	bool pht_real_refill(int n, istate_t *istate)	335	bool pht_real_refill(int n, istate_t *istate)
324	{	336	{
325	uintptr_t badvaddr;	337	uintptr_t badvaddr;
326		338
327	if (n == VECTOR_DATA_STORAGE) {	339	if (n == VECTOR_DATA_STORAGE) {
328	asm volatile (	340	asm volatile (
329	"mfdar %0\n"	341	"mfdar %0\n"
330	: "=r" (badvaddr)	342	: "=r" (badvaddr)
331	);	343	);
332	} else	344	} else
333	badvaddr = istate->pc;	345	badvaddr = istate->pc;
334		346
335	uint32_t physmem;	347	uint32_t physmem;
336	asm volatile (	348	asm volatile (
337	"mfsprg3 %0\n"	349	"mfsprg3 %0\n"
338	: "=r" (physmem)	350	: "=r" (physmem)
339	);	351	);
340		352
341	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {	353	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
342	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);	354	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
343	return true;	355	return true;
344	}	356	}
345		357
346	return false;	358	return false;
347	}	359	}
348		360
349		361
350	void tlb_arch_init(void)	362	void tlb_arch_init(void)
351	{	363	{
352	tlb_invalidate_all();	364	tlb_invalidate_all();
353	}	365	}
354		366
355		367
356	void tlb_invalidate_all(void)	368	void tlb_invalidate_all(void)
357	{	369	{
358	asm volatile (	370	asm volatile (
359	"tlbia\n"	371	"tlbia\n"
360	"tlbsync\n"	372	"tlbsync\n"
361	);	373	);
362	}	374	}
363		375
364		376
365	void tlb_invalidate_asid(asid_t asid)	377	void tlb_invalidate_asid(asid_t asid)
366	{	378	{
367	uint32_t sdr1;	379	uint32_t sdr1;
368	asm volatile (	380	asm volatile (
369	"mfsdr1 %0\n"	381	"mfsdr1 %0\n"
370	: "=r" (sdr1)	382	: "=r" (sdr1)
371	);	383	);
372	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	384	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
373		385
374	uint32_t i;	386	uint32_t i;
375	for (i = 0; i < 8192; i++) {	387	for (i = 0; i < 8192; i++) {
376	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && (phte[i].vsid < ((asid << 4) + 16)))	388	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
-		389	(phte[i].vsid < ((asid << 4) + 16)))
377	phte[i].v = 0;	390	phte[i].v = 0;
378	}	391	}
379	tlb_invalidate_all();	392	tlb_invalidate_all();
380	}	393	}
381		394
382		395
383	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	396	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
384	{	397	{
385	// TODO	398	// TODO
386	tlb_invalidate_all();	399	tlb_invalidate_all();
387	}	400	}
388		401
389		402
390	#define PRINT_BAT(name, ureg, lreg) \	403	#define PRINT_BAT(name, ureg, lreg) \
391	asm volatile ( \	404	asm volatile ( \
392	"mfspr %0," #ureg "\n" \	405	"mfspr %0," #ureg "\n" \
393	"mfspr %1," #lreg "\n" \	406	"mfspr %1," #lreg "\n" \
394	: "=r" (upper), "=r" (lower) \	407	: "=r" (upper), "=r" (lower) \
395	); \	408	); \
396	mask = (upper & 0x1ffc) >> 2; \	409	mask = (upper & 0x1ffc) >> 2; \
397	if (upper & 3) { \	410	if (upper & 3) { \
398	uint32_t tmp = mask; \	411	uint32_t tmp = mask; \
399	length = 128; \	412	length = 128; \
400	while (tmp) { \	413	while (tmp) { \
401	if ((tmp & 1) == 0) { \	414	if ((tmp & 1) == 0) { \
402	printf("ibat[0]: error in mask\n"); \	415	printf("ibat[0]: error in mask\n"); \
403	break; \	416	break; \
404	} \	417	} \
405	length <<= 1; \	418	length <<= 1; \
406	tmp >>= 1; \	419	tmp >>= 1; \
407	} \	420	} \
408	} else \	421	} else \
409	length = 0; \	422	length = 0; \
410	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, lower & 0xffff0000, length, mask, ((upper >> 1) & 1) ? " supervisor" : "", (upper & 1) ? " user" : "");	423	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", \
-		424	sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
-		425	lower & 0xffff0000, length, mask, \
-		426	((upper >> 1) & 1) ? " supervisor" : "", \
-		427	(upper & 1) ? " user" : "");
411		428
412		429
413	void tlb_print(void)	430	void tlb_print(void)
414	{	431	{
415	uint32_t sr;	432	uint32_t sr;
416		433
417	for (sr = 0; sr < 16; sr++) {	434	for (sr = 0; sr < 16; sr++) {
418	uint32_t vsid;	435	uint32_t vsid;
419	asm volatile (	436	asm volatile (
420	"mfsrin %0, %1\n"	437	"mfsrin %0, %1\n"
421	: "=r" (vsid)	438	: "=r" (vsid)
422	: "r" (sr << 28)	439	: "r" (sr << 28)
423	);	440	);
-		441	printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
424	printf("vsid[%d]: VSID=%.p (ASID=%d)%s%s\n", sr, sizeof(vsid) 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, ((vsid >> 30) & 1) ? " supervisor" : "", ((vsid >> 29) & 1) ? " user" : "");	442	sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
-		443	((vsid >> 30) & 1) ? " supervisor" : "",
-		444	((vsid >> 29) & 1) ? " user" : "");
425	}	445	}
426		446
427	uint32_t upper;	447	uint32_t upper;
428	uint32_t lower;	448	uint32_t lower;
429	uint32_t mask;	449	uint32_t mask;
430	uint32_t length;	450	uint32_t length;
431		451
432	PRINT_BAT("ibat[0]", 528, 529);	452	PRINT_BAT("ibat[0]", 528, 529);
433	PRINT_BAT("ibat[1]", 530, 531);	453	PRINT_BAT("ibat[1]", 530, 531);
434	PRINT_BAT("ibat[2]", 532, 533);	454	PRINT_BAT("ibat[2]", 532, 533);
435	PRINT_BAT("ibat[3]", 534, 535);	455	PRINT_BAT("ibat[3]", 534, 535);
436		456
437	PRINT_BAT("dbat[0]", 536, 537);	457	PRINT_BAT("dbat[0]", 536, 537);
438	PRINT_BAT("dbat[1]", 538, 539);	458	PRINT_BAT("dbat[1]", 538, 539);
439	PRINT_BAT("dbat[2]", 540, 541);	459	PRINT_BAT("dbat[2]", 540, 541);
440	PRINT_BAT("dbat[3]", 542, 543);	460	PRINT_BAT("dbat[3]", 542, 543);
441	}	461	}
442		462
443	/** @}	463	/** @}
444	*/	464	*/
445		465

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(root)/branches/tracing/kernel/arch/ppc32/src/mm/tlb.c – Rev 2787 → 3425