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1
#
1
#
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# Copyright (c) 2003-2004 Jakub Jermar
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# Copyright (c) 2003-2004 Jakub Jermar
3
# All rights reserved.
3
# All rights reserved.
4
#
4
#
5
# Redistribution and use in source and binary forms, with or without
5
# Redistribution and use in source and binary forms, with or without
6
# modification, are permitted provided that the following conditions
6
# modification, are permitted provided that the following conditions
7
# are met:
7
# are met:
8
#
8
#
9
# - Redistributions of source code must retain the above copyright
9
# - Redistributions of source code must retain the above copyright
10
#   notice, this list of conditions and the following disclaimer.
10
#   notice, this list of conditions and the following disclaimer.
11
# - Redistributions in binary form must reproduce the above copyright
11
# - Redistributions in binary form must reproduce the above copyright
12
#   notice, this list of conditions and the following disclaimer in the
12
#   notice, this list of conditions and the following disclaimer in the
13
#   documentation and/or other materials provided with the distribution.
13
#   documentation and/or other materials provided with the distribution.
14
# - The name of the author may not be used to endorse or promote products
14
# - The name of the author may not be used to endorse or promote products
15
#   derived from this software without specific prior written permission.
15
#   derived from this software without specific prior written permission.
16
#
16
#
17
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
#
27
#
28
 
28
 
29
#include <arch/asm/regname.h>
29
#include <arch/asm/regname.h>
30
	
30
	
31
.text
31
.text
32
 
32
 
33
.macro cp0_read reg
33
.macro cp0_read reg
34
	mfc0 $2,\reg
34
	mfc0 $2,\reg
35
	j $31
35
	j $31
36
	nop
36
	nop
37
.endm
37
.endm
38
 
38
 
39
.macro cp0_write reg
39
.macro cp0_write reg
40
	mtc0 $4,\reg
40
	mtc0 $4,\reg
41
	j $31
41
	j $31
42
	nop
42
	nop
43
.endm
43
.endm
44
 
44
 
45
.set noat
45
.set noat
46
.set noreorder
46
.set noreorder
47
.set nomacro
47
.set nomacro
48
 
48
 
49
.global cpu_halt
49
.global cpu_halt
50
cpu_halt:
50
cpu_halt:
51
	j cpu_halt
51
	j cpu_halt
52
	nop
52
	nop
53
 
53
 
54
 
54
 
55
.global memsetb
55
.global memsetb
56
memsetb:
56
memsetb:
57
	j _memsetb
57
	j _memsetb
58
	nop
58
	nop
59
 
59
 
60
 
60
 
61
.global memcpy
61
.global memcpy
62
.global memcpy_from_uspace
62
.global memcpy_from_uspace
63
.global memcpy_to_uspace
63
.global memcpy_to_uspace
64
.global memcpy_from_uspace_failover_address
64
.global memcpy_from_uspace_failover_address
65
.global memcpy_to_uspace_failover_address
65
.global memcpy_to_uspace_failover_address
66
memcpy:
66
memcpy:
67
memcpy_from_uspace:
67
memcpy_from_uspace:
68
memcpy_to_uspace:
68
memcpy_to_uspace:
69
	addiu	$v0,$a1,3
69
	addiu	$v0,$a1,3
70
	li	$v1,-4			# 0xfffffffffffffffc
70
	li	$v1,-4			# 0xfffffffffffffffc
71
	and	$v0,$v0,$v1
71
	and	$v0,$v0,$v1
72
	beq	$a1,$v0,3f
72
	beq	$a1,$v0,3f
73
	move	$t0,$a0
73
	move	$t0,$a0
-
 
74
	move	$t2,$a0			# save dst
74
 
75
 
75
0:
76
0:
76
	beq	$a2,$zero,2f
77
	beq	$a2,$zero,2f
77
	move	$a3,$zero
78
	move	$a3,$zero
78
 
79
 
79
1:
80
1:
80
	addu	$v0,$a1,$a3
81
	addu	$v0,$a1,$a3
81
	lbu	$a0,0($v0)
82
	lbu	$a0,0($v0)
82
	addu	$v1,$t0,$a3
83
	addu	$v1,$t0,$a3
83
	addiu	$a3,$a3,1
84
	addiu	$a3,$a3,1
84
	bne	$a3,$a2,1b
85
	bne	$a3,$a2,1b
85
	sb	$a0,0($v1)
86
	sb	$a0,0($v1)
86
 
87
 
87
2:
88
2:
88
	jr	$ra
89
	jr	$ra
89
	move	$v0,$a1
90
	move	$v0,$t2
90
 
91
 
91
3:
92
3:
92
	addiu	$v0,$a0,3
93
	addiu	$v0,$a0,3
93
	and	$v0,$v0,$v1
94
	and	$v0,$v0,$v1
94
	bne	$a0,$v0,0b
95
	bne	$a0,$v0,0b
95
	srl	$t1,$a2,2
96
	srl	$t1,$a2,2
96
 
97
 
97
	beq	$t1,$zero,5f
98
	beq	$t1,$zero,5f
98
	move	$a3,$zero
99
	move	$a3,$zero
99
 
100
 
100
	move	$a3,$zero
101
	move	$a3,$zero
101
	move	$a0,$zero
102
	move	$a0,$zero
102
4:
103
4:
103
	addu	$v0,$a1,$a0
104
	addu	$v0,$a1,$a0
104
	lw	$v1,0($v0)
105
	lw	$v1,0($v0)
105
	addiu	$a3,$a3,1
106
	addiu	$a3,$a3,1
106
	addu	$v0,$t0,$a0
107
	addu	$v0,$t0,$a0
107
	sw	$v1,0($v0)
108
	sw	$v1,0($v0)
108
	bne	$a3,$t1,4b
109
	bne	$a3,$t1,4b
109
	addiu	$a0,$a0,4
110
	addiu	$a0,$a0,4
110
 
111
 
111
5:
112
5:
112
	andi	$a2,$a2,0x3
113
	andi	$a2,$a2,0x3
113
	beq	$a2,$zero,2b
114
	beq	$a2,$zero,2b
114
	nop
115
	nop
115
 
116
 
116
	sll	$v0,$a3,2
117
	sll	$v0,$a3,2
117
	addu	$t1,$v0,$t0
118
	addu	$t1,$v0,$t0
118
	move	$a3,$zero
119
	move	$a3,$zero
119
	addu	$t0,$v0,$a1
120
	addu	$t0,$v0,$a1
120
6:
121
6:
121
	addu	$v0,$t0,$a3
122
	addu	$v0,$t0,$a3
122
	lbu	$a0,0($v0)
123
	lbu	$a0,0($v0)
123
	addu	$v1,$t1,$a3
124
	addu	$v1,$t1,$a3
124
	addiu	$a3,$a3,1
125
	addiu	$a3,$a3,1
125
	bne	$a3,$a2,6b
126
	bne	$a3,$a2,6b
126
	sb	$a0,0($v1)
127
	sb	$a0,0($v1)
127
 
128
 
128
	jr	$ra
129
	jr	$ra
129
	move	$v0,$a1
130
	move	$v0,$t2
130
 
131
 
131
memcpy_from_uspace_failover_address:
132
memcpy_from_uspace_failover_address:
132
memcpy_to_uspace_failover_address:
133
memcpy_to_uspace_failover_address:
133
	jr	$ra
134
	jr	$ra
134
	move	$v0, $zero
135
	move	$v0, $zero
135
 
136
 
136
 
137
 
137
 
138
 
138
.macro fpu_gp_save reg ctx
139
.macro fpu_gp_save reg ctx
139
	mfc1 $t0,$\reg
140
	mfc1 $t0,$\reg
140
	sw $t0, \reg*4(\ctx)
141
	sw $t0, \reg*4(\ctx)
141
.endm
142
.endm
142
 
143
 
143
.macro fpu_gp_restore reg ctx
144
.macro fpu_gp_restore reg ctx
144
	lw $t0, \reg*4(\ctx)
145
	lw $t0, \reg*4(\ctx)
145
	mtc1 $t0,$\reg
146
	mtc1 $t0,$\reg
146
.endm
147
.endm
147
 
148
 
148
.macro fpu_ct_save reg ctx
149
.macro fpu_ct_save reg ctx
149
	cfc1 $t0,$1
150
	cfc1 $t0,$1
150
	sw $t0, (\reg+32)*4(\ctx)
151
	sw $t0, (\reg+32)*4(\ctx)
151
.endm	
152
.endm	
152
 
153
 
153
.macro fpu_ct_restore reg ctx
154
.macro fpu_ct_restore reg ctx
154
	lw $t0, (\reg+32)*4(\ctx)
155
	lw $t0, (\reg+32)*4(\ctx)
155
	ctc1 $t0,$\reg
156
	ctc1 $t0,$\reg
156
.endm
157
.endm
157
 
158
 
158
 
159
 
159
.global fpu_context_save
160
.global fpu_context_save
160
fpu_context_save:
161
fpu_context_save:
161
#ifdef ARCH_HAS_FPU
162
#ifdef ARCH_HAS_FPU
162
	fpu_gp_save 0,$a0
163
	fpu_gp_save 0,$a0
163
	fpu_gp_save 1,$a0
164
	fpu_gp_save 1,$a0
164
	fpu_gp_save 2,$a0
165
	fpu_gp_save 2,$a0
165
	fpu_gp_save 3,$a0
166
	fpu_gp_save 3,$a0
166
	fpu_gp_save 4,$a0
167
	fpu_gp_save 4,$a0
167
	fpu_gp_save 5,$a0
168
	fpu_gp_save 5,$a0
168
	fpu_gp_save 6,$a0
169
	fpu_gp_save 6,$a0
169
	fpu_gp_save 7,$a0
170
	fpu_gp_save 7,$a0
170
	fpu_gp_save 8,$a0
171
	fpu_gp_save 8,$a0
171
	fpu_gp_save 9,$a0
172
	fpu_gp_save 9,$a0
172
	fpu_gp_save 10,$a0
173
	fpu_gp_save 10,$a0
173
	fpu_gp_save 11,$a0
174
	fpu_gp_save 11,$a0
174
	fpu_gp_save 12,$a0
175
	fpu_gp_save 12,$a0
175
	fpu_gp_save 13,$a0
176
	fpu_gp_save 13,$a0
176
	fpu_gp_save 14,$a0
177
	fpu_gp_save 14,$a0
177
	fpu_gp_save 15,$a0
178
	fpu_gp_save 15,$a0
178
	fpu_gp_save 16,$a0
179
	fpu_gp_save 16,$a0
179
	fpu_gp_save 17,$a0
180
	fpu_gp_save 17,$a0
180
	fpu_gp_save 18,$a0
181
	fpu_gp_save 18,$a0
181
	fpu_gp_save 19,$a0
182
	fpu_gp_save 19,$a0
182
	fpu_gp_save 20,$a0
183
	fpu_gp_save 20,$a0
183
	fpu_gp_save 21,$a0
184
	fpu_gp_save 21,$a0
184
	fpu_gp_save 22,$a0
185
	fpu_gp_save 22,$a0
185
	fpu_gp_save 23,$a0
186
	fpu_gp_save 23,$a0
186
	fpu_gp_save 24,$a0
187
	fpu_gp_save 24,$a0
187
	fpu_gp_save 25,$a0
188
	fpu_gp_save 25,$a0
188
	fpu_gp_save 26,$a0
189
	fpu_gp_save 26,$a0
189
	fpu_gp_save 27,$a0
190
	fpu_gp_save 27,$a0
190
	fpu_gp_save 28,$a0
191
	fpu_gp_save 28,$a0
191
	fpu_gp_save 29,$a0
192
	fpu_gp_save 29,$a0
192
	fpu_gp_save 30,$a0
193
	fpu_gp_save 30,$a0
193
	fpu_gp_save 31,$a0
194
	fpu_gp_save 31,$a0
194
 
195
 
195
	fpu_ct_save 1,$a0
196
	fpu_ct_save 1,$a0
196
	fpu_ct_save 2,$a0
197
	fpu_ct_save 2,$a0
197
	fpu_ct_save 3,$a0
198
	fpu_ct_save 3,$a0
198
	fpu_ct_save 4,$a0
199
	fpu_ct_save 4,$a0
199
	fpu_ct_save 5,$a0
200
	fpu_ct_save 5,$a0
200
	fpu_ct_save 6,$a0
201
	fpu_ct_save 6,$a0
201
	fpu_ct_save 7,$a0
202
	fpu_ct_save 7,$a0
202
	fpu_ct_save 8,$a0
203
	fpu_ct_save 8,$a0
203
	fpu_ct_save 9,$a0
204
	fpu_ct_save 9,$a0
204
	fpu_ct_save 10,$a0
205
	fpu_ct_save 10,$a0
205
	fpu_ct_save 11,$a0
206
	fpu_ct_save 11,$a0
206
	fpu_ct_save 12,$a0
207
	fpu_ct_save 12,$a0
207
	fpu_ct_save 13,$a0
208
	fpu_ct_save 13,$a0
208
	fpu_ct_save 14,$a0
209
	fpu_ct_save 14,$a0
209
	fpu_ct_save 15,$a0
210
	fpu_ct_save 15,$a0
210
	fpu_ct_save 16,$a0
211
	fpu_ct_save 16,$a0
211
	fpu_ct_save 17,$a0
212
	fpu_ct_save 17,$a0
212
	fpu_ct_save 18,$a0
213
	fpu_ct_save 18,$a0
213
	fpu_ct_save 19,$a0
214
	fpu_ct_save 19,$a0
214
	fpu_ct_save 20,$a0
215
	fpu_ct_save 20,$a0
215
	fpu_ct_save 21,$a0
216
	fpu_ct_save 21,$a0
216
	fpu_ct_save 22,$a0
217
	fpu_ct_save 22,$a0
217
	fpu_ct_save 23,$a0
218
	fpu_ct_save 23,$a0
218
	fpu_ct_save 24,$a0
219
	fpu_ct_save 24,$a0
219
	fpu_ct_save 25,$a0
220
	fpu_ct_save 25,$a0
220
	fpu_ct_save 26,$a0
221
	fpu_ct_save 26,$a0
221
	fpu_ct_save 27,$a0
222
	fpu_ct_save 27,$a0
222
	fpu_ct_save 28,$a0
223
	fpu_ct_save 28,$a0
223
	fpu_ct_save 29,$a0
224
	fpu_ct_save 29,$a0
224
	fpu_ct_save 30,$a0
225
	fpu_ct_save 30,$a0
225
	fpu_ct_save 31,$a0
226
	fpu_ct_save 31,$a0
226
#endif		
227
#endif		
227
	j $ra
228
	j $ra
228
	nop
229
	nop
229
 
230
 
230
.global fpu_context_restore
231
.global fpu_context_restore
231
fpu_context_restore:
232
fpu_context_restore:
232
#ifdef ARCH_HAS_FPU
233
#ifdef ARCH_HAS_FPU
233
	fpu_gp_restore 0,$a0
234
	fpu_gp_restore 0,$a0
234
	fpu_gp_restore 1,$a0
235
	fpu_gp_restore 1,$a0
235
	fpu_gp_restore 2,$a0
236
	fpu_gp_restore 2,$a0
236
	fpu_gp_restore 3,$a0
237
	fpu_gp_restore 3,$a0
237
	fpu_gp_restore 4,$a0
238
	fpu_gp_restore 4,$a0
238
	fpu_gp_restore 5,$a0
239
	fpu_gp_restore 5,$a0
239
	fpu_gp_restore 6,$a0
240
	fpu_gp_restore 6,$a0
240
	fpu_gp_restore 7,$a0
241
	fpu_gp_restore 7,$a0
241
	fpu_gp_restore 8,$a0
242
	fpu_gp_restore 8,$a0
242
	fpu_gp_restore 9,$a0
243
	fpu_gp_restore 9,$a0
243
	fpu_gp_restore 10,$a0
244
	fpu_gp_restore 10,$a0
244
	fpu_gp_restore 11,$a0
245
	fpu_gp_restore 11,$a0
245
	fpu_gp_restore 12,$a0
246
	fpu_gp_restore 12,$a0
246
	fpu_gp_restore 13,$a0
247
	fpu_gp_restore 13,$a0
247
	fpu_gp_restore 14,$a0
248
	fpu_gp_restore 14,$a0
248
	fpu_gp_restore 15,$a0
249
	fpu_gp_restore 15,$a0
249
	fpu_gp_restore 16,$a0
250
	fpu_gp_restore 16,$a0
250
	fpu_gp_restore 17,$a0
251
	fpu_gp_restore 17,$a0
251
	fpu_gp_restore 18,$a0
252
	fpu_gp_restore 18,$a0
252
	fpu_gp_restore 19,$a0
253
	fpu_gp_restore 19,$a0
253
	fpu_gp_restore 20,$a0
254
	fpu_gp_restore 20,$a0
254
	fpu_gp_restore 21,$a0
255
	fpu_gp_restore 21,$a0
255
	fpu_gp_restore 22,$a0
256
	fpu_gp_restore 22,$a0
256
	fpu_gp_restore 23,$a0
257
	fpu_gp_restore 23,$a0
257
	fpu_gp_restore 24,$a0
258
	fpu_gp_restore 24,$a0
258
	fpu_gp_restore 25,$a0
259
	fpu_gp_restore 25,$a0
259
	fpu_gp_restore 26,$a0
260
	fpu_gp_restore 26,$a0
260
	fpu_gp_restore 27,$a0
261
	fpu_gp_restore 27,$a0
261
	fpu_gp_restore 28,$a0
262
	fpu_gp_restore 28,$a0
262
	fpu_gp_restore 29,$a0
263
	fpu_gp_restore 29,$a0
263
	fpu_gp_restore 30,$a0
264
	fpu_gp_restore 30,$a0
264
	fpu_gp_restore 31,$a0
265
	fpu_gp_restore 31,$a0
265
 
266
 
266
	fpu_ct_restore 1,$a0
267
	fpu_ct_restore 1,$a0
267
	fpu_ct_restore 2,$a0
268
	fpu_ct_restore 2,$a0
268
	fpu_ct_restore 3,$a0
269
	fpu_ct_restore 3,$a0
269
	fpu_ct_restore 4,$a0
270
	fpu_ct_restore 4,$a0
270
	fpu_ct_restore 5,$a0
271
	fpu_ct_restore 5,$a0
271
	fpu_ct_restore 6,$a0
272
	fpu_ct_restore 6,$a0
272
	fpu_ct_restore 7,$a0
273
	fpu_ct_restore 7,$a0
273
	fpu_ct_restore 8,$a0
274
	fpu_ct_restore 8,$a0
274
	fpu_ct_restore 9,$a0
275
	fpu_ct_restore 9,$a0
275
	fpu_ct_restore 10,$a0
276
	fpu_ct_restore 10,$a0
276
	fpu_ct_restore 11,$a0
277
	fpu_ct_restore 11,$a0
277
	fpu_ct_restore 12,$a0
278
	fpu_ct_restore 12,$a0
278
	fpu_ct_restore 13,$a0
279
	fpu_ct_restore 13,$a0
279
	fpu_ct_restore 14,$a0
280
	fpu_ct_restore 14,$a0
280
	fpu_ct_restore 15,$a0
281
	fpu_ct_restore 15,$a0
281
	fpu_ct_restore 16,$a0
282
	fpu_ct_restore 16,$a0
282
	fpu_ct_restore 17,$a0
283
	fpu_ct_restore 17,$a0
283
	fpu_ct_restore 18,$a0
284
	fpu_ct_restore 18,$a0
284
	fpu_ct_restore 19,$a0
285
	fpu_ct_restore 19,$a0
285
	fpu_ct_restore 20,$a0
286
	fpu_ct_restore 20,$a0
286
	fpu_ct_restore 21,$a0
287
	fpu_ct_restore 21,$a0
287
	fpu_ct_restore 22,$a0
288
	fpu_ct_restore 22,$a0
288
	fpu_ct_restore 23,$a0
289
	fpu_ct_restore 23,$a0
289
	fpu_ct_restore 24,$a0
290
	fpu_ct_restore 24,$a0
290
	fpu_ct_restore 25,$a0
291
	fpu_ct_restore 25,$a0
291
	fpu_ct_restore 26,$a0
292
	fpu_ct_restore 26,$a0
292
	fpu_ct_restore 27,$a0
293
	fpu_ct_restore 27,$a0
293
	fpu_ct_restore 28,$a0
294
	fpu_ct_restore 28,$a0
294
	fpu_ct_restore 29,$a0
295
	fpu_ct_restore 29,$a0
295
	fpu_ct_restore 30,$a0
296
	fpu_ct_restore 30,$a0
296
	fpu_ct_restore 31,$a0
297
	fpu_ct_restore 31,$a0
297
#endif	
298
#endif	
298
	j $ra
299
	j $ra
299
	nop
300
	nop
300
 
301
 
301
 
302
 
302

Generated by GNU Enscript 1.6.6.
303

Generated by GNU Enscript 1.6.6.
303
 
304
 
304
 
305
 
305
 
306