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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * Copyright (c) 2006 Jakub Vana |
3 | * Copyright (c) 2006 Jakub Vana |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | /** @addtogroup ia64mm |
30 | /** @addtogroup ia64mm |
31 | * @{ |
31 | * @{ |
32 | */ |
32 | */ |
33 | /** @file |
33 | /** @file |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/mm/page.h> |
36 | #include <arch/mm/page.h> |
37 | #include <genarch/mm/page_ht.h> |
37 | #include <genarch/mm/page_ht.h> |
38 | #include <mm/asid.h> |
38 | #include <mm/asid.h> |
39 | #include <arch/mm/asid.h> |
39 | #include <arch/mm/asid.h> |
40 | #include <arch/mm/vhpt.h> |
40 | #include <arch/mm/vhpt.h> |
41 | #include <arch/types.h> |
41 | #include <arch/types.h> |
42 | #include <print.h> |
42 | #include <print.h> |
43 | #include <mm/page.h> |
43 | #include <mm/page.h> |
44 | #include <mm/frame.h> |
44 | #include <mm/frame.h> |
45 | #include <config.h> |
45 | #include <config.h> |
46 | #include <panic.h> |
46 | #include <panic.h> |
47 | #include <arch/asm.h> |
47 | #include <arch/asm.h> |
48 | #include <arch/barrier.h> |
48 | #include <arch/barrier.h> |
49 | #include <memstr.h> |
49 | #include <memstr.h> |
- | 50 | #include <align.h> |
|
50 | 51 | ||
51 | static void set_environment(void); |
52 | static void set_environment(void); |
52 | 53 | ||
53 | /** Initialize ia64 virtual address translation subsystem. */ |
54 | /** Initialize ia64 virtual address translation subsystem. */ |
54 | void page_arch_init(void) |
55 | void page_arch_init(void) |
55 | { |
56 | { |
56 | page_mapping_operations = &ht_mapping_operations; |
57 | page_mapping_operations = &ht_mapping_operations; |
57 | pk_disable(); |
58 | pk_disable(); |
58 | set_environment(); |
59 | set_environment(); |
59 | } |
60 | } |
60 | 61 | ||
61 | /** Initialize VHPT and region registers. */ |
62 | /** Initialize VHPT and region registers. */ |
62 | void set_environment(void) |
63 | void set_environment(void) |
63 | { |
64 | { |
64 | region_register rr; |
65 | region_register rr; |
65 | pta_register pta; |
66 | pta_register pta; |
66 | int i; |
67 | int i; |
67 | #ifdef CONFIG_VHPT |
68 | #ifdef CONFIG_VHPT |
68 | uintptr_t vhpt_base; |
69 | uintptr_t vhpt_base; |
69 | #endif |
70 | #endif |
70 | 71 | ||
71 | /* |
72 | /* |
72 | * First set up kernel region register. |
73 | * First set up kernel region register. |
73 | * This is redundant (see start.S) but we keep it here just for sure. |
74 | * This is redundant (see start.S) but we keep it here just for sure. |
74 | */ |
75 | */ |
75 | rr.word = rr_read(VRN_KERNEL); |
76 | rr.word = rr_read(VRN_KERNEL); |
76 | rr.map.ve = 0; /* disable VHPT walker */ |
77 | rr.map.ve = 0; /* disable VHPT walker */ |
77 | rr.map.ps = PAGE_WIDTH; |
78 | rr.map.ps = PAGE_WIDTH; |
78 | rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL); |
79 | rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL); |
79 | rr_write(VRN_KERNEL, rr.word); |
80 | rr_write(VRN_KERNEL, rr.word); |
80 | srlz_i(); |
81 | srlz_i(); |
81 | srlz_d(); |
82 | srlz_d(); |
82 | 83 | ||
83 | /* |
84 | /* |
84 | * And setup the rest of region register. |
85 | * And setup the rest of region register. |
85 | */ |
86 | */ |
86 | for(i = 0; i < REGION_REGISTERS; i++) { |
87 | for(i = 0; i < REGION_REGISTERS; i++) { |
87 | /* skip kernel rr */ |
88 | /* skip kernel rr */ |
88 | if (i == VRN_KERNEL) |
89 | if (i == VRN_KERNEL) |
89 | continue; |
90 | continue; |
90 | 91 | ||
91 | rr.word = rr_read(i); |
92 | rr.word = rr_read(i); |
92 | rr.map.ve = 0; /* disable VHPT walker */ |
93 | rr.map.ve = 0; /* disable VHPT walker */ |
93 | rr.map.rid = RID_KERNEL; |
94 | rr.map.rid = RID_KERNEL; |
94 | rr.map.ps = PAGE_WIDTH; |
95 | rr.map.ps = PAGE_WIDTH; |
95 | rr_write(i, rr.word); |
96 | rr_write(i, rr.word); |
96 | srlz_i(); |
97 | srlz_i(); |
97 | srlz_d(); |
98 | srlz_d(); |
98 | } |
99 | } |
99 | 100 | ||
100 | #ifdef CONFIG_VHPT |
101 | #ifdef CONFIG_VHPT |
101 | vhpt_base = vhpt_set_up(); |
102 | vhpt_base = vhpt_set_up(); |
102 | #endif |
103 | #endif |
103 | /* |
104 | /* |
104 | * Set up PTA register. |
105 | * Set up PTA register. |
105 | */ |
106 | */ |
106 | pta.word = pta_read(); |
107 | pta.word = pta_read(); |
107 | #ifndef CONFIG_VHPT |
108 | #ifndef CONFIG_VHPT |
108 | pta.map.ve = 0; /* disable VHPT walker */ |
109 | pta.map.ve = 0; /* disable VHPT walker */ |
109 | pta.map.base = 0 >> PTA_BASE_SHIFT; |
110 | pta.map.base = 0 >> PTA_BASE_SHIFT; |
110 | #else |
111 | #else |
111 | pta.map.ve = 1; /* enable VHPT walker */ |
112 | pta.map.ve = 1; /* enable VHPT walker */ |
112 | pta.map.base = vhpt_base >> PTA_BASE_SHIFT; |
113 | pta.map.base = vhpt_base >> PTA_BASE_SHIFT; |
113 | #endif |
114 | #endif |
114 | pta.map.vf = 1; /* large entry format */ |
115 | pta.map.vf = 1; /* large entry format */ |
115 | pta.map.size = VHPT_WIDTH; |
116 | pta.map.size = VHPT_WIDTH; |
116 | pta_write(pta.word); |
117 | pta_write(pta.word); |
117 | srlz_i(); |
118 | srlz_i(); |
118 | srlz_d(); |
119 | srlz_d(); |
119 | } |
120 | } |
120 | 121 | ||
121 | /** Calculate address of collision chain from VPN and ASID. |
122 | /** Calculate address of collision chain from VPN and ASID. |
122 | * |
123 | * |
123 | * Interrupts must be disabled. |
124 | * Interrupts must be disabled. |
124 | * |
125 | * |
125 | * @param page Address of virtual page including VRN bits. |
126 | * @param page Address of virtual page including VRN bits. |
126 | * @param asid Address space identifier. |
127 | * @param asid Address space identifier. |
127 | * |
128 | * |
128 | * @return VHPT entry address. |
129 | * @return VHPT entry address. |
129 | */ |
130 | */ |
130 | vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid) |
131 | vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid) |
131 | { |
132 | { |
132 | region_register rr_save, rr; |
133 | region_register rr_save, rr; |
133 | index_t vrn; |
134 | index_t vrn; |
134 | rid_t rid; |
135 | rid_t rid; |
135 | vhpt_entry_t *v; |
136 | vhpt_entry_t *v; |
136 | 137 | ||
137 | vrn = page >> VRN_SHIFT; |
138 | vrn = page >> VRN_SHIFT; |
138 | rid = ASID2RID(asid, vrn); |
139 | rid = ASID2RID(asid, vrn); |
139 | 140 | ||
140 | rr_save.word = rr_read(vrn); |
141 | rr_save.word = rr_read(vrn); |
141 | if (rr_save.map.rid == rid) { |
142 | if (rr_save.map.rid == rid) { |
142 | /* |
143 | /* |
143 | * The RID is already in place, compute thash and return. |
144 | * The RID is already in place, compute thash and return. |
144 | */ |
145 | */ |
145 | v = (vhpt_entry_t *) thash(page); |
146 | v = (vhpt_entry_t *) thash(page); |
146 | return v; |
147 | return v; |
147 | } |
148 | } |
148 | 149 | ||
149 | /* |
150 | /* |
150 | * The RID must be written to some region register. |
151 | * The RID must be written to some region register. |
151 | * To speed things up, register indexed by vrn is used. |
152 | * To speed things up, register indexed by vrn is used. |
152 | */ |
153 | */ |
153 | rr.word = rr_save.word; |
154 | rr.word = rr_save.word; |
154 | rr.map.rid = rid; |
155 | rr.map.rid = rid; |
155 | rr_write(vrn, rr.word); |
156 | rr_write(vrn, rr.word); |
156 | srlz_i(); |
157 | srlz_i(); |
157 | v = (vhpt_entry_t *) thash(page); |
158 | v = (vhpt_entry_t *) thash(page); |
158 | rr_write(vrn, rr_save.word); |
159 | rr_write(vrn, rr_save.word); |
159 | srlz_i(); |
160 | srlz_i(); |
160 | srlz_d(); |
161 | srlz_d(); |
161 | 162 | ||
162 | return v; |
163 | return v; |
163 | } |
164 | } |
164 | 165 | ||
165 | /** Compare ASID and VPN against PTE. |
166 | /** Compare ASID and VPN against PTE. |
166 | * |
167 | * |
167 | * Interrupts must be disabled. |
168 | * Interrupts must be disabled. |
168 | * |
169 | * |
169 | * @param page Address of virtual page including VRN bits. |
170 | * @param page Address of virtual page including VRN bits. |
170 | * @param asid Address space identifier. |
171 | * @param asid Address space identifier. |
171 | * |
172 | * |
172 | * @return True if page and asid match the page and asid of t, false otherwise. |
173 | * @return True if page and asid match the page and asid of t, false otherwise. |
173 | */ |
174 | */ |
174 | bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v) |
175 | bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v) |
175 | { |
176 | { |
176 | region_register rr_save, rr; |
177 | region_register rr_save, rr; |
177 | index_t vrn; |
178 | index_t vrn; |
178 | rid_t rid; |
179 | rid_t rid; |
179 | bool match; |
180 | bool match; |
180 | 181 | ||
181 | ASSERT(v); |
182 | ASSERT(v); |
182 | 183 | ||
183 | vrn = page >> VRN_SHIFT; |
184 | vrn = page >> VRN_SHIFT; |
184 | rid = ASID2RID(asid, vrn); |
185 | rid = ASID2RID(asid, vrn); |
185 | 186 | ||
186 | rr_save.word = rr_read(vrn); |
187 | rr_save.word = rr_read(vrn); |
187 | if (rr_save.map.rid == rid) { |
188 | if (rr_save.map.rid == rid) { |
188 | /* |
189 | /* |
189 | * The RID is already in place, compare ttag with t and return. |
190 | * The RID is already in place, compare ttag with t and return. |
190 | */ |
191 | */ |
191 | return ttag(page) == v->present.tag.tag_word; |
192 | return ttag(page) == v->present.tag.tag_word; |
192 | } |
193 | } |
193 | 194 | ||
194 | /* |
195 | /* |
195 | * The RID must be written to some region register. |
196 | * The RID must be written to some region register. |
196 | * To speed things up, register indexed by vrn is used. |
197 | * To speed things up, register indexed by vrn is used. |
197 | */ |
198 | */ |
198 | rr.word = rr_save.word; |
199 | rr.word = rr_save.word; |
199 | rr.map.rid = rid; |
200 | rr.map.rid = rid; |
200 | rr_write(vrn, rr.word); |
201 | rr_write(vrn, rr.word); |
201 | srlz_i(); |
202 | srlz_i(); |
202 | match = (ttag(page) == v->present.tag.tag_word); |
203 | match = (ttag(page) == v->present.tag.tag_word); |
203 | rr_write(vrn, rr_save.word); |
204 | rr_write(vrn, rr_save.word); |
204 | srlz_i(); |
205 | srlz_i(); |
205 | srlz_d(); |
206 | srlz_d(); |
206 | 207 | ||
207 | return match; |
208 | return match; |
208 | } |
209 | } |
209 | 210 | ||
210 | /** Set up one VHPT entry. |
211 | /** Set up one VHPT entry. |
211 | * |
212 | * |
212 | * @param v VHPT entry to be set up. |
213 | * @param v VHPT entry to be set up. |
213 | * @param page Virtual address of the page mapped by the entry. |
214 | * @param page Virtual address of the page mapped by the entry. |
214 | * @param asid Address space identifier of the address space to which page belongs. |
215 | * @param asid Address space identifier of the address space to which page belongs. |
215 | * @param frame Physical address of the frame to wich page is mapped. |
216 | * @param frame Physical address of the frame to wich page is mapped. |
216 | * @param flags Different flags for the mapping. |
217 | * @param flags Different flags for the mapping. |
217 | */ |
218 | */ |
218 | void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags) |
219 | void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags) |
219 | { |
220 | { |
220 | region_register rr_save, rr; |
221 | region_register rr_save, rr; |
221 | index_t vrn; |
222 | index_t vrn; |
222 | rid_t rid; |
223 | rid_t rid; |
223 | uint64_t tag; |
224 | uint64_t tag; |
224 | 225 | ||
225 | ASSERT(v); |
226 | ASSERT(v); |
226 | 227 | ||
227 | vrn = page >> VRN_SHIFT; |
228 | vrn = page >> VRN_SHIFT; |
228 | rid = ASID2RID(asid, vrn); |
229 | rid = ASID2RID(asid, vrn); |
229 | 230 | ||
230 | /* |
231 | /* |
231 | * Compute ttag. |
232 | * Compute ttag. |
232 | */ |
233 | */ |
233 | rr_save.word = rr_read(vrn); |
234 | rr_save.word = rr_read(vrn); |
234 | rr.word = rr_save.word; |
235 | rr.word = rr_save.word; |
235 | rr.map.rid = rid; |
236 | rr.map.rid = rid; |
236 | rr_write(vrn, rr.word); |
237 | rr_write(vrn, rr.word); |
237 | srlz_i(); |
238 | srlz_i(); |
238 | tag = ttag(page); |
239 | tag = ttag(page); |
239 | rr_write(vrn, rr_save.word); |
240 | rr_write(vrn, rr_save.word); |
240 | srlz_i(); |
241 | srlz_i(); |
241 | srlz_d(); |
242 | srlz_d(); |
242 | 243 | ||
243 | /* |
244 | /* |
244 | * Clear the entry. |
245 | * Clear the entry. |
245 | */ |
246 | */ |
246 | v->word[0] = 0; |
247 | v->word[0] = 0; |
247 | v->word[1] = 0; |
248 | v->word[1] = 0; |
248 | v->word[2] = 0; |
249 | v->word[2] = 0; |
249 | v->word[3] = 0; |
250 | v->word[3] = 0; |
250 | 251 | ||
251 | v->present.p = true; |
252 | v->present.p = true; |
252 | v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE; |
253 | v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE; |
253 | v->present.a = false; /* not accessed */ |
254 | v->present.a = false; /* not accessed */ |
254 | v->present.d = false; /* not dirty */ |
255 | v->present.d = false; /* not dirty */ |
255 | v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL; |
256 | v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL; |
256 | v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ; |
257 | v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ; |
257 | v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0; |
258 | v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0; |
258 | v->present.ppn = frame >> PPN_SHIFT; |
259 | v->present.ppn = frame >> PPN_SHIFT; |
259 | v->present.ed = false; /* exception not deffered */ |
260 | v->present.ed = false; /* exception not deffered */ |
260 | v->present.ps = PAGE_WIDTH; |
261 | v->present.ps = PAGE_WIDTH; |
261 | v->present.key = 0; |
262 | v->present.key = 0; |
262 | v->present.tag.tag_word = tag; |
263 | v->present.tag.tag_word = tag; |
263 | } |
264 | } |
264 | 265 | ||
- | 266 | extern uintptr_t last_frame; |
|
- | 267 | ||
- | 268 | ||
- | 269 | uintptr_t hw_map(uintptr_t physaddr, size_t size) |
|
- | 270 | { |
|
- | 271 | if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) |
|
- | 272 | panic("Unable to map physical memory %p (%d bytes)", physaddr, size) |
|
- | 273 | ||
- | 274 | uintptr_t virtaddr = PA2KA(last_frame); |
|
- | 275 | pfn_t i; |
|
- | 276 | for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) { |
|
- | 277 | uintptr_t addr = PFN2ADDR(i); |
|
- | 278 | page_mapping_insert(AS_KERNEL, virtaddr + addr, physaddr + addr, PAGE_NOT_CACHEABLE | PAGE_WRITE); |
|
- | 279 | } |
|
- | 280 | ||
- | 281 | last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE); |
|
- | 282 | ||
- | 283 | return virtaddr; |
|
- | 284 | } |
|
- | 285 | ||
- | 286 | ||
- | 287 | ||
265 | /** @} |
288 | /** @} |
266 | */ |
289 | */ |
267 | 290 |