WebSVN – HelenOS – Diff – /branches/tracing/kernel/arch/ia64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia64   
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia64_ASM_H_
#define KERN_ia64_ASM_H_
 
#include <config.h>
#include <typedefs.h>
#include <arch/types.h>
#include <arch/register.h>
 
 
 
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
 
static inline void pio_write_8(ioport8_t *port, uint8_t v)
{
    uintptr_t prt = (uintptr_t) port;
 
    *((ioport8_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline void pio_write_16(ioport16_t *port, uint16_t v)
{
    uintptr_t prt = (uintptr_t) port;
 
    *((ioport16_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline void pio_write_32(ioport32_t *port, uint32_t v)
{
    uintptr_t prt = (uintptr_t) port;
 
    *((ioport32_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
 
 
static inline uint8_t pio_read_8(ioport8_t *port)
{
    uintptr_t prt = (uintptr_t) port;
 
    asm volatile ("mf\n" ::: "memory");
 
    return *((ioport8_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12))));
}
 
static inline uint16_t pio_read_16(ioport16_t *port)
{
    uintptr_t prt = (uintptr_t) port;
 
    asm volatile ("mf\n" ::: "memory");
 
    return *((ioport16_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12))));
}
 
static inline uint32_t pio_read_32(ioport32_t *port)
{
    uintptr_t prt = (uintptr_t) port;
 
    asm volatile ("mf\n" ::: "memory");
 
    return *((ioport32_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12))));
}
 
 
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uint64_t v;
 
    //I'm not sure why but this code bad inlines in scheduler, 
    //so THE shifts about 16B and causes kernel panic
    //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
    //return v;
   
    //this code have the same meaning but inlines well
    asm volatile ("mov %0 = r12" : "=r" (v)  );
    return v & (~(STACK_SIZE-1));
}
 
/** Return Processor State Register.
 *
 * @return PSR.
 */
static inline uint64_t psr_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = psr\n" : "=r" (v));
   
    return v;
}
 
/** Read IVA (Interruption Vector Address).
 *
 * @return Return location of interruption vector table.
 */
static inline uint64_t iva_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
   
    return v;
}
 
/** Write IVA (Interruption Vector Address) register.
 *
 * @param v New location of interruption vector table.
 */
static inline void iva_write(uint64_t v)
{
    asm volatile ("mov cr.iva = %0\n" : : "r" (v));
}
 
 
/** Read IVR (External Interrupt Vector Register).
 *
 * @return Highest priority, pending, unmasked external interrupt vector.
 */
static inline uint64_t ivr_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
   
    return v;
}
 
static inline uint64_t cr64_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr64\n" : "=r" (v));
   
    return v;
}
 
 
/** Write ITC (Interval Timer Counter) register.
 *
 * @param v New counter value.
 */
static inline void itc_write(uint64_t v)
{
    asm volatile ("mov ar.itc = %0\n" : : "r" (v));
}
 
/** Read ITC (Interval Timer Counter) register.
 *
 * @return Current counter value.
 */
static inline uint64_t itc_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
   
    return v;
}
 
/** Write ITM (Interval Timer Match) register.
 *
 * @param v New match value.
 */
static inline void itm_write(uint64_t v)
{
    asm volatile ("mov cr.itm = %0\n" : : "r" (v));
}
 
/** Read ITM (Interval Timer Match) register.
 *
 * @return Match value.
 */
static inline uint64_t itm_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
   
    return v;
}
 
/** Read ITV (Interval Timer Vector) register.
 *
 * @return Current vector and mask bit.
 */
static inline uint64_t itv_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
   
    return v;
}
 
/** Write ITV (Interval Timer Vector) register.
 *
 * @param v New vector and mask bit.
 */
static inline void itv_write(uint64_t v)
{
    asm volatile ("mov cr.itv = %0\n" : : "r" (v));
}
 
/** Write EOI (End Of Interrupt) register.
 *
 * @param v This value is ignored.
 */
static inline void eoi_write(uint64_t v)
{
    asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
}
 
/** Read TPR (Task Priority Register).
 *
 * @return Current value of TPR.
 */
static inline uint64_t tpr_read(void)
{
    uint64_t v;
 
    asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
   
    return v;
}
 
/** Write TPR (Task Priority Register).
 *
 * @param v New value of TPR.
 */
static inline void tpr_write(uint64_t v)
{
    asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 */
static ipl_t interrupts_disable(void)
{
    uint64_t v;
   
    asm volatile (
        "mov %0 = psr\n"
        "rsm %1\n"
        : "=r" (v)
        : "i" (PSR_I_MASK)
    );
   
    return (ipl_t) v;
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 */
static ipl_t interrupts_enable(void)
{
    uint64_t v;
   
    asm volatile (
        "mov %0 = psr\n"
        "ssm %1\n"
        ";;\n"
        "srlz.d\n"
        : "=r" (v)
        : "i" (PSR_I_MASK)
    );
   
    return (ipl_t) v;
}
 
/** Restore interrupt priority level.
 *
 * Restore PSR.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl)
{
    if (ipl & PSR_I_MASK)
        (void) interrupts_enable();
    else
        (void) interrupts_disable();
}
 
/** Return interrupt priority level.
 *
 * @return PSR.
 */
static inline ipl_t interrupts_read(void)
{
    return (ipl_t) psr_read();
}
 
/** Disable protection key checking. */
static inline void pk_disable(void)
{
    asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(uint32_t t);
 
extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
    uint64_t, uint64_t);
 
#endif
 
/** @}
 */
 

Rev 3597	Rev 4377
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia64	29	/** @addtogroup ia64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ia64_ASM_H_	35	#ifndef KERN_ia64_ASM_H_
36	#define KERN_ia64_ASM_H_	36	#define KERN_ia64_ASM_H_
37		37
38	#include <config.h>	38	#include <config.h>
-		39	#include <typedefs.h>
39	#include <arch/types.h>	40	#include <arch/types.h>
40	#include <arch/register.h>	41	#include <arch/register.h>
41		42
42	typedef uint64_t ioport_t;	-
43		-
44	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL	43	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
45		44
46	static inline void outb(ioport_t port,uint8_t v)	45	static inline void pio_write_8(ioport8_t *port, uint8_t v)
47	{	46	{
-		47	uintptr_t prt = (uintptr_t) port;
-		48
-		49	((ioport8_t )(IA64_IOSPACE_ADDRESS +
48	((uint8_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;	50	((prt & 0xfff) \| ((prt >> 2) << 12)))) = v;
49		51
50	asm volatile ("mf\n" ::: "memory");	52	asm volatile ("mf\n" ::: "memory");
51	}	53	}
52		54
53	static inline void outw(ioport_t port,uint16_t v)	55	static inline void pio_write_16(ioport16_t *port, uint16_t v)
54	{	56	{
-		57	uintptr_t prt = (uintptr_t) port;
-		58
-		59	((ioport16_t )(IA64_IOSPACE_ADDRESS +
55	((uint16_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;	60	((prt & 0xfff) \| ((prt >> 2) << 12)))) = v;
56		61
57	asm volatile ("mf\n" ::: "memory");	62	asm volatile ("mf\n" ::: "memory");
58	}	63	}
59		64
60	static inline void outl(ioport_t port,uint32_t v)	65	static inline void pio_write_32(ioport32_t *port, uint32_t v)
61	{	66	{
-		67	uintptr_t prt = (uintptr_t) port;
-		68
-		69	((ioport32_t )(IA64_IOSPACE_ADDRESS +
62	((uint32_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;	70	((prt & 0xfff) \| ((prt >> 2) << 12)))) = v;
63		71
64	asm volatile ("mf\n" ::: "memory");	72	asm volatile ("mf\n" ::: "memory");
65	}	73	}
66		74
67		-
68		-
69	static inline uint8_t inb(ioport_t port)	75	static inline uint8_t pio_read_8(ioport8_t *port)
70	{	76	{
-		77	uintptr_t prt = (uintptr_t) port;
-		78
71	asm volatile ("mf\n" ::: "memory");	79	asm volatile ("mf\n" ::: "memory");
72		80
-		81	return ((ioport8_t )(IA64_IOSPACE_ADDRESS +
73	return ((uint8_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 ))));	82	((prt & 0xfff) \| ((prt >> 2) << 12))));
74	}	83	}
75		84
76	static inline uint16_t inw(ioport_t port)	85	static inline uint16_t pio_read_16(ioport16_t *port)
77	{	86	{
-		87	uintptr_t prt = (uintptr_t) port;
-		88
78	asm volatile ("mf\n" ::: "memory");	89	asm volatile ("mf\n" ::: "memory");
79		90
-		91	return ((ioport16_t )(IA64_IOSPACE_ADDRESS +
80	return ((uint16_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) \| ( (port >> 2) << 12 ))));	92	((prt & 0xfff) \| ((prt >> 2) << 12))));
81	}	93	}
82		94
83	static inline uint32_t inl(ioport_t port)	95	static inline uint32_t pio_read_32(ioport32_t *port)
84	{	96	{
-		97	uintptr_t prt = (uintptr_t) port;
-		98
85	asm volatile ("mf\n" ::: "memory");	99	asm volatile ("mf\n" ::: "memory");
86		100
-		101	return ((ioport32_t )(IA64_IOSPACE_ADDRESS +
87	return ((uint32_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 ))));	102	((prt & 0xfff) \| ((prt >> 2) << 12))));
88	}	103	}
89		104
90		-
91		-
92	/** Return base address of current stack	105	/** Return base address of current stack
93	*	106	*
94	* Return the base address of the current stack.	107	* Return the base address of the current stack.
95	* The stack is assumed to be STACK_SIZE long.	108	* The stack is assumed to be STACK_SIZE long.
96	* The stack must start on page boundary.	109	* The stack must start on page boundary.
97	*/	110	*/
98	static inline uintptr_t get_stack_base(void)	111	static inline uintptr_t get_stack_base(void)
99	{	112	{
100	uint64_t v;	113	uint64_t v;
101		114
102	//I'm not sure why but this code bad inlines in scheduler,	115	//I'm not sure why but this code bad inlines in scheduler,
103	//so THE shifts about 16B and causes kernel panic	116	//so THE shifts about 16B and causes kernel panic
104	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));	117	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
105	//return v;	118	//return v;
106		119
107	//this code have the same meaning but inlines well	120	//this code have the same meaning but inlines well
108	asm volatile ("mov %0 = r12" : "=r" (v) );	121	asm volatile ("mov %0 = r12" : "=r" (v) );
109	return v & (~(STACK_SIZE-1));	122	return v & (~(STACK_SIZE-1));
110	}	123	}
111		124
112	/** Return Processor State Register.	125	/** Return Processor State Register.
113	*	126	*
114	* @return PSR.	127	* @return PSR.
115	*/	128	*/
116	static inline uint64_t psr_read(void)	129	static inline uint64_t psr_read(void)
117	{	130	{
118	uint64_t v;	131	uint64_t v;
119		132
120	asm volatile ("mov %0 = psr\n" : "=r" (v));	133	asm volatile ("mov %0 = psr\n" : "=r" (v));
121		134
122	return v;	135	return v;
123	}	136	}
124		137
125	/** Read IVA (Interruption Vector Address).	138	/** Read IVA (Interruption Vector Address).
126	*	139	*
127	* @return Return location of interruption vector table.	140	* @return Return location of interruption vector table.
128	*/	141	*/
129	static inline uint64_t iva_read(void)	142	static inline uint64_t iva_read(void)
130	{	143	{
131	uint64_t v;	144	uint64_t v;
132		145
133	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));	146	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
134		147
135	return v;	148	return v;
136	}	149	}
137		150
138	/** Write IVA (Interruption Vector Address) register.	151	/** Write IVA (Interruption Vector Address) register.
139	*	152	*
140	* @param v New location of interruption vector table.	153	* @param v New location of interruption vector table.
141	*/	154	*/
142	static inline void iva_write(uint64_t v)	155	static inline void iva_write(uint64_t v)
143	{	156	{
144	asm volatile ("mov cr.iva = %0\n" : : "r" (v));	157	asm volatile ("mov cr.iva = %0\n" : : "r" (v));
145	}	158	}
146		159
147		160
148	/** Read IVR (External Interrupt Vector Register).	161	/** Read IVR (External Interrupt Vector Register).
149	*	162	*
150	* @return Highest priority, pending, unmasked external interrupt vector.	163	* @return Highest priority, pending, unmasked external interrupt vector.
151	*/	164	*/
152	static inline uint64_t ivr_read(void)	165	static inline uint64_t ivr_read(void)
153	{	166	{
154	uint64_t v;	167	uint64_t v;
155		168
156	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));	169	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
157		170
158	return v;	171	return v;
159	}	172	}
160		173
161	static inline uint64_t cr64_read(void)	174	static inline uint64_t cr64_read(void)
162	{	175	{
163	uint64_t v;	176	uint64_t v;
164		177
165	asm volatile ("mov %0 = cr64\n" : "=r" (v));	178	asm volatile ("mov %0 = cr64\n" : "=r" (v));
166		179
167	return v;	180	return v;
168	}	181	}
169		182
170		183
171	/** Write ITC (Interval Timer Counter) register.	184	/** Write ITC (Interval Timer Counter) register.
172	*	185	*
173	* @param v New counter value.	186	* @param v New counter value.
174	*/	187	*/
175	static inline void itc_write(uint64_t v)	188	static inline void itc_write(uint64_t v)
176	{	189	{
177	asm volatile ("mov ar.itc = %0\n" : : "r" (v));	190	asm volatile ("mov ar.itc = %0\n" : : "r" (v));
178	}	191	}
179		192
180	/** Read ITC (Interval Timer Counter) register.	193	/** Read ITC (Interval Timer Counter) register.
181	*	194	*
182	* @return Current counter value.	195	* @return Current counter value.
183	*/	196	*/
184	static inline uint64_t itc_read(void)	197	static inline uint64_t itc_read(void)
185	{	198	{
186	uint64_t v;	199	uint64_t v;
187		200
188	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));	201	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
189		202
190	return v;	203	return v;
191	}	204	}
192		205
193	/** Write ITM (Interval Timer Match) register.	206	/** Write ITM (Interval Timer Match) register.
194	*	207	*
195	* @param v New match value.	208	* @param v New match value.
196	*/	209	*/
197	static inline void itm_write(uint64_t v)	210	static inline void itm_write(uint64_t v)
198	{	211	{
199	asm volatile ("mov cr.itm = %0\n" : : "r" (v));	212	asm volatile ("mov cr.itm = %0\n" : : "r" (v));
200	}	213	}
201		214
202	/** Read ITM (Interval Timer Match) register.	215	/** Read ITM (Interval Timer Match) register.
203	*	216	*
204	* @return Match value.	217	* @return Match value.
205	*/	218	*/
206	static inline uint64_t itm_read(void)	219	static inline uint64_t itm_read(void)
207	{	220	{
208	uint64_t v;	221	uint64_t v;
209		222
210	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));	223	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
211		224
212	return v;	225	return v;
213	}	226	}
214		227
215	/** Read ITV (Interval Timer Vector) register.	228	/** Read ITV (Interval Timer Vector) register.
216	*	229	*
217	* @return Current vector and mask bit.	230	* @return Current vector and mask bit.
218	*/	231	*/
219	static inline uint64_t itv_read(void)	232	static inline uint64_t itv_read(void)
220	{	233	{
221	uint64_t v;	234	uint64_t v;
222		235
223	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));	236	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
224		237
225	return v;	238	return v;
226	}	239	}
227		240
228	/** Write ITV (Interval Timer Vector) register.	241	/** Write ITV (Interval Timer Vector) register.
229	*	242	*
230	* @param v New vector and mask bit.	243	* @param v New vector and mask bit.
231	*/	244	*/
232	static inline void itv_write(uint64_t v)	245	static inline void itv_write(uint64_t v)
233	{	246	{
234	asm volatile ("mov cr.itv = %0\n" : : "r" (v));	247	asm volatile ("mov cr.itv = %0\n" : : "r" (v));
235	}	248	}
236		249
237	/** Write EOI (End Of Interrupt) register.	250	/** Write EOI (End Of Interrupt) register.
238	*	251	*
239	* @param v This value is ignored.	252	* @param v This value is ignored.
240	*/	253	*/
241	static inline void eoi_write(uint64_t v)	254	static inline void eoi_write(uint64_t v)
242	{	255	{
243	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));	256	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
244	}	257	}
245		258
246	/** Read TPR (Task Priority Register).	259	/** Read TPR (Task Priority Register).
247	*	260	*
248	* @return Current value of TPR.	261	* @return Current value of TPR.
249	*/	262	*/
250	static inline uint64_t tpr_read(void)	263	static inline uint64_t tpr_read(void)
251	{	264	{
252	uint64_t v;	265	uint64_t v;
253		266
254	asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));	267	asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));
255		268
256	return v;	269	return v;
257	}	270	}
258		271
259	/** Write TPR (Task Priority Register).	272	/** Write TPR (Task Priority Register).
260	*	273	*
261	* @param v New value of TPR.	274	* @param v New value of TPR.
262	*/	275	*/
263	static inline void tpr_write(uint64_t v)	276	static inline void tpr_write(uint64_t v)
264	{	277	{
265	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));	278	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
266	}	279	}
267		280
268	/** Disable interrupts.	281	/** Disable interrupts.
269	*	282	*
270	* Disable interrupts and return previous	283	* Disable interrupts and return previous
271	* value of PSR.	284	* value of PSR.
272	*	285	*
273	* @return Old interrupt priority level.	286	* @return Old interrupt priority level.
274	*/	287	*/
275	static ipl_t interrupts_disable(void)	288	static ipl_t interrupts_disable(void)
276	{	289	{
277	uint64_t v;	290	uint64_t v;
278		291
279	asm volatile (	292	asm volatile (
280	"mov %0 = psr\n"	293	"mov %0 = psr\n"
281	"rsm %1\n"	294	"rsm %1\n"
282	: "=r" (v)	295	: "=r" (v)
283	: "i" (PSR_I_MASK)	296	: "i" (PSR_I_MASK)
284	);	297	);
285		298
286	return (ipl_t) v;	299	return (ipl_t) v;
287	}	300	}
288		301
289	/** Enable interrupts.	302	/** Enable interrupts.
290	*	303	*
291	* Enable interrupts and return previous	304	* Enable interrupts and return previous
292	* value of PSR.	305	* value of PSR.
293	*	306	*
294	* @return Old interrupt priority level.	307	* @return Old interrupt priority level.
295	*/	308	*/
296	static ipl_t interrupts_enable(void)	309	static ipl_t interrupts_enable(void)
297	{	310	{
298	uint64_t v;	311	uint64_t v;
299		312
300	asm volatile (	313	asm volatile (
301	"mov %0 = psr\n"	314	"mov %0 = psr\n"
302	"ssm %1\n"	315	"ssm %1\n"
303	";;\n"	316	";;\n"
304	"srlz.d\n"	317	"srlz.d\n"
305	: "=r" (v)	318	: "=r" (v)
306	: "i" (PSR_I_MASK)	319	: "i" (PSR_I_MASK)
307	);	320	);
308		321
309	return (ipl_t) v;	322	return (ipl_t) v;
310	}	323	}
311		324
312	/** Restore interrupt priority level.	325	/** Restore interrupt priority level.
313	*	326	*
314	* Restore PSR.	327	* Restore PSR.
315	*	328	*
316	* @param ipl Saved interrupt priority level.	329	* @param ipl Saved interrupt priority level.
317	*/	330	*/
318	static inline void interrupts_restore(ipl_t ipl)	331	static inline void interrupts_restore(ipl_t ipl)
319	{	332	{
320	if (ipl & PSR_I_MASK)	333	if (ipl & PSR_I_MASK)
321	(void) interrupts_enable();	334	(void) interrupts_enable();
322	else	335	else
323	(void) interrupts_disable();	336	(void) interrupts_disable();
324	}	337	}
325		338
326	/** Return interrupt priority level.	339	/** Return interrupt priority level.
327	*	340	*
328	* @return PSR.	341	* @return PSR.
329	*/	342	*/
330	static inline ipl_t interrupts_read(void)	343	static inline ipl_t interrupts_read(void)
331	{	344	{
332	return (ipl_t) psr_read();	345	return (ipl_t) psr_read();
333	}	346	}
334		347
335	/** Disable protection key checking. */	348	/** Disable protection key checking. */
336	static inline void pk_disable(void)	349	static inline void pk_disable(void)
337	{	350	{
338	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));	351	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
339	}	352	}
340		353
341	extern void cpu_halt(void);	354	extern void cpu_halt(void);
342	extern void cpu_sleep(void);	355	extern void cpu_sleep(void);
343	extern void asm_delay_loop(uint32_t t);	356	extern void asm_delay_loop(uint32_t t);
344		357
345	extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);	358	extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
-		359	uint64_t, uint64_t);
346		360
347	#endif	361	#endif
348		362
349	/** @}	363	/** @}
350	*/	364	*/
351		365

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(root)/branches/tracing/kernel/arch/ia64/include/asm.h – Rev 3597 → 4377