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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Martin Decky |
2 | * Copyright (C) 2006 Martin Decky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ia32xen |
29 | /** @addtogroup ia32xen |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/pm.h> |
35 | #include <arch/pm.h> |
36 | #include <config.h> |
36 | #include <config.h> |
37 | #include <arch/types.h> |
37 | #include <arch/types.h> |
38 | #include <typedefs.h> |
38 | #include <typedefs.h> |
39 | #include <arch/interrupt.h> |
39 | #include <arch/interrupt.h> |
40 | #include <arch/asm.h> |
40 | #include <arch/asm.h> |
41 | #include <arch/context.h> |
41 | #include <arch/context.h> |
42 | #include <panic.h> |
42 | #include <panic.h> |
43 | #include <arch/mm/page.h> |
43 | #include <arch/mm/page.h> |
44 | #include <mm/slab.h> |
44 | #include <mm/slab.h> |
45 | #include <memstr.h> |
45 | #include <memstr.h> |
46 | #include <arch/boot/boot.h> |
46 | #include <arch/boot/boot.h> |
47 | #include <interrupt.h> |
47 | #include <interrupt.h> |
48 | 48 | ||
49 | /* |
49 | /* |
50 | * Early ia32xen configuration functions and data structures. |
50 | * Early ia32xen configuration functions and data structures. |
51 | */ |
51 | */ |
52 | 52 | ||
53 | /* |
53 | /* |
54 | * We have no use for segmentation so we set up flat mode. In this |
54 | * We have no use for segmentation so we set up flat mode. In this |
55 | * mode, we use, for each privilege level, two segments spanning the |
55 | * mode, we use, for each privilege level, two segments spanning the |
56 | * whole memory. One is for code and one is for data. |
56 | * whole memory. One is for code and one is for data. |
57 | * |
57 | * |
58 | * One is for GS register which holds pointer to the TLS thread |
58 | * One is for GS register which holds pointer to the TLS thread |
59 | * structure in it's base. |
59 | * structure in it's base. |
60 | */ |
60 | */ |
61 | descriptor_t gdt[GDT_ITEMS] = { |
61 | descriptor_t gdt[GDT_ITEMS] = { |
62 | /* NULL descriptor */ |
62 | /* NULL descriptor */ |
63 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
63 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
64 | /* KTEXT descriptor */ |
64 | /* KTEXT descriptor */ |
65 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
65 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
66 | /* KDATA descriptor */ |
66 | /* KDATA descriptor */ |
67 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
67 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
68 | /* UTEXT descriptor */ |
68 | /* UTEXT descriptor */ |
69 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
69 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
70 | /* UDATA descriptor */ |
70 | /* UDATA descriptor */ |
71 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
71 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
72 | /* TSS descriptor - set up will be completed later */ |
72 | /* TSS descriptor - set up will be completed later */ |
73 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
73 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
74 | /* TLS descriptor */ |
74 | /* TLS descriptor */ |
75 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
75 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
76 | }; |
76 | }; |
77 | 77 | ||
78 | static trap_info_t traps[IDT_ITEMS + 1]; |
78 | static trap_info_t traps[IDT_ITEMS + 1]; |
79 | 79 | ||
80 | static tss_t tss; |
80 | static tss_t tss; |
81 | 81 | ||
82 | tss_t *tss_p = NULL; |
82 | tss_t *tss_p = NULL; |
83 | 83 | ||
84 | /* gdtr is changed by kmp before next CPU is initialized */ |
84 | /* gdtr is changed by kmp before next CPU is initialized */ |
85 | ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) }; |
85 | ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) }; |
86 | ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt }; |
86 | ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt }; |
87 | 87 | ||
88 | void gdt_setbase(descriptor_t *d, uintptr_t base) |
88 | void gdt_setbase(descriptor_t *d, uintptr_t base) |
89 | { |
89 | { |
90 | d->base_0_15 = base & 0xffff; |
90 | d->base_0_15 = base & 0xffff; |
91 | d->base_16_23 = ((base) >> 16) & 0xff; |
91 | d->base_16_23 = ((base) >> 16) & 0xff; |
92 | d->base_24_31 = ((base) >> 24) & 0xff; |
92 | d->base_24_31 = ((base) >> 24) & 0xff; |
93 | } |
93 | } |
94 | 94 | ||
95 | void gdt_setlimit(descriptor_t *d, uint32_t limit) |
95 | void gdt_setlimit(descriptor_t *d, uint32_t limit) |
96 | { |
96 | { |
97 | d->limit_0_15 = limit & 0xffff; |
97 | d->limit_0_15 = limit & 0xffff; |
98 | d->limit_16_19 = (limit >> 16) & 0xf; |
98 | d->limit_16_19 = (limit >> 16) & 0xf; |
99 | } |
99 | } |
100 | 100 | ||
101 | void tss_initialize(tss_t *t) |
101 | void tss_initialize(tss_t *t) |
102 | { |
102 | { |
103 | memsetb((uintptr_t) t, sizeof(struct tss), 0); |
103 | memsetb((uintptr_t) t, sizeof(struct tss), 0); |
104 | } |
104 | } |
105 | 105 | ||
106 | static void trap(void) |
106 | static void trap(void) |
107 | { |
107 | { |
108 | } |
108 | } |
109 | 109 | ||
110 | void traps_init(void) |
110 | void traps_init(void) |
111 | { |
111 | { |
112 | index_t i; |
112 | index_t i; |
113 | 113 | ||
114 | for (i = 0; i < IDT_ITEMS; i++) { |
114 | for (i = 0; i < IDT_ITEMS; i++) { |
115 | traps[i].vector = i; |
115 | traps[i].vector = i; |
116 | 116 | ||
117 | if (i == VECTOR_SYSCALL) |
117 | if (i == VECTOR_SYSCALL) |
118 | traps[i].flags = 3; |
118 | traps[i].flags = 3; |
119 | else |
119 | else |
120 | traps[i].flags = 0; |
120 | traps[i].flags = 0; |
121 | 121 | ||
122 | traps[i].cs = XEN_CS; |
122 | traps[i].cs = XEN_CS; |
123 | traps[i].address = trap; |
123 | traps[i].address = trap; |
124 | exc_register(i, "undef", (iroutine) null_interrupt); |
- | |
125 | } |
124 | } |
126 | traps[IDT_ITEMS].vector = 0; |
125 | traps[IDT_ITEMS].vector = 0; |
127 | traps[IDT_ITEMS].flags = 0; |
126 | traps[IDT_ITEMS].flags = 0; |
128 | traps[IDT_ITEMS].cs = 0; |
127 | traps[IDT_ITEMS].cs = 0; |
129 | traps[IDT_ITEMS].address = NULL; |
128 | traps[IDT_ITEMS].address = NULL; |
130 | - | ||
131 | exc_register(13, "gp_fault", (iroutine) gp_fault); |
- | |
132 | exc_register( 7, "nm_fault", (iroutine) nm_fault); |
- | |
133 | exc_register(12, "ss_fault", (iroutine) ss_fault); |
- | |
134 | exc_register(19, "simd_fp", (iroutine) simd_fp_exception); |
- | |
135 | } |
129 | } |
136 | 130 | ||
137 | 131 | ||
138 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
132 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
139 | static void clean_IOPL_NT_flags(void) |
133 | static void clean_IOPL_NT_flags(void) |
140 | { |
134 | { |
141 | // __asm__ volatile ( |
135 | // __asm__ volatile ( |
142 | // "pushfl\n" |
136 | // "pushfl\n" |
143 | // "pop %%eax\n" |
137 | // "pop %%eax\n" |
144 | // "and $0xffff8fff, %%eax\n" |
138 | // "and $0xffff8fff, %%eax\n" |
145 | // "push %%eax\n" |
139 | // "push %%eax\n" |
146 | // "popfl\n" |
140 | // "popfl\n" |
147 | // : : : "eax" |
141 | // : : : "eax" |
148 | // ); |
142 | // ); |
149 | } |
143 | } |
150 | 144 | ||
151 | /* Clean AM(18) flag in CR0 register */ |
145 | /* Clean AM(18) flag in CR0 register */ |
152 | static void clean_AM_flag(void) |
146 | static void clean_AM_flag(void) |
153 | { |
147 | { |
154 | // __asm__ volatile ( |
148 | // __asm__ volatile ( |
155 | // "mov %%cr0, %%eax\n" |
149 | // "mov %%cr0, %%eax\n" |
156 | // "and $0xfffbffff, %%eax\n" |
150 | // "and $0xfffbffff, %%eax\n" |
157 | // "mov %%eax, %%cr0\n" |
151 | // "mov %%eax, %%cr0\n" |
158 | // : : : "eax" |
152 | // : : : "eax" |
159 | // ); |
153 | // ); |
160 | } |
154 | } |
161 | 155 | ||
162 | void pm_init(void) |
156 | void pm_init(void) |
163 | { |
157 | { |
164 | descriptor_t *gdt_p = (descriptor_t *) gdtr.base; |
158 | descriptor_t *gdt_p = (descriptor_t *) gdtr.base; |
165 | 159 | ||
166 | // gdtr_load(&gdtr); |
160 | // gdtr_load(&gdtr); |
167 | 161 | ||
168 | if (config.cpu_active == 1) { |
162 | if (config.cpu_active == 1) { |
169 | traps_init(); |
163 | traps_init(); |
170 | xen_set_trap_table(traps); |
164 | xen_set_trap_table(traps); |
171 | /* |
165 | /* |
172 | * NOTE: bootstrap CPU has statically allocated TSS, because |
166 | * NOTE: bootstrap CPU has statically allocated TSS, because |
173 | * the heap hasn't been initialized so far. |
167 | * the heap hasn't been initialized so far. |
174 | */ |
168 | */ |
175 | tss_p = &tss; |
169 | tss_p = &tss; |
176 | } else { |
170 | } else { |
177 | tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
171 | tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
178 | if (!tss_p) |
172 | if (!tss_p) |
179 | panic("could not allocate TSS\n"); |
173 | panic("could not allocate TSS\n"); |
180 | } |
174 | } |
181 | 175 | ||
182 | // tss_initialize(tss_p); |
176 | // tss_initialize(tss_p); |
183 | 177 | ||
184 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
178 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
185 | gdt_p[TSS_DES].special = 1; |
179 | gdt_p[TSS_DES].special = 1; |
186 | gdt_p[TSS_DES].granularity = 0; |
180 | gdt_p[TSS_DES].granularity = 0; |
187 | 181 | ||
188 | gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); |
182 | gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); |
189 | gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
183 | gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
190 | 184 | ||
191 | /* |
185 | /* |
192 | * As of this moment, the current CPU has its own GDT pointing |
186 | * As of this moment, the current CPU has its own GDT pointing |
193 | * to its own TSS. We just need to load the TR register. |
187 | * to its own TSS. We just need to load the TR register. |
194 | */ |
188 | */ |
195 | // tr_load(selector(TSS_DES)); |
189 | // tr_load(selector(TSS_DES)); |
196 | 190 | ||
197 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
191 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
198 | clean_AM_flag(); /* Disable alignment check */ |
192 | clean_AM_flag(); /* Disable alignment check */ |
199 | } |
193 | } |
200 | 194 | ||
201 | void set_tls_desc(uintptr_t tls) |
195 | void set_tls_desc(uintptr_t tls) |
202 | { |
196 | { |
203 | ptr_16_32_t cpugdtr; |
197 | ptr_16_32_t cpugdtr; |
204 | descriptor_t *gdt_p; |
198 | descriptor_t *gdt_p; |
205 | 199 | ||
206 | gdtr_store(&cpugdtr); |
200 | gdtr_store(&cpugdtr); |
207 | gdt_p = (descriptor_t *) cpugdtr.base; |
201 | gdt_p = (descriptor_t *) cpugdtr.base; |
208 | gdt_setbase(&gdt_p[TLS_DES], tls); |
202 | gdt_setbase(&gdt_p[TLS_DES], tls); |
209 | /* Reload gdt register to update GS in CPU */ |
203 | /* Reload gdt register to update GS in CPU */ |
210 | gdtr_load(&cpugdtr); |
204 | gdtr_load(&cpugdtr); |
211 | } |
205 | } |
212 | 206 | ||
213 | /** @} |
207 | /** @} |
214 | */ |
208 | */ |
215 | 209 |